JPS6312404B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency dividing circuit, particularly a pulse swallow circuit that can directly divide a high frequency signal by an arbitrary half-integer (a number obtained by dividing a positive integer by 2 is called a half-integer) frequency division ratio. Regarding frequency dividing circuits.

A pulse swallow frequency divider circuit has been known as a frequency divider that can divide a high frequency signal by an arbitrary integer frequency division ratio. FIG. 1 shows a basic block diagram of this frequency divider. The variable pre-frequency divider 1 divides the input signal 100 from the input terminal by a frequency division ratio of either P or P+1 corresponding to the logic level of the control signal 200 of “1” or “0”. It is a frequency divider that cycles. This output is applied to a programmable counter 2 that performs a frequency division operation at a frequency division ratio B and a programmable counter 3 that counts an integer A.
The output of the counter 3 is used as a control signal 200, and the output of the counter 2 becomes the output of this frequency divider circuit and is also used to reset the counter 2 itself and the counter 3. However, P, A and B are positive integers and are BA.

Initially, it is assumed that the control signal 200 is "0". When the counter 3 counts A number of (P+1) frequency-divided signals of the input signal 100, it stops and sets the control signal 200 to "0".
to “1”, and the division ratio of frequency divider 1 is set to (P
+1) to P. Counter 2 is (P+
1) After counting A frequency-divided signals, count the P frequency-divided signals and when the total number reaches B, output pulses to return the circuit to the initial state. As a result, it becomes a frequency dividing circuit that counts the input signals as follows: N=(P+1)A+P(B-A)=PB+A...(1) and outputs one output. Here, when A and B are made variable, in order for the overall frequency division ratio given by N above to take continuous integer values, it is sufficient to set A = 0 to P-1, BP-1, and this lower limit Since Amin=0 and Bmin=P-1, the circumferential ratio Nmin becomes Nmin=PBmin+Amin=P(P-1)...(2). From the above explanation, it can be seen that by using the pulse swallow frequency divider circuit, any continuous integer frequency division ratio of P (P-1) or more can be obtained.

The pulse swallow divider circuit described above is often
Used in frequency synthesizers as a programmable counter in PLL circuits. Figure 2 is a block diagram showing the basic configuration of a frequency synthesizer, in which the frequency of a voltage controlled oscillator (VCO) 8 that generates an output signal is divided by a programmable counter 4, and a reference frequency generator 5 with high frequency stability is generated. An error output signal is detected by comparing the output and phase with a phase comparator 6, and is fed back to the VCO 8 via a low-pass filter 7, thereby forming a PLL circuit and controlling the frequency.

When changing the output frequency of such a frequency synthesizer in steps of △F, according to the conventional pulse swallow frequency divider circuit, the frequency division ratio is limited to 1/integer, so the reference frequency r is r=
△F, even if the step of △F is small, △
A reference frequency higher than F cannot be selected, and there are various design constraints. If the reference frequency can now be selected to be twice as high as r=2ΔF, these constraints will be greatly relaxed, and the following effects will be achieved in terms of design. In other words, (i) the frequency division ratio becomes about half, so the loop gain of the PLL circuit easily doubles,
Phase noise can be kept low. (ii) Since the reference frequency is doubled, leakage of the reference signal component from the low-pass filter is reduced, and therefore spurious noise due to residual modulation can be reduced. Alternatively, the design of the low-pass filter can be simplified. (iii) Frequency step △F
When is extremely low, the loop band can be expanded, so that the loop gain can be increased and the response characteristics can be improved.

The object of the present invention is to provide a frequency divider circuit that can obtain the above-mentioned effects by relaxing the constraints on frequency synthesizer design by setting r=2△F, that is, a pulse pulse that can obtain a continuous arbitrary half-integer frequency division ratio. - To provide a thrower frequency divider circuit.

The pulse thrower frequency divider circuit of the present invention has a pair of frequency division ratios P (P is a positive integer) and P-
A first counter that performs a frequency division operation by selecting one of the frequency division ratios of 0.5 or P and P+0.5, and a counter that is cascade-connected to the first counter and has a frequency division ratio of B (B is a positive integer). a second counter that performs a frequency division operation using a frequency division ratio; and a third counter that is cascade-connected to the first counter and is capable of counting a positive integer A that is equal to or smaller than the frequency division ratio B. , the second counter counts the A number of frequency-divided outputs of the first counter according to one of the preselected frequency division ratios, and counts the frequency-divided outputs according to the other frequency division ratio to the remaining B- The frequency division ratio of the first counter is controlled by the information of the second and third counters so that the frequency dividing operation is performed by counting A number of counters.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 3 is a block diagram of an embodiment of the present invention.
2 and 3 are programmable counters, 100 is an input signal, and 200 is a control signal. The variable prefrequency divider 9 converts the input signal 100 from the input terminal to the logic level “1” of the control signal 200.
Or a pair of frequency division ratios P and P-0.5 corresponding to “0”
A first counter, programmable counter 2, which performs a frequency division operation by selecting each of them; a second counter, programmable counter 3, which is cascade-connected to the first counter and performs a frequency division operation at a frequency division ratio of a positive integer B; is a third counter that is cascaded to the first counter and is capable of counting positive integers A that are equal to or less than B. When the programmable counter 2 counts B outputs of the prefix variable divider 9, it generates an output pulse.
and 3 to start the next count, and change the control signal 200 from "1" to "0" so that the variable prefrequency divider 9 performs frequency division operation using the frequency division ratio (P-0.5). Control. When the programmable counter 3 counts A pulses, it outputs a control signal 20.
0 is changed from "0" to "1", and the variable prefrequency divider 9 is controlled to perform a frequency division operation with a frequency division ratio P.

As is clear from the above explanation, according to the circuit of this embodiment, the programmable counter 2 first
-0.5), count A divided outputs with a division ratio of
Next, the frequency divided output by the frequency division ratio of P is divided into the remaining (B-
A) A pulse swallow frequency divider circuit that divides the frequency by counting and dividing the frequency by N _T = (P-0.5) A + P (B-A) = PB-0.5A ...(3) is obtained. It will be done. However, it is BA. Here, when A and B are changed, the conditions for the frequency division ratio given by equation (3) to be any continuous half-integer are A = 0 to 2 (P-1), B2
(P-1) {However, when B=2(P-1), A=0
~2(P-1)}, and the lower limit frequency division ratio is Bmin=2
(P-1), Amax=2(P-1), N _T min=PBmin-0.5Amax =(P-1)(2P-1) ...(4), and (P-1)(2P −1) or more continuous half-integer frequency division ratios can be obtained.

FIG. 4 is a block diagram showing an embodiment of the variable prefrequency divider used in the present invention, in which 10 is an exclusive OR circuit, 11, 12, and 13 are T-type flip-flop circuits that operate at the rising edge of the input signal; 14 is an OR circuit which converts the input signal 100 into a control signal 200.
When is “0”, the frequency is divided by a division ratio of 3.5, and the control signal 2
This is a variable prefrequency divider 9' with P=4 that divides the frequency at a frequency division ratio of 4 when 00 is "1".

FIG. 5 is a time chart explaining the operation of FIG. 4, from the top: signal input 100, input T ₁ of flip-flop circuit (hereinafter abbreviated as FF) 11, output Q ₁ of FF 11, output Q ₂ of FF 12 (divided output), FF12 complementary output ₂ , control signal 200, FF
The signal waveforms of the input T ₃ of the FF 13 and the output Q ₃ of the FF 13 are shown. The waveform shown by the solid line from T ₁ to Q ₃ in the figure is the waveform when the control signal 200 is changed from "0" to "1" at the point when an even number of pulses divided by 1/3.5 is counted, and the waveform shown by the broken line is the waveform shown by the solid line from T 1 to Q 3. shows the waveform for an odd number of cases. It can be seen that in either case, the output signal Q ₂ is frequency-divided to 1/3.5 or 1/4 of the input signal, corresponding to "0" or "1" of the control signal 200. The waveform in the figure is displayed ignoring the time delay between input and output of the flip-flop, so the FF
The output Q ₃ of 13 actually has a time delay of about △t from the figure, and the output of the exclusive OR circuit 10 has a time delay of about △t compared to the figure.
A waveform as shown in T ₁ is obtained. Further, although the control signal 200 is shown to be switched at the same time as the frequency divided output _Q2 , it is not necessarily necessary to switch at the same time. That is, the time point at which the switching signal 200 switches is as shown in the figure.
Even if the waveforms are delayed by a time less than T ₀ than t ₀ , t ₁ , t ₂ , and t ₃ , the same operation is performed without any change in other waveforms. Note that the time chart in FIG. 5 shows the case where the duty ratio of the input signal 100 is 50%, but if it deviates from 50%, the interval between the outputs of _Q2 will deviate slightly from the state shown in the figure. When the duty ratio becomes smaller than 50% and the pulse width becomes shorter by △T, the solid line starts from time t ₀ and becomes 3.5T _0.
−△T, 3.5T ₀ +△T, 4T ₀ , ... In case of broken line
3.5T ₀ −△T, 4T ₀ , 3.5T ₀ +△T, ..., and 3.5T ₀ alternately changes by ±△T, so there is a fraction of 0.5 in the overall frequency division ratio N _T In this case, the frequency-divided output interval also changes by ±△T, which is N _T T ₀ ±△T, but this slight phase modulation due to the 1/2 frequency can be easily removed with a filter, etc. It does not cause any essential problems as a frequency divider.

Although one embodiment of the present invention has been described above, the variable prefrequency divider used in the present invention is not limited to the circuit shown in FIG. It can be constructed with a circuit including a ripple counter circuit, and can be realized not only with an asynchronous ripple counter circuit but also with a synchronous counter circuit. In addition, in the description of the embodiment shown in FIG. 3, the variable prefrequency divider 9 has two frequency division ratios P
and (P-0.5) correspond to "1" and "0" of the control signal 200, respectively, but they may correspond to "0" and "1" of the control signal conversely.
Furthermore, the same effect can be obtained even if the frequency division ratio is P or (P+0.5), and the control signal is not limited to binary signals of logic levels "0" and "1". It may be a pulse signal issued at the time of switching. In addition, in this example,
All of the control signals 200 are configured to be supplied from the counter 3, but the control signal that switches the frequency division ratio at the same time as the counters 2 and 3 are reset is
It is also possible to configure the supply directly from the counter 2 without passing through the counter 3. or,
Of the total B pulses counted by the counter 2, it is configured to first count A (P-0.5) frequency-divided pulses, but the timing of counting A pulses is not limited to the beginning but can be determined at any arbitrary time. It is also clear that the same effect can be obtained regardless of position.

As explained above, according to the pulse swallow frequency divider circuit of the present invention, it is possible to obtain a continuous half-integer frequency division ratio.
When applied to a PLL circuit, the reference frequency can be selected to be twice the frequency step, which has the effect of easing conventional design constraints and easily providing a device with good performance.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram of a conventional pulse swallow frequency divider circuit, Fig. 2 is a block diagram showing the basic configuration of a frequency synthesizer, Fig. 3 is a block diagram of an embodiment of the present invention, and Fig. 4 is a block diagram showing the basic configuration of a frequency synthesizer. FIG. 5 is a block diagram of one embodiment of the variable prefrequency divider used in the present invention, and is a time chart explaining the operation of the circuit shown in FIG. 4. 1... Conventional variable pre-frequency divider, 2, 3 and 4...
...Programmable counter, 5...Reference frequency generator, 6...Phase comparator, 7...Low pass filter, 8
...Voltage controlled oscillator (VCO), 9 and 9'...
Prevariable frequency divider, 10...Exclusive OR circuit, 1
1, 12 and 13...T-type flip-flop circuit, 14...OR circuit, 100...input signal,
200...Control signal.

Claims (1)

[Claims] 1 The first frequency dividing operation is performed by selecting one of a pair of frequency dividing ratios P (P is a positive integer) and P-0.5 (or P and P+0.5) by a control signal. a second counter that is cascade-connected to the first counter and performs frequency dividing operation at a frequency division ratio of B (B is a positive integer); a third counter that can count a positive integer A that is equal to or smaller than B, and the second counter outputs a frequency divided by a preselected frequency division ratio of one of the first counters. The frequency division ratio of the first counter is set to the second and third frequency division ratios so that the frequency division ratio of the first counter is calculated by counting the A number of frequency outputs and counting the remaining B-A frequency division outputs based on the other frequency division ratio to perform the frequency division operation. A pulse swallow frequency divider circuit characterized in that it is controlled by information of a counter.