JPH0743658B2 - Software runaway monitoring timer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to peripheral hardware of a microcomputer, and more particularly to a system / system in which a count value overflows.
The present invention relates to a circuit configuration of a software runaway monitoring timer having a function of generating a reset signal.

[Conventional technology]

Conventionally, this type of timer has been used as shown in FIG.
It was composed of a bit binary counter 5-1 and a reset controller 5-2.

The conventional software runaway monitoring timer shown in FIG. 5 will be described below with reference to a specific example.

First, it is assumed that a low level is applied to the terminal 5-3 when the system is reset to the microcomputer by an externally applied reset signal. Then, at the time of reset, the reset control unit 5-2 outputs a low-level signal. Therefore, the count value of the k-bit binary counter 5-1 having the row active reset terminal is initialized to zero.

The terminal 5-4 is a terminal which becomes a low level when it is executed by an instruction for resetting the (K) bit binary counter by software, and is a high level otherwise.

In this state, a clock having a sufficiently long cycle with respect to the instruction cycle of the microcomputer is applied to the terminals 5-5. Then, when the microcomputer executes some instructions, the count value of the bit binary counter 5-1 is incremented by one. Then, an instruction to reset the (K) -bit binary counter 5-1 before the count value overflows, that is, an instruction to set the terminal 5-4 to the low level is executed.

That is, the (K) -bit binary counter 5-1 is used for every step of the instruction executed by the microcomputer.
It is to put an instruction to reset. As a result, the terminals 5-6 are always kept at the low level. If for some reason (K) bit binary counter 5-1
If is not reset and overflows and the terminal 5-6 goes to a high level, it is determined that the instruction for resetting the k-bit binary counter has not been executed because the software has runaway.

Specifically, as the circuit configuration of the microcomputer,
When the terminals 5-6 become high level, a system reset signal equivalent to the external reset signal applied to the microcomputer is generated.
Therefore, the time that the program continues to run away is only the time until the (K) -bit binary counter 5-1 overflows.

[Problems to be Solved by the Invention]

However, the conventional software runaway monitoring timer of this system has a drawback that it cannot detect runaway in the following cases.

That is, if the runaway endless loop including the instruction to reset the (K) -bit binary counter 5-1 is entered, and the (K) -bit binary counter 5-1 is entered.
Since it does not overflow, it has the drawback that it will continue to run away unless a reset signal is applied from outside the microcomputer.

An object of the present invention is to eliminate the above-mentioned drawbacks and provide a circuit for generating a system reset signal by determining that an instruction being executed is in a runaway infinite loop even when the runaway infinite loop is entered. There is to do.

[Means for Solving the Problems]

The feature of the runaway monitoring timer of the software of the present invention is that the count clock obtained by dividing the system clock is counted, and the count result is reset by a predetermined instruction before overflow, and reset when overflow occurs. In a software runaway monitoring timer having a K-bit binary counter for generating a signal and for performing a system reset on the microcomputer in response to the reset signal at the time of overflow, the K-bit binary counter is The count value output from the Lth bit to the Mth bit (0 ≦ L ≦ M <K) immediately before resetting is stored in the corresponding N-bit shift register at each reset. Shifted in each bit of each of these N-bit shift registers. First reset control means for generating a system reset signal when the respective set values become the same value, or the count value output immediately before the reset is stored in the corresponding D-type flip-flop, and the stored value and the next value are stored. The second reset control for generating the system reset signal when the coincidence signal is supplied to the n-bit binary counter for counting every time the count value immediately before the reset coincides with each other, and reaches a predetermined value. When any one of the means is provided and the runaway of the program is an infinite loop, and the predetermined instruction for resetting the K-bit binary counter is included in the loop, the instruction is executed at least N times. Each time the count value output immediately before the reset is always the same value, the predetermined command executed thereafter According to the present invention, the reset according to the first or second reset control means is invalidated to cause the K-bit binary counter to overflow and exit from the infinite loop. A description will be given with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. In this embodiment, the number K of flip-flops constituting a binary counter is K = 7, and the bit string to be stored in a register among the bit strings of the binary counter. When the lowest bit number L = 1, the highest bit number M = 5 of the bit string stored in the register of the binary counter bit string, and the set value N = 3 of the number of times the binary counter is reset by an instruction are selected. Here is an example.

The terminals 1-5 are set to a low level by externally applying a reset signal to the microcomputer, and are set to a high level when the reset is released.
That is, it becomes low level when the system of the microcomputer is reset. When the terminal 1-5 goes low, the output of the 2-input AND gate 1-6 also goes low. Then, the terminals 1-5 are directly connected to the row active reset terminals, and the D-type flip-flops 1-71 to
1-75, 1-81 to 1-85, 1-91 to 1-95 each constitute a 3-bit register as an example, the Q output of these is low level, and the 2-input AND gate 1- 6
The output value of the 7-bit binary counter 1-1 connected to the reset terminal of low active is 0.
Is reset to. Therefore, 3-input AND gate 1-101-
1-105 and 3-input NOR gates 1-131 to 1-115 all have a low level, and as a result, the outputs of the OR gates 1-121 to 1-125 are high level.
The output of the 5-input NAND gate 1-13 is fixed to the low level and the output of the 2-input NAND gate 1-17 is fixed to the high level.

When the system reset of the microcomputer is released and the logic value of the terminal 1-5 becomes high level, the output of the 2-input AND gate 1-6 becomes high level and the 7-bit binary counter 1-1 and D Mold flip
Flop 1-71 to 1-75, 1-81 to 1-85, 1-91 to 1-95
Reset is released. When reset is released, 7
The bit binary counter 1-1 is started by the clock applied to the terminals 1-4. This clock is
It is a low-frequency clock generated by dividing the system clock. At the same time, the microcomputer starts executing instructions. An instruction set for resetting the 7-bit binary counter 1-1 is prepared in advance in the instruction set of the microcomputer, and the instruction is inserted everywhere in the instruction for performing control and operation, and the 7-bit binary counter is inserted. Reset so that 1-1 does not overflow.

The hardware procedure for resetting is as follows.

When the instruction to reset the 7-bit binary counter 1-1 is executed, the hardware of the microcomputer is configured so that the signals A and B are generated at the timing shown in FIG. 15 and B signal to terminal 1
Give to -14. 7-bit binary counter 1-
Focusing on the first bit of 1, the value of the Q output of the first bit is stored in the D-type flip-flop 1-75 by the signal A, and at the same time, the value of the Q output of the D-type flip-flop 1-75 is D. Type flip-flop 1-85, also 1-85
Are stored in 1-95, respectively. Similar procedure
The same applies to the second to fifth bits. That is, the value of the first bit to the fifth bit of the count value of the 7-bit binary counter 1-1 is transferred to the D-type flip-flops 1-75 to 1-71 by the signal A.

When the transfer is completed, the output of the 5-input NAND gate 1-13 before the signal B goes high is determined. For example,
Now, it is assumed that the Q output values of the D-type flip-flops 1-75 to 1-71 are high, low, high, low, and high in order. Then, the Q of the D-type flip-flops 1-85 to 1-81 and 1-95 to 1-91 is reset by the previous system reset.
Since the output is low level, 2-input OR gate 1-12
The outputs of 5 to 1-121 sequentially become low, high, low, high, and low levels, and the output of the 5-input NAND gate 1-13 becomes high level. Therefore, with signal B, 2-input NAND
The output of the gate 1-17 is low level, and the two inputs are AND
The output of the gates 1-6 also goes low, and 7 bits
The count value of the binary counter 1-1 is reset to 0.

In the unlikely event that the count value of the 7-bit binary counter 1-1 overflows, the sequence of instruction execution of the microcomputer is broken and it is considered that it has run out of control. A system reset is applied to the microcomputer based on the level signal. This is the same as the operation of the conventional circuit. If the program runaway becomes an infinite loop, and the 7-bit binary counter 1
If the instruction to reset -1 is included, the operation is as follows.

The formation of an infinite loop means that the count value when the 7-bit binary counter 1-1 is reset is always the same. Then, when the procedure described so far is taken, the Q outputs of the D-type flip-flops 1-75, 1-85, and 1-95 match the first bit through the infinite loop three times. The same applies to the second bit to the fifth bit. As a result, the outputs of the 2-input OR gates 1-125 to 1-121 are all at the high level and the outputs of the 5-input NAND gate 1-13 are at the low level. Therefore, the signal B of the instruction to reset the 7-bit binary counter 1-1 on the third round of the infinite loop is
Since the other side of the 2-input NAND gate 1-17 to which the signal B is input is low level, the 2-input NAND gate 1
The output of -17 remains high level, the 7-bit binary counter 1-1 is not reset, it overflows, the terminal 1-16 becomes high level, the system is reset, and the infinite loop is exited. You can

In the present embodiment, the fact that the contents of the 0th bit is not stored in the D flip-flop is a measure for making it possible to judge that the time of one infinite loop is an infinite loop even if the time of the loop is slightly different. The reason why the sixth bit is not stored is that the Q output of the sixth bit does not become high level unless it overflows.

A characteristic of this circuit is that if the 7-bit binary counter 1-1 is reset in the same cycle, it is determined that the runaway has occurred even if it is a normal instruction execution sequence. Therefore, the reset command for the 7-bit binary counter 1-1 must be executed irregularly.

FIG. 2 is a circuit diagram of the second embodiment of the present invention, which is an example in which the values of K, L, M and N are selected to be 7, 1, 5 and 5, respectively. .

The terminal 2-5 is normally at high level and at low level at system reset of the microcomputer. When the terminal 2-5 becomes low level, 2-input AND
The output of the gate 2-6 becomes low level and 7 bits
The binary counter 2-1 has a count value of 0, and is composed of the Q outputs of the D-type flip-flops 2-71 to 2-75 and the flip-flops 2-14, 2-15, 2-16. The Q output of the 3-bit binary counter is reset to low level. Therefore, EXNOR gates 2-81-2
The output of −85 is fixed to the high level, the output of the 5-input AND gate is fixed to the high level, and the output of the 3-input NAND gate 2-17 is fixed to the high level.

When the system reset is released, the terminal 2-5 goes high and the 7-bit binary counter 2-1
The D-type flip-flops 2-71 to 2-75 and the binary flip-flops 2-14, 2-15, 2-16 are released from reset. When the reset is released, the 7-bit binary counter 2-1 starts counting by the clock applied to the terminal 2-4. At the same time, micro
The computer begins executing instructions. Then, as in the first embodiment, the 7-bit binary counter 2-1 is used.
Don't overflow due to a reset instruction.

The reset procedure is as follows, unlike the first embodiment.

When the instruction to reset the 7-bit binary counter 2-1 is executed, the hardware of the microcomputer is configured so that the signals A, B and C are generated at the timing shown in FIG. -20, B signal to terminal 2-21,
The C signal is applied to terminals 2-22, respectively. EXNOR2-81 ~
2-85 is the first to fifth bits of the 7-bit binary counter 2-1 that keeps counting with the Q outputs of the D-type flip-flops 2-71 to 2-75 that were previously reset.
The bit value is compared with each other, and if they match, a high level is output.

Therefore, the 5-input AND gate 2-9 outputs a high level when all the bits to be compared match. 5 inputs
If the signal A goes high and then goes low again while the output of the AND gate 2-9 is fixed, if the output of the 5-input AND gate 2-9 is high, 2
The same signal as the signal A appears at the output of the input AND gate 2-11. Also, the output of the 2-input AND gate 2-13 remains at the high level. Conversely, if the output of the 5-input AND gate 2-9 is low level, the output of the 2-input AND gate 2-11 remains low level, and the 2-input AND gate 2
An inverted signal of the signal A appears at the output of -13.

That is, the 7-bit binary counter 2 is generated by the signal A.
If the count value of -1 and the stored value of the D-type flip-flop match, the binary flip-flops 2-14 to 2-2
The count value of the binary counter composed of -16 is set to +1. When they do not match, the count value is reset to 0. Next, with the signal B, the values from the first bit to the fifth bit of the compared count value of the 7-bit binary counter 2-1 are compared with the D-type flip-flop 2-.
Transfer to 71 to 2-75. Finally, the signal C resets the 7-bit binary counter 2-1. Signal C
To the other input of the 2-input NAND gate 2-10, the output of the 3-input NAND gate 2-17 is connected, and the Q outputs of the D-type flip-flops 2-14 to 2-16 are 3 only when the levels are high, low, high
The output of the input NAND gate 2-17 becomes low level. That is, in the normal state, the signal C resets the 7-bit binary counter 2-1.

Here, as in the first embodiment, the program runs away,
Consider the case of entering an infinite loop containing an instruction to reset the bit binary counter 2-1.

When the value of the 1st bit to the 5th bit of the 7-bit binary counter 2-1 is reset 5 times with the same value, the value of the Q output of the binary flip-flops 2-14 to 2-16 sequentially becomes high. , Low, high level, and the output of the 3-input NAND gate 2-17 becomes low level. Then, even if the sixth reset command of the 7-bit binary counter 2-1 is executed, the output of the 2-input NAND gate 2-10 is fixed at the high level, and the 7-bit binary counter 2-1 is fixed. Is not reset but overflows to bring the terminal 2-23 to a high level, and a system reset is applied as in the first embodiment.

In this way, you can exit the infinite loop.

〔The invention's effect〕

As described above, according to the present invention, the K-bit binary counter that keeps counting by the count clock generated by dividing the system clock of the microcomputer is reset by a predetermined instruction, and the L-th binary counter is reset at each reset.
The N-bit corresponding to the count value output immediately before the reset from the bit-th bit to the M-th bit (0 ≦ L ≦ M <K)
First reset control means for generating a system reset signal when the bit values of the N-bit shift registers stored in the shift register have the same value, or the count value output just before the reset, respectively, correspond to each other. Each time the stored value stored in the D-type flip-flop and the count value immediately before the next reset match, the match signal is supplied to the n-bit binary counter to be counted and predetermined. Since either one of the second reset control means for generating a system reset signal when the predetermined value is reached is provided, the runaway of the program becomes an infinite loop, and the K-bit binary counter is reset in the loop. When the predetermined instruction is included, every time this instruction is executed at least N times, If the count value output immediately before reset is always the same value, the reset by the predetermined instruction executed thereafter is invalidated by either the first or second reset control means, and the K-bit binary counter is set. Can overflow. Therefore, in addition to the conventional runaway monitoring timer function, program runaway
Even an infinite loop including an instruction to reset the bit binary counter can be exited from the infinite loop, and a program runaway can be detected.

Therefore, the reliability of the operation of the system controlled by the microcomputer can be further improved.

[Brief description of drawings]

1 and 2 are circuit diagrams of the first and second embodiments of the present invention, FIG. 3 is a timing chart of signals used in the first embodiment, and FIG. 4 is a second embodiment. FIG. 5 is a timing diagram of signals used, and FIG. 5 is a circuit diagram of a conventional example. 1-1 …… 7-bit binary counter 1-2 ……
The first just before the binary counter 1-1 is reset
Register that stores the value of the 5th bit from bit 1-3
...... Reset controller, 1-4 …… Count clock input terminal that divides the system clock, 1-5…
… Terminals that go low when microcomputer system is reset, 1-6 …… 2-input AND gate, 1
-71 to 1-75, 1-81 to 1-85, 1-91 to 1-95 ... When the R terminal becomes low level, the Q output is reset to low level and the signal applied to the C terminal rises. D on the falling edge
D-type flip-flop in which data input from the terminal is transmitted to the Q terminal, 1-101 to 1-105 …… 3 input AND gate, 1-111 to 1-115 …… 3 input NOR gate, 1-121∼
1-125 ... 2-input OR gate, 1-13 ... 5-input NAND gate, 1-14 ... Terminal to which signal B of FIG. 3 is given when executing an instruction to reset the binary counter 1-1 , 1-15 ... the terminal to which the signal A is given in the same manner as 1-14, 1-16 ... the most significant bit Q of the binary counter
Output terminal, 1-17 …… 2 input NAND gate, 2-1 …… 7
Bit binary counter, 2-1 ... Register for storing values of 1st bit to 5th bit immediately before resetting binary counter 2-1 2-3 ... Reset control unit, 2-4 ...... Count clock input terminals, 2
-5 ... a terminal that becomes low level when the system of the microcomputer is reset, 2-6 ... 2-input AND gate, 2-71 to 2-75 ... D-type flip-flop, 2-
81 to 2-85 …… EXNOR gate (inversion of exclusive OR) 2
-9 ... 5-input AND gate, 2-10 ... input NAND gate, 2-11 ... 2-input AND gate, 2-12 ... inverter, 2-13 ... 2-input AND gate, 2-14,2 -15,2-16
...... Inverting related clocks are input to the C and C terminals, and the Q output is inverted at every rising edge of the clock applied to the C terminal. Also, when a low level signal is applied to the R terminal, the Q output becomes low level. Binary flip-flop to be reset, 2-17 …… 3 input NAND gate, 2-18 …… 2 input
NAND gate, 2-19 ... Inverter, 2-20 ... When executing the instruction to reset the binary counter 2-1
The terminal to which the signal A of FIG. 4 is applied, the terminal to which the signal B is applied similarly to 2-21 ... 1-20, the terminal to which the signal C is applied similarly to 2-22 ... 1-20, 2-23 ...... Q output terminal of the most significant bit of the binary counter, 5-1 (K)
Bit-binary counter, 5-2 ... Reset control section, 5-3 ... Terminal that goes to low level at system reset of microcomputer, 5-4 ... Command to reset k-bit binary counter When executed, it temporarily becomes low level, 5-5 ... Count clock input terminal, 5-6 ... Q output of highest bit of binary counter.

Claims (1)

[Claims] 1. A count clock obtained by dividing a system clock is counted and reset by a predetermined instruction before the count result overflows,
K that generates a reset signal when overflow occurs
In a software runaway monitoring timer having a bit binary counter and adapted to perform a system reset on a microcomputer in response to a reset signal at the time of overflow, the K bit binary counter is It is reset, and at every reset, the Lth bit to the Mth bit (0 ≦ L ≦ M <K)
Count value output just before resetting corresponds to N
The first reset control means for generating a system reset signal when the bit values stored in the bit shift register are shifted and the respective bit values of these N bit shift registers have the same value, or the count value output just before the reset is output. This coincidence signal is supplied to the n-bit binary counter and counted each time the stored value stored in the corresponding D-type flip-flop and the stored count value immediately before the next reset coincide with each other. One of the second reset control means for generating a system reset signal when it reaches a predetermined value is provided, and the runaway of the program becomes an infinite loop, and the K-bit binary counter is reset in the loop. If the predetermined instruction to execute is included, this instruction is at least N
If the count value output immediately before the reset is always the same value every time it is executed, the reset by the predetermined command executed thereafter is invalidated by either the first or the second reset control means. The above K-bit binary
A software runaway monitoring timer characterized by overflowing a counter and exiting from the infinite loop.