JPH0738651B2 - FSK demodulation circuit - Google Patents

Description

[Description] The present invention relates to an FSK signal demodulation circuit, and in particular to an FSK demodulation circuit in which deterioration of demodulation characteristics due to noise is reduced, and a phase shifter is used due to the circuit configuration of the phase detector used for FSK demodulation. The FSK demodulation circuit is easy to implement because it does not do so, and it is possible to reduce the occurrence of errors due to noise, etc. Corresponding two orthogonal phase relationships change
Phase detecting means for obtaining a signal output, sampling means for sampling the other signal value by one rising edge and one falling edge of each of the two signal outputs to obtain four binary signals, and the four binary signal A majority decision means for performing a majority decision and generating an output of the decision result, and when the majority decision is made in the majority decision means, the output of the decision result is output as a demodulation signal, and “1” and “0” are given in the majority decision. And a holding unit that holds the immediately preceding determination value when the same number is obtained, and outputs the immediately preceding determination result that was held as a demodulation signal.

[Industrial application field]

The present invention relates to a demodulation circuit of an FSK (Frequency Shift Keying) signal, and in particular, reduces deterioration of demodulation characteristics due to noise.
The present invention relates to an FSK demodulation circuit.

The FSK method is a method of digital FM modulation, and information is transmitted by associating a binary code “0” with a frequency f _{1 and} a frequency “1” with a frequency f ₂ . As a demodulation method for such an FSK signal, a synchronous detection method, a frequency detection method, etc. are known, but when the modulation index (| f ₁ −f ₂ | / signal speed) is large, it is similar to the synchronous detection method. It is possible to perform phase detection without performing carrier wave regeneration in the circuit configuration. The present invention proposes the structure of the phase detector used in this case.

[Conventional technology]

FIG. 9 shows the basic configuration of the FSK demodulation circuit. In FIG. 9, 10 is a hybrid that divides the input signal into two in-phase, 11 is a local oscillator, 12 and 13 are mixers of Ich and Qch, 14 is a hybrid that divides the signal of the local oscillator 11 into two in quadrature phase, and 15 and 16 are low-pass. The filter (LPF), 17 is a phase detector.

If the received signal is r (t) = cos (ωc + aiωd) t ωc: carrier wave ωd: modulation degree ai = + 1 (when data “1”) ai = −1 (when data “0”), this signal becomes Via hybrid 10, mixer 12,
It is input to 13 and is multiplied by sinωct and cosωct respectively, and low-pass filters 15 and 16 are composed of low frequency components Ich and Qch.
As an output of dI (t) = − sin (aiωdt) = − aisinωdt dQ (t) = cos (aiωdt) = cosωdt. Further, the phase detector 17 detects the phase relationship between both outputs and demodulates the reproduction data ai.

In this case, there are several methods for obtaining the original data ai from both outputs dI and dQ, that is, there are several methods for the configuration of the phase detector 17 in FIG. Will be explained.

(1) Method Using Phase Shifter and Multiplier FIG. 10 is a block diagram of a conventional phase detector using a phase shifter and a multiplier, in which 18 is a π / 2 phase shifter and 19 is a multiplication. 20 is a low pass filter (LPF), and 21 is a comparator.

The signal dI ′ obtained by shifting the input dI by π / 2 through the phase shifter 18 is dI ′ = − aisin (ωdt + π / 2) = − aicosωdt By multiplying the signal dI ′ and the input dQ by the multiplier 19, dI ′ · dQ = −ai cos ² ωdt = −ai (l + cos2ωdt) / 2 is obtained. Furthermore, this output dI ′ · dQ is converted to a low-pass filter 20.
The original signal ai can be reproduced by discriminating the positive / negative of the output in which cos2ωdt / 2 is suppressed by smoothing the signal through the comparator 21.

(2) Method using D-type flip-flop FIG. 11 is a block diagram of a conventional phase detector using a D-type flip-flop, wherein 22 and 23 are comparators and 24 is a D-type flip-flop (D-FF). Is.

Further, FIG. 12 is a time chart diagram showing signals of respective parts in the phase detector of FIG.

Both dI and dQ signals are converted into binary signals through comparators 22 and 23, respectively, and outputs Di and Dq are obtained. For example, output Di is D
By applying the output Dq to the clock terminal CK in addition to the data terminal D of the type flip-flop (D-FF) 24, an output obtained by sampling the signal Di at the rising edge of the signal Dq is obtained at the terminal Q. (The relationship between the signals Di and Dq may be reversed.) At this time, the phase relationship between the data terminal D and the clock terminal CK of the D type flip-flop (D-FF) 24 corresponds to the original signal ai in FIG. ), (B) becomes the waveform,
Therefore, the original signal ai is reproduced at the output terminal Q of the D type flip-flop (D-FF) 24.

Of the above conventional methods, a phase shifter and a multiplier are used (1)
This method has a problem that it is difficult to realize the phase shifter 18 that delays the phase of the baseband signal dI. I.e. signal dI
This is because it is difficult to fabricate a phase shifter that accurately shifts the phase by π / 2 at such a low frequency because the frequency of is equal to the modulation degree and is usually about several kHz.

The method (2) using the D-type flip-flop has a high possibility of realization because the circuit configuration is simple, but since it does not have a filter or the like, there is a problem that an error easily occurs in the output Q due to noise.

[Problems to be Solved by the Invention]

The object of the present invention is to solve the above problems of the prior art,
It is an object of the present invention to provide an FSK demodulation circuit that is easy to implement because it does not use a phase shifter because of the circuit configuration of the phase detector used for FSK demodulation and that can reduce the occurrence of errors due to noise and the like.

[Means for Solving the Problems]

FIG. 1 shows the principle configuration of the FSK demodulation circuit of the present invention.

Reference numeral 1 is a phase detection means for multiplying two carrier waves orthogonal to each other with respect to the FSK modulated wave to obtain two orthogonal signal outputs whose phase relationship changes corresponding to the modulation code.

Is ₂₁ to ₂₄ a sampling means, thereby obtaining a respective one of the rising and falling binary signal four by sampling the other of the signal values by the edge of the two signal outputs.

3 is a majority decision means, which makes a majority decision on the four binary signals and outputs an output of the decision result.

Reference numeral 4 is a holding means, and when the majority decision is made by the majority decision means 3, the output of this decision result is outputted as a demodulation signal, and "1" and "0" are the same number in the majority decision. In this case, the previous judgment value is held.

Therefore, the structure of the present invention is as follows. That is,
Phase detection means (1) for obtaining two orthogonal signal outputs whose phase relationship changes corresponding to the modulation code by multiplying two mutually orthogonal carrier waves with respect to the FSK modulated wave, and each of the two signal outputs. and one of the rising and falling edges by sampling the other of the signal values obtained four binary signal sampling means ₍₂₁ to _24), the determination result output by performing the majority decision of the four binary signals And a majority decision judging means (3) for generating a decision result, and when the majority decision is made in the majority decision judging means (3), an output of the decision result is outputted as a demodulation signal, and "1" and "0" are outputted in the majority decision. And a holding means (4) for holding the immediately preceding judgment value when the numbers are the same, and outputting the immediately preceding held judgment result as a demodulation signal.

[Action]

The present invention is applied to the above-mentioned method (2) for explaining the conventional phase detector using the D-type flip-flop shown in FIG. 11, and as shown in FIG.
Binary Di and Dq signals are input from the dQ signal.

FIG. 2 is a diagram showing the relationship between the phase information of both Di and Dq signals and the change points of the original signal data. As shown in FIG. 2, in the Di and Dq signals, when there is a change in the original signal data as shown at point A, the information of the change point of the original signal data is the rising edge of each of the Di and Dq signals. , Are included as phase information at a total of four falling edges. However, in the conventional method, as shown in FIG. 12, only the information of the rising edge of the signal Dq is used, which is not efficient.

FIG. 3 illustrates the phase detection method in the FSK demodulation circuit of the present invention. In the phase detection method of the FSK demodulation circuit of the present invention, the above-mentioned four pieces of phase information are extracted, and the majority of the results is processed to suppress the error occurrence due to noise.

When such a majority decision is made on four data, if the number of data is 4: 0 or 3: 1, there is no problem in the decision, but the processing method when it becomes 2/2 is a problem. Becomes

In FIG. 3, it is assumed that a change occurs in the data at point B, which causes both the Di and Dq signals to change as shown. In this case, the output when the data Dq is sampled at the rising edge of the data Di is I, the inversion of the output when the data Di is sampled at the rising edge of the data Dq is II, and the output when the data Dq is sampled at the falling edge of the data Di Let III be the inversion of data and IV be the output when data Di is sampled at the falling edge of data Dq.
The change in IV is as shown.

Now, comparing the number of each data I to IV being “0” and the number being “1”, 4: 0 → 3: 1 → 2: 2 → 1: before and after the change at point B. It changes like 3 → 0: 4. In this case, 4: 0 and 3: 1 correspond to data “0”, and 1: 3 and 0: 4 correspond to data “1”, for example, to make a correct majority decision. , 2: 2 state cannot generally make a majority decision. Therefore, in this case, if the state immediately before that is held, it is possible to obtain a determination result that correctly represents a change in data, as shown in FIG. In this case, the reproduced data will be delayed, but this will not cause any adverse effect.

Also, due to noise or the like between the data symbols, C in FIG.
As shown in the point, for example, when an error occurs in the data Dq, changes occur in the order of 0: 4 → 1: 3 → 2: 2 → 1: 3 → 0: 4 before and after the point C. In this case As for the majority decision for 2: 2 as well, by holding the state of the data before the error occurrence, the correct decision can be made and the data can be reproduced.

When the number of states of "0" and "1" is the same, the demodulation can be performed using four pieces of phase information by always holding the data state immediately before that.

〔Example〕

FIG. 4 is a block diagram of an FSK demodulation circuit as an embodiment of the present invention, showing a configuration example when a phase detector using the determination method of the present invention is realized by digital processing. In FIG. 4, 31 to 34 are D type flip-flops (D-FF), 35 and 36 are inverters, 37 is a read only memory (ROM), 38 is a delay circuit, and 39 is a latch circuit.

The signal Di as the result of the above-mentioned two-planted phase detection is D
Data terminal D of type flip-flop (D-FF) 31 and clock terminal of D type flip-flop (D-FF) 32
The data terminal D of the D-type flip-flop (D-FF) 33 which is added to CK and inverted through the inverter 35.
And a clock terminal CK of a D type flip-flop (D-FF) 34. The signal Dq is applied to the clock terminal CK of the D-type flip-flop (D-FF) 31 and the data terminal CK of the D-type flip-flop (D-FF) 32, and is inverted via the inverter 36 to be inverted by the D-type flip-flop ( D-FF) 33 clock terminal CK and D-type flip-flop (D-FF) 34 data terminal D.
As a result, each D-type flip-flop (D-FF) 31
The four binary signals I to IV indicating the above-mentioned phase states are generated at Q, Q, and the output terminals of to 34. This signal I-IV
Addresses A3 to A0 in the read-only memory (ROM) 37.
Given as.

The read-only memory (ROM) 37 has addresses A3 to A0.
Corresponding to the combination of "1" and "0" in each of the signals I to IV, the majority decision result data D1 is written, and when any address is designated, it corresponds to this. Output data D1. At the same time, the data D0 which is "0" when the combination of "1" and "0" in the signals I to IV is 2: 2 and is "1" otherwise is output.

The data D1 is added to the data input D of the latch circuit 39 via the delay circuit 38, and the data D0 is the gate terminal G of the latch circuit 39.
Added to. When "1" is given to the gate terminal G, the latch circuit 39 latches the signal of the data terminal D and outputs it.
Output to. On the other hand, when "0" is given to the gate terminal G, the state is not changed and the previous state is maintained. As a result, the signal Di as the binarized phase determination result,
Playback data can be output by making a majority decision on Dq.

In this case, the delay circuit 38 uses the data at the gate terminal G.
After the state change of D0 is completed, data D1 is transferred to data terminal D
It is provided to communicate to. This is because in the 2: 2 state, gating needs to be performed while the data input D of the latch circuit 39 holds the previous state.

FIG. 5 shows a configuration example of a delay circuit, and illustrates a delay circuit configured by using an integrating circuit including a resistor R and a capacitor C.

FIG. 6 shows the contents of the read-only memory (ROM) 37, which can be realized using a 16 × 2 bit ROM.

In the FSK demodulation circuit as one embodiment of the present invention shown in FIG. 4, instead of using the read only memory (ROM) 37, a gate circuit is used in combination so that the majority decision can be made by a logical operation. Is also possible.

FIG. 7 is a block diagram of an FSK demodulation circuit as another embodiment of the present invention, showing a configuration example when a phase detector using the determination method of the present invention is realized by analog processing. In FIG. 7, the same parts as those in FIG. 4 are indicated by the same numbers, 41 is an analog adder circuit, 42 and 43 are comparators, 44 is an exclusive logic circuit, and 45 is an inverter.

In FIG. 7, the signals Di and Dq as the binarized phase detection result described above are used in the same manner as in FIG.
2 binary signals I to IV are generated. The analog adder circuit 41 includes diodes D _{1 to} D ₄ and resistors R _{1 to} R ₅ , and adds the signals I to IV in an analog manner. Signals I to IV are "1" or "0"
Since the analog addition circuit 41 has a predetermined level corresponding to, an average value output is generated from the analog addition circuit 41.

The comparator 42 has an intermediate level between the case where the number of "1" is 3 and the case where it is 2 as the threshold value Vth ₁ , and the comparator 43 has "1".
The number has a level intermediate cases of the 1 2 as the threshold Vth ₂ of. Therefore, the comparator 42 outputs "1" when the number of "1" is 4 and 3, and the comparator 43 outputs "1" when the number of "1" is 4 to 2. Therefore, when the number of "1" is 2, the outputs of both comparators 42 and 43 do not match, and the exclusive OR circuit 44 detects this state and generates an output. Since the output of the exclusive OR circuit 44 is inverted through the inverter 45 and applied to the gate terminal G of the latch circuit 39, the latch circuit 39 holds the previous value in this state. Therefore, the latch circuit 39 is similar to the case of FIG.
It is possible to perform majority decision on the signals Di and Dq as the binarized phase detection result and output the reproduction data.

FIG. 8 shows an example of the error rate characteristic of the FSK demodulation circuit of the present invention. In the case of the conventional method shown by the solid line, the error rate is about 10 ^-2 as compared with the case of the conventional method shown by the broken line. 2d
B improvement is shown. FIG. 8 shows the measured values when the modulation index ≈18.

〔The invention's effect〕

As described above, according to the present invention, a phase shifter is not required in the FSK demodulation circuit due to the circuit configuration of the phase detector, and the phase information included in the two orthogonal phase detection signals is efficiently used for demodulation output. Can be obtained, and the occurrence of errors due to noise or the like can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the principle of the FSK demodulation circuit of the present invention, FIG. 2 is a diagram showing the relationship between the phase information in both Di and Dq signals and the change point of the original signal data, and FIG. 3 is the FSK of the present invention. FIG. 4 is a diagram illustrating a phase detection method in a demodulation circuit, FIG. 4 is a configuration diagram of an FSK demodulation circuit as one embodiment of the present invention, FIG. 5 is a diagram illustrating a configuration example of the delay circuit 38 in FIG. 4, and FIG. FIG. 7 is a diagram showing the contents of a read-only memory (ROM), FIG. 7 is a block diagram of an FSK demodulation circuit as another embodiment of the present invention, and FIG. 8 is an example of error rate characteristics of the FSK demodulation circuit of the present invention. FIG. 9 is a basic configuration diagram of a conventional FSK demodulation circuit, FIG. 10 is a configuration diagram of a conventional phase detector using a phase shifter and a multiplier, and FIG. 11 is a D type flip-flop. Fig. 12 is a block diagram of the conventional phase detector used, and Fig. 12 is a time chart showing the signals of each part in the conventional phase detector shown in Fig. 11. It is a chart. 1 ...... Phase detection means 2 ₁ to 2 ₄ ...... Sampling means 3 ...... Majority decision means 4 ...... Holding means 10,14 ...... Hybrid 11 ...... Local oscillator 12,13,19 ...... Multiplier (mixer) 15 , 16,20 …… Low-pass filter (LPF) 17 …… Phase detector 18 …… Phase shifter 21,22,23,42,43, …… Comparator 24,31,32,33,34 …… D type flip-flop (DF
F) 35,36,45 …… Inverter 37 …… Read only memory (ROM) 38 …… Delay circuit 39 …… Latch circuit 41 …… Analog addition circuit 44 …… Exclusive OR circuit 45 …… Inverter

Claims (1)

[Claims] 1. A phase detection means for multiplying two FSK modulated waves by two orthogonal carrier waves to obtain two orthogonal signal outputs whose phase relationship changes corresponding to a modulation code, and a phase detection means for the two signal outputs. Sampling means for obtaining four binary signals by sampling the signal value of the other one by the rising edge and the falling edge of each, and a majority decision for making a majority decision of the four binary signals and producing an output of the decision result. Means, and when the majority decision is made by the majority decision means, the output of the decision result is output as a demodulation signal, and when the majority decision is “1” and “0” are the same number, the immediately preceding decision value is held. An FSK demodulation circuit, characterized by comprising a holding means for outputting a judgment result immediately before being held as a demodulation signal.