JPS6149865B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital phase modulation method in which the spectrum of a modulated wave is narrow band and the envelope can be constant.

Phase continuous FSK (Frequency Shift Keying)
is AM or band-limited PSK (Phase Shift
Unlike Keying), the envelope of the modulated wave is constant, and the main spectrum is AM-PM even though it is suppressed by the saturation of the output amplifier, e.g. TWT or class C amplifier.
Since it is not affected by conversion, it is an advantageous modulation method for transmission lines that include these nonlinear systems. In particular, phase continuous FSK with modulation index 0.5 is MSK
(Minimum Shift Keying), and is attracting attention as an efficient modulation method with a narrow occupied bandwidth. Moreover, MSK has the advantage that by performing phase plane detection, it is possible to obtain a C/N versus code error rate characteristic that is almost the same as that of two-phase PSK.

By the way, in general, in communication systems that attempt to accommodate many subscribers in a limited radio frequency band, such as mobile communications, (1) spread spectrum systems, in which all subscribers are accommodated in the same broadband frequency band; Effective use of frequencies is achieved by utilizing the S/N improvement characteristics of broadband communications. (2) Narrow the frequency band allocated to each subscriber for effective frequency use. Possible methods include: MSK is a method suitable for (2) because the occupied bandwidth is narrow, but it is difficult to say that it is a sufficient narrowband modulation method when compared with the frequency utilization efficiency of current analog FM modulation methods.

Although the C/N vs. code error rate characteristic is comparable to that of MSK, the occupied bandwidth can be narrower than that of MSK, and the modulated wave has a constant envelope, and the transmission path includes a nonlinear system. For example, as a digital modulation method that satisfies conditions such as the spectrum being less affected by
Frequency Modulation‐F.Jagen IEEE COM—
26 May 1978) is known. However, in this method, the minimum phase shift amount is as small as π/4, so there is a problem that the code error rate increases.

An object of the present invention is to provide a digital phase modulation method that can obtain C/N vs. code error rate characteristics comparable to MSK, have a constant envelope, and make the occupied bandwidth narrower than conventional methods. Our goal is to provide the following.

This invention stores phase shift information or its sine and cosine values corresponding to various combinations of three or more consecutive bits of input data in accordance with specific conditions, and stores them in a memory from this memory in accordance with the input data. A modulated input signal is obtained by selectively reading information, and in particular, relative phase transitions of multiple types stored in memory as phase values or values obtained by sine and cosine transformation of the phase values are obtained. The information is that among the combinations of codes of 3 or more consecutive bits of the input data, the amount of phase shift corresponding to the combination in which all 3 consecutive bits have the same sign is +π/2 or -π/2, and the amount of phase shift of the 3 bits is +π/2 or −π/2. The amount of phase shift corresponding to a combination in which two consecutive bits have the same sign is +φ or -φ (however, 0<φ<
π/2), and the amount of phase shift corresponding to a combination in which two consecutive bits of the three bits have different signs is 2.
It is characterized in that it is determined to be φ-π/2 or π/2-2φ.

The present invention will be explained in detail below with reference to Examples.
FIG. 1 is a block diagram showing a first embodiment of the invention. Serial input data of binary values of "1" and "0" inputted to the input terminal 1 is given to the digital memory 3 together with the data delayed by the delay circuit 2 as an information selection signal. Assuming that the reference clock frequency of input data _{is T} = 1/T, the delay circuit 2 generates two data obtained by delaying the input data by a time T and 2T. Therefore, the information selection signal is expressed by a combination of three consecutive bits of input data. On the other hand, the count value of the ring counter 5 which counts the high speed clock input to the terminal 4 is given to the memory 3 as an address designation signal. The ring counter 5 counts high-speed clocks in synchronization with the reference clock of input data, and after counting N high-speed clocks, the count returns to "1" and restarts counting from the beginning at the next time slot of input data. It is.

In this example, the memory 3 stores in advance eight types of relative phase shift information, each corresponding to a combination (2 ³ =8 types) of consecutive three bits of input data. In this case, it is assumed that the phase transition information in the memory 3 is obtained by predetermining the phase transition curve, performing N samples, and expressing each sample value as a digital value. When input data enters input terminal 1,
Phase shift information corresponding to the combination of consecutive 3-bit input data constituting the information selection signal is selected from the memory 3, and the digital value of the address specified by the address designation signal from the ring counter 5 of the phase shift information is selected. are read out sequentially. The same operation is repeated every time one bit of input data is input, and relative phase shift information is read out from the memory 3.

The phase shift information read out from the memory 3 in this manner is input to the digital adder 6. This adder 6 sequentially adds the final phase of the absolute phase shift information at the time point one slot before the input data to the relative phase shift information inputted from the memory 3 to obtain absolute phase shift information. belongs to. That is, from the adder 6, the time t (=nT) ~
When absolute phase shift information in one time slot of period t+T is output, time t−Δt
(Δt is a minute time), the latch circuit operates, and the output value of the adder 6 at time t−Δt is set to T
Hold for seconds. The digital value held in this latch circuit 7 is the absolute phase at time t, that is, the absolute phase corresponding to the input data in the period t-T to t, which is one slot before the input data in the period t to t+T. Corresponds to the final phase of transition information. The adder 6 outputs the value held by the latch circuit 7 from the memory 3. The momentary values of relative phase shift information corresponding to input data for a period from t to t+T are added to sequentially output digital values indicating absolute phase shift information.

Note that if the adder 6 simply adds the output of the memory 3 to the output of the latch circuit 7,
When the input data becomes "1" or "0" continuously, the adder 6 and the latch circuit 7 enter an overflow state. Here, since the output of the adder 6 is subjected to sine and cosine operations as described later, 2π
There is no problem in taking the value modulo . Therefore, in order to prevent the above-mentioned overflow condition, the latch circuit 7
The values held in are input to digital comparators 8 and 9, and it is determined whether the value is greater than or equal to 2π or less than -2π, respectively. If this value is 2π or more, the output of the comparator 8 drives the digital value generating circuit 10, and from this circuit 10 a digital value corresponding to -2π is input to the adder 6. Also,
If the value held by the latch circuit 7 is less than -2π, the output of the comparator 9 drives the digital value generating circuit 11, and the digital value corresponding to 2π is input from the circuit 11 to the adder 6. Due to this operation, the output of adder 6 becomes “1” as input data.
Alternatively, even if "0" continues, the value is kept within a certain value.

The absolute phase shift information corresponding to the input data output from the adder 6 in this way is input to the sine calculation circuit 12 and the cosine calculation circuit 13,
Its sine and cosine values are calculated. That is, if the absolute phase shift information is θ(t), the outputs of the sine calculation circuit 12 and the cosine calculation circuit 13 are represented by sin θ(t) and cosθ(t), respectively. The outputs of the sine calculation circuit 12 and cosine calculation circuit 13 are converted into analog values by D/A converters 14 and 15, respectively, and further processed by low-pass filters 16 and 17.
After unnecessary components are removed, the signal is input to carrier suppression amplitude modulators (DSB modulators) 18 and 19 as modulated input signals. Here, the modulator 18 has a terminal 20
The carrier wave sinω _c t applied to the modulator 19 is directly applied to the carrier wave sinω c t, and the sinω _c t is applied to the modulator 19 via the π/2 phase shifter 21.
Each is input as a modulated wave. That is, the modulators 18 and 19 each have sinθ(t),
The modulated input signal cosθ(t) is sinω _c t, which is the in-phase component of the carrier wave, and cosω _{c t} , which is the quadrature component of the carrier wave.
t is carrier wave suppression amplitude modulated. Then, the outputs of these modulators 18 and 19 are added by an analog adder 22, and sinθ(t) sinω _c t+cosθ(t)
The digital phase modulated wave cos ω _c t is output from the output terminal 23 .

In the above configuration, eight types of phase shift information stored in the memory 3 are determined as shown in FIG. 2, for example. Figure 2 a to h are three consecutive input data
Relative phase shift information corresponding to each combination of bit data _ao-1 , _ao , ao ₊₁ is shown as a phase change in T seconds of one time slot of central bit data _ao . It is something.

As can be seen from this figure, when the combinations of _ao-1 , _ao , _{and ao+1} all have the same sign, that is, “111” and “000”
In the case of (a) and (b), the absolute value is π/2 in T seconds
When the data a _o of the center bit is “1”, the phase changes by
When it is "0", it is negative. That is, in the case of "111", the phase change is +π/2, and in the case of "000", the phase change is -π/2.

Also, if two consecutive bits of _ao-1 , _ao , _ao+1 have the same sign, that is, the combination of _ao-1 , _ao , _ao+1 is "110", "011", In case of “001”, “100”,
As shown in (c), (d), (e), and (f), the phase changes by an absolute value (π/4<<π/2) in T seconds, and the sign of the change is that a _o is “1”. ” is positive, and “0” is negative. That is, the phase change is + for "110" and "011", and - for "001" and "100".

Furthermore, if consecutive two bits of a _o-1 , a _o , a _o+1 are all different signs, that is, a _o-1 , a _o , a
When the combination of _o+1 is “101” and “010”, the phase changes by 2−π/2 in absolute value as shown in (g) and (h), respectively, and the sign is that a _o is “1”. ” is correct,
When it is "0", it is negative. In other words, 2-π/2 for “010” and π/2-2 for “101”
This results in a phase change of .

The reason for specifying the range of φ as π/4<φ<π/2, especially the reason for setting the lower limit of φ to be larger than π/4, is that if φ is less than π/4, the input data Among combinations of codes of 3 or more consecutive bits, 2 consecutive bits have different codes, i.e. "010" shown in Figure 2a or h in the same figure.
This is because the phase transition corresponding to the combination "101" shown in the figure becomes zero, or the direction of the phase transition becomes opposite to the direction in which the phase transition should originally occur (the transition direction in the case of MSK). For example, when φ=π/4, the amount of phase shift corresponding to g and h in Figure 2 becomes zero, and when φ<π/4, the amount of phase shift corresponding to g in Figure 2 becomes zero. The direction is the negative direction, and the direction of the phase shift corresponding to FIG. 2h is the positive direction. When the direction of the phase shift is reversed as in the latter case,
This makes it difficult for the receiving side to correctly identify the code.

In particular, when a simple demodulation method is adopted in which the modulated signal received on the receiving side is binarized through a frequency discriminator and then the code is identified by level judgment, the direction of the phase shift of the received signal is the same as the original direction. If it is reversed, the polarity of the output of the frequency discriminator will be reversed, causing a problem that the code identification result will be incorrect.

On the other hand, if φ is set larger than π/4 as in the present invention, the phase transition corresponding to the combination of "010" in Figure 2a or "101" in Figure 2h will be in the original phase transition direction. is the same, so the above problem is solved.

Furthermore, by making φ larger than π/4, the eye opening ratio on the receiving side can be increased by that much compared to the conventional TFM method in which φ is set to π/4, and the C/N vs. code error rate characteristic It has the advantage of improving.

Note that the amount of phase shift corresponding to the combination of “010” in Figure 2a or “101” in Figure 2h is 2φ−
The reason for setting π/2, π/2 to 2φ is to specify the eye opening ratio in φ radians (generally, if the eye opening ratio is not specified, the judgment used for code identification on the receiving side (This makes it difficult to set the level.) With conventional MSK, if the input data is “1”, the
There are only two types of phase changes corresponding to a and b in FIG. 2, such as π/2 and -π/2 in the case of "0". In contrast, in the present invention, various types of phase transitions with different amounts of phase change are given to the output digital phase modulated wave according to the combination of, for example, three consecutive bits of the input data. By selecting a small amount of phase change when the sign of input data changes, the overall phase transition state of the digital phase modulated wave becomes smooth.

Figure 3 shows the phase transition of the modulated wave when the input data is “0110111001”, and the dotted line is
MSK, the solid line is for the method of this invention. As can be seen, according to the present invention, the phase transition near 2T, 3T, etc., where the sign of input data changes, is gentler than in the case of MSK.
As a result, the distribution range of the spectrum of the modulated wave also becomes 4th.
As shown in the figure, the band of this invention (solid line) is significantly narrower than that of MSK (dotted line). Therefore, according to the present invention, the occupied bandwidth can be narrowed.

It goes without saying that the width of the spectrum can be appropriately selected by changing the values in the above embodiments.

Furthermore, the digital phase modulated wave obtained by this invention is sinθ(t) sinω _c t + cosθ(t) cosω _c t =√ ² + ²・cos(ω _c t+), and its amplitude is √ ² + ² = 1, so the envelope is always constant. Therefore, even in a transmission path including a nonlinear system, the spectrum of the modulated wave is less affected, and transmission with less distortion is possible.

Note that when the value of in the above description is made smaller than π/2, the synchronous detection output on the receiving side generally becomes smaller and the bit error rate increases. However, even if it is about 1 (radian), the ideal
The C/M is only degraded by 1 dB compared to BPSK, and the C/N vs. code error rate characteristic is almost the same as that of MSK, but this code error rate is smaller than that of the TFM method described above.

Furthermore, according to the above embodiment, since the adder 6 adds the relative phase shift information in the new time slot to the final phase value in the phase shift information one time slot before, absolute phase shift information is obtained. , the phase transition of the modulated wave is always continuous.

As detailed above, the method of this invention is based on MSK
In addition to ensuring C/N code error rate characteristics comparable to that of This has the effect of making it possible to make effective use of frequency resources.

Furthermore, although the above description has been made regarding the case of binary digital phase modulation, the present invention can also be applied to multilevel digital phase modulation. For example, in the case of 4-value input data, there are ²⁶ combinations of consecutive 3 bits, so it is only necessary to generate phase shift information or sine and cosine values from the memories 3 and 3' corresponding to these combinations. .

Further, in the above explanation, phase transition information corresponding to a combination of three consecutive bits of input data is determined, but phase transition information corresponding to a combination of four or more bits, preferably 5 bits, 7 bits, etc., is determined. It is also possible to make the phase transition of the modulated wave even smoother. For example, when determining the phase transition corresponding to a combination of consecutive 5 bits, the first to fourth
The initial phase and final phase of each phase transition may be determined by the combination of bits and the second to fifth bits, and the sign (direction) of the phase transition may be determined by the central third bit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing the stored contents of a memory in the same embodiment, and FIG. 3 shows an example of the phase shift of a modulated wave according to the method of the present invention. FIG. 4 is a diagram showing a comparison between the method of the present invention and the case of MSK, and FIG. 4 is a diagram showing an example of the spectrum of a modulated wave. 2...Delay circuit, 3...Memory, 5...Ring counter, 6...Digital adder, 7...Latch circuit,
8, 9... Digital comparator, 10, 11... Digital value generation circuit, 12... Sine computing circuit, 13... Cosine computing circuit, 14, 15... D/A converter, 16,
17...Low pass filter, 18, 19...DSB modulator,
21...π/2 phase shifter, 22... Analog adder.

Claims (1)

[Claims] 1. A memory that stores in advance multiple types of relative phase shift information corresponding to various combinations of consecutive codes of 3 or more bits of input data, and means for sequentially and selectively reading phase shift information corresponding to the combination according to the combination; and a means for sequentially selectively reading phase shift information corresponding to the combination; In addition, means for obtaining absolute phase shift information, means for obtaining sine and cosine values corresponding to the phase shift information obtained by this means, and in-phase and quadrature of carrier waves using the sine and cosine values obtained by this means. means for amplitude modulating each phase component and then synthesizing it to obtain a digital phase modulated wave, and the plurality of types of relative phase shift information stored in the memory are configured to amplitude-modulate the phase components, respectively, and then synthesize them to obtain a digital phase modulated wave.
Among combinations of codes of bits or more, the amount of phase shift corresponding to a combination in which all three consecutive bits have the same sign is +π/2 or -π/2, and two consecutive bits of the three bits have the same sign. The amount of phase shift corresponding to a certain combination is +φ or −φ (however, π/
4<φ<π/2), and the amount of phase shift corresponding to a combination in which two consecutive bits of the three bits have different signs is determined to be 2φ−π/2 or π/2−2φ. A digital phase modulation method characterized by: