JPH0738105B2 - Active matrix liquid crystal display gradation display drive circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a liquid crystal drive circuit for gradation display of an active matrix liquid crystal display applied to OA equipment.

[Conventional technology]

Computer terminals and portable types of personal computers have become widespread,
A large number of thin and lightweight LCD displays that are easy on the eyes are used. As the contents of information display become more sophisticated, the necessity of color display and gradation display is increasing. There are roughly two types of methods for driving a liquid crystal display, a simple matrix and an active matrix. In the simple matrix system, striped transparent electrodes are provided on the upper and lower glass substrates in the X and Y directions, and intersecting pixels are time-divisionally driven by line-sequential scanning directly from the outside. The active matrix system is a drive system in which a switching element such as a thin film transistor (TFT) is provided in each pixel to statically drive liquid crystal. Although the active matrix method is difficult to manufacture, it has a large contrast ratio, a wide viewing angle, and a high display response speed of 20 to 30 ms.
In addition, the color display is clear and gradation display is easy, and it has high-quality display quality.

As a driving method for displaying a gradation of an active matrix liquid crystal display, a voltage modulation method is generally used in which a voltage corresponding to a gradation level is applied to the liquid crystal through a data line and a TFT by utilizing a voltage transmission characteristic of the liquid crystal. . Conventionally, this kind of data line drive circuit amplifies the display signal of the analog to the drive level of the liquid crystal, samples the amplified display signal for one scanning line by the sample hold circuit, and holds the voltage for one scanning line period. Then, the pixel on one scanning line is driven at a time. Such an analog type data line drive circuit has an L line having about 100 output lines.
SI has been put to practical use. On the other hand, the most frequently used personal computer (640x400 or 640x480 pixels) has a display data transfer rate of 20MHz to 30MHz, which is extremely high at 60 to 90MHz considering the three primary colors of RGB.

A document describing this type of technology is "Hitachi, Catalog, HD66300 (1990)".

[Problems to be Solved by the Invention]

In order to realize high-speed display data with an analog-type data line drive circuit LSI, a high-speed device that makes full use of microfabrication is used, and at the same time, the liquid crystal handles a voltage dynamic range of more than a dozen V. Are required, and high-speed and high-withstand-voltage LSIs that conflict with each other are required, resulting in an extremely expensive LSI. As another conventional method, the display color of a PC is different from that of a TV, and the expression color is, for example,
There is a digital data line drive system that inputs digitized display data because it is limited to simultaneous display of 16 colors out of 4096 colors. "Refer to Hitachi, Catalog, HD66310 (1990)." For example, in the case of 16-gradation display, this method inputs a 16-level gradation level signal from the outside and decodes 4-bit display data to obtain 16-level gradation. A configuration is adopted in which the corresponding level is selected from the level signal and the data line is driven. Since the digital circuit is used as described above, even if the transfer speed of the display data becomes high, the display data of a plurality of systems can be input in parallel until the transfer speed of the drive circuit is met, and parallel processing can be easily performed. However, when this configuration is integrated into an LSI, the number of input terminals is increased to 16 in order to input the gradation signal, and since the display data is digitized, the number of terminals of the LSI is further increasing, There is a drawback that it becomes difficult to mount the LSI. Since the number of input terminals of the gradation signal is 2 ⁿ when the gradation level is ⁿ , it increases rapidly as the gradation level increases. For this reason, the mounting problem of LSI becomes more and more serious.

An object of the present invention is to improve the gradation of an active matrix liquid crystal display by devising a gradation level signal generation circuit, which has a small number of external terminals and can be easily driven even by a liquid crystal display of a computer terminal requiring high-speed data transfer. It is to provide a display driving circuit.

[Means for Solving the Problems]

In order to solve the above problems, the present invention has n sample and hold circuits that sample a gradation reference signal having repetitiveness and hold a voltage, and sequentially sample the gradation reference signal by each sample and hold circuit. To output n gradation level signals, a decoder circuit to decode n-bit digital display data, and select and activate the gradation level signals according to the output of the decoder circuit. A multiplexer circuit for outputting to the data line of the matrix liquid crystal display is provided.

[Action]

The operation of the present invention will be described in detail in the explanation of the operation of the circuit shown in FIG.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. First
The drawing is a block diagram showing an embodiment of the present invention. In FIG. 1, for simplification of description, a drive circuit for displaying 8 gradations will be described. Reference numeral 10 denotes a gradation level generation circuit which outputs gradation level signals V1, V2 ... V8, and shift registers 11 and 8 are provided.
It consists of individual sample and hold circuits 12, 13 ... 19. The shift register 11 has a configuration in which eight registers R1 to R8 are connected in series, and a start pulse signal (SP signal) is sequentially transferred from the register R1 to R2 ... R8 by a clock signal (CLK2 signal). Each sample and hold circuit includes an analog switch 1, a capacitor 2 that holds a voltage, and an analog buffer circuit 3. The analog switches 1 of the sample and hold circuits 12, 13 ... 19 are connected to the registers R1, R2 ... R8 in the shift register 11, respectively, and turned ON / OFF according to the contents of the registers.
It is controlled and samples the gradation reference signal (Vref signal). Capacitor 2 is Vref when analog switch is ON.
Electric charges are supplied from the signal via the analog switch 1. When the analog switch 1 is turned off, it holds the voltage of the Vref signal at the time of sampling. The analog buffer circuit 3 is a buffer circuit for driving the signal held in the capacitor 2 to an external circuit.

Reference numeral 30 is a shift register in which n registers SR1, SR2 ... SRn are connected in series, and is 3-bit digital display data.
D1, D2, D3 are sequentially transferred from SR1 to SR2 ... SRn by the CLK1 signal which is a display data transfer clock. 40 is a latch circuit group consisting of n latch circuits LAT1, LAT2 ... LATn. When the display data for one scanning period is transferred to the shift register 30, the data of the registers SR1, SR2, ... SRn are respectively transferred to the latch circuits LAT1, L by the load pulse signal (LP signal).
AT2: Transferred to LATn every scanning period. Reference numeral 50 is a gradation level selection circuit for selecting one signal from the gradation level signals V1, V2 ... V8 based on 3-bit display data,
It is composed of a decoder circuit 51 and a multiplexer circuit 52. The gradation level selection circuit 50 is provided corresponding to the latch circuits LAT1, LAT2 ... LATn. The decoder circuit 51 decodes the 3-bit display data held in the latch circuit. The multiplexer circuit 52 has a configuration in which eight analog switches are wired-OR, and one of the eight analog switches is turned on based on the decoding result of the decoder circuit 51 to select the corresponding gradation level signal. An analog buffer circuit 60 outputs the selected gradation level signal to the data line of the active matrix liquid crystal display.

FIG. 2 is a timing chart for explaining the operation of the grayscale level generation circuit 10 of FIG. 1 in detail. The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. When the SP signal of 8 clock cycles is input to the gradation level generation circuit 10 as shown in FIG. 2, the contents of the SP signal are sequentially registered in the register R in synchronization with the CLK2 signal.
1, R2 ... Transferred to R8, each register Ri sequentially outputs a pulse for one cycle of the CLK2 signal.

Since the SP signal is a repetitive signal of 8 clock cycles, each register Ri outputs a pulse as shown in FIG. 2 at 8 clock cycles. Consider the triangular wave shown in FIG. 2 as the gradation reference signal Vref signal. When the register R1 outputs a pulse, the analog switch 1 of the sample and hold circuit 12 turns on, and Vref
The electric charge is supplied to the capacitor 2 from the signal line, and when the analog switch 1 is turned off, the electric charge is held in the capacitor 2.

Therefore, the voltage V1 at the time of sampling by the analog switch 1 is held and supplied to the gradation level selection circuit via the analog buffer circuit 3. After that, the registers R2 to R8 output pulses sequentially, and the sample and hold circuits 13 to 19 output Vref.
The signals are sequentially sampled and the gradation level signals V2 to V8 are output. By repeating such an operation every eight clock cycles, the gradation level generation circuit 10 outputs the gradation level signal of eight levels obtained by evenly dividing the voltage value of the Vref signal. The decoder circuit 51 decodes the 3-bit display data and drives the multiplexer circuit 52. For example, if the display data is "011", the decoder circuit 51 3
No. terminal is turned on, only the analog switch of the corresponding multiplexer circuit 52 is turned on, and the gradation level signal V3 is selected. The gradation level signal V3 is supplied to the data line of the liquid crystal display by the analog buffer circuit 60.

Similarly, the gradation level signal is selected by the gradation level selection circuit 50 based on the 3-bit display data. To drive the liquid crystal, alternating current drive in which signals with different polarities are alternately applied is required. In this case, a negative triangular wave may be applied to the Vref signal terminal as shown in the right side of FIG. In the timing example of FIG. 2, the positive / negative polarity of the gradation level signal is inverted every scanning period (1H and Hs are horizontal synchronization signals). However, the operating speed of the TFT used for the active matrix liquid crystal display is slow, and the wiring capacitance and wiring resistance of the data line are large, so that it takes a dozen μs or so for the driving circuit to supply a predetermined charge to the pixel. . For this reason, it is necessary to stabilize the gradation level signal in the first half of one scanning period, and the repetition cycle of the SP signal and the Vref signal needs to be several μs or less.

FIG. 3 is a block diagram showing a second embodiment of the present invention, and is a block diagram without the limiting conditions of the Vref signal and the SP signal shown in FIG. In FIG. 3, only the gradation level generating circuit is shown, and the other circuits are the same as those in the configuration diagram of FIG. 1, so the description thereof will be omitted below. FIG. 4 is a timing chart showing the operation of the gradation level generation circuit of FIG.
The configuration and operation of the second embodiment will be described below with reference to FIGS. 3 and 4. Reference numeral 10 is a gradation level generation circuit, and 11 is a shift register described in the embodiment of FIG. 12-1, 12-2 ...
19-1 and 19-2 are sample hold circuits, each of which is composed of an analog switch 1, a capacitor 2, and an analog buffer circuit 3. Reference numerals 20 and 21 are analog switches, and 20 and 21 form a multiplexer circuit, which is connected to each sample and hold circuit. Selection signal (FR signal) is ON
In case of, the positive gradation level signal (Vi) held in the sample and hold circuits 12-1, 13-1 ... 19-1 is selected and output to the gradation level signal lines V1, V2 ... V8. To do. When the FR signal is OFF, the sample hold circuit 12-2, 13-2 …… 19-2
The gradation level signal (-Vi) of negative polarity held at is selected and output to the gradation level signal lines V1, V2 ... V8. twenty two
Reference numerals 23 and 23 are AND circuits, and 22 and 23 form a switch. When FR signal is ON, sample hold circuit 12-2,1
3-2 …… The analog switch 1 of 19-2 is the shift register 11
ON / OFF control is performed by connecting to each register of and the Vref signal is sampled. The other sample and hold circuit 12-1,1
3-1 …… 19-1 has analog switch 1 and shift register 11
When the FR signal is OFF, it holds the voltage obtained by sampling the Vref signal. When the FR signal is OFF, the reverse operation is performed and the sample and hold circuits 12-1, 13-1 …… 19-1
Sample the Vref signal and sample and hold circuit 12
-2,13-2 …… 19-2 holds the voltage. Next, the operation will be described with reference to FIG. 4 focusing on the gradation level signal V5. Vr
As the ef signal, consider a triangular wave that repeats positive and negative polarities in one scanning period. When the FR signal corresponding to the AC signal of the liquid crystal is ON, the analog hold switch 15-1
Since it is turned off, the voltage V5 obtained by sampling the positive Vref signal in the previous scanning period is held, and this voltage is output as the gradation level signal V5. Sample hold circuit 15
-2 performs sampling operation because the analog switch 1 is controlled by the shift register 11. That is, when a predetermined pulse is input as described with reference to FIG.
The signal is sampled and the voltage −V5 is held. When the FR signal turns off in the next cycle, the sample and hold circuits 15-1 and 15-1
5 to reverse the operation as shown in FIG.
V5 outputs a negative voltage −V5. As described above, in the gradation level generation circuit of FIG. 3, unlike the embodiment of FIG. 1, the gradation level signal to be output to the gradation level selection circuit 50 is determined in the previous scanning period.

Although the Vref signal, the SP signal and the CLK2 signal are supplied from the outside in the embodiment of the present invention, it is obvious that they may be generated internally by using an oscillator or the like. Further, in the configuration of FIG. 3 which is the second embodiment, two sample and hold circuits having the same configuration are used, and while one sample and hold circuit is sampling, the other holds the voltage and selects the gradation level. It is configured to output a gradation level signal to the circuit.
As another configuration, two capacitors and four analog switches are provided (eg NEC PD μ400
Data sheet of 1), while the Vref signal is being supplied to one capacitor, the same operation is performed even if the gradation level signal is output from the voltage held in the other capacitor via the analog buffer circuit. The timing chart of FIG. 4 shows an embodiment in which the polarities of the FR signal and the Vref signal are changed every horizontal scanning period, but it is obvious that the same operation is performed even if the polarities are changed in the vertical scanning period.

〔The invention's effect〕

As is clear from the above description, the gradation display drive circuit based on the digital display data of the present invention has n sample and hold circuits for sampling the gradation reference signal having repeatability and holding the voltage. The sample and hold circuit is provided with a gradation level generation circuit that sequentially samples the gradation reference signal and outputs n gradation level signals, and a gradation level is provided by a decoder circuit and a multiplexer circuit that decodes n-bit digital display data. Since the signal is selected, it has the following advantages. Even if the gradation level increases, the number of external terminals that supply the gradation level signal is 2 n
Since the number of gradation reference signals, the start pulse signal, and the clock signal is only three instead of being increased by multiplication, the number of external terminals can be significantly reduced. Further, since the gradation level generation circuit is composed of a shift register, an analog switch, a capacitor and an analog amplifier, the drive circuit according to the present invention is
It is easy to make LSI. Also, since the number of external terminals is small, the LSI becomes cheaper and the LSI mounting becomes easier. Another advantage is that the display data is digital, so that even when the number of display pixels is large and a high data transfer rate is required, the display data can be input in parallel in multiple systems and processed in parallel. Can handle. The hardware load at this time is a logic circuit of the shift register and the latch circuit group, and even if it is made into an LSI, it is slight. Still another advantage is that so-called γ correction for correcting the voltage value can be easily performed so as to obtain a linear gradation display characteristic in accordance with the voltage transmission characteristic of the liquid crystal. There are two ways to do this. The first method is a method of applying a triangular wave which has been subjected to γ correction to the gradation reference signal. The second method is to change the interval of the clock for sampling the gradation reference signal according to the γ correction value.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of the first embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the gradation level generation circuit in FIG. 1, and FIG. 3 is a second embodiment of the present invention. Circuit configuration diagram, No. 4
The figure is a timing diagram showing the operation of the circuit of FIG. [Description of symbols] 1 ... Analog switch 2 ... Capacitor 3 ... Analog buffer circuit 10 ... Gradation level generation circuit 11 ... Shift register 12 to 19 ... Sample hold circuit 20,21 ... Analog switch 30 ... Shift register 40 ... Latch circuit group 50 ... Gradation level selection circuit 51 ... Decoder circuit 52 ... Multiplexer circuit 60 ... Analog buffer circuit

Claims (2)

[Claims] 1. A gradation reference signal having a repeatability and having n sample and hold circuits for holding a voltage, said gradation reference signal being sequentially sampled by each sample and hold circuit, and having n levels. A gradation level generation circuit that outputs a gradation level signal, a decoder circuit that decodes n-bit digital display data, the gradation level signal is selected according to the output signal of the decoder circuit, and the data of the active matrix liquid crystal display is selected. A gradation display drive circuit for an active matrix liquid crystal display, comprising: a multiplexer circuit for outputting lines. 2. The sample and hold circuit according to claim 1 is provided for two systems for one gradation level signal, and while the gradation level signal is output from the sample and hold circuit of one system by the selection signal, the other The sample-hold circuit of this system is a gradation display drive circuit for an active matrix liquid crystal display, which samples and holds a gradation reference signal.