JPH07319809A - Processor - Google Patents

Abstract

PURPOSE:To prevent the insertion of an unnecessary idle cycle and to reduce the reduction of processing capacity. CONSTITUTION:Respective I/O address spaces are previously set up in respective registers in a register group 12 in accordance with an internal I/O writing instruction outputted from a processor, Idle cycle time corresponding to each I/O address space in the register group 12 is previously set up in a register group 13 based upon the internal I/O writing instruction. Each comparator in a comparator group 15 compares an address (I/O instruction address) on an address bus 100 with the set value of the I/O address space of its corresponding register in the register group 12. A selector 16 selects the idle cycle time set up in a register group 13 in accordance with a compared result signal from the comparator group 15 and sends the selected time to a bus interface unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, and more particularly to a processor having a function of controlling an issue interval of I / O (input / output) instructions.

[0002]

2. Description of the Related Art Conventionally, in this type of processor,
When issuing commands to peripheral I / O devices, I / O
In order to satisfy the time limit of continuous access (hereinafter referred to as recovery time) specified by the O device,
After issuing the I / O command, a certain idle cycle is automatically inserted.

That is, as shown in FIG. 4, the port (P
ort) A (not shown) A / O command is issued (step S1 in FIG. 4), other processing is performed (step S2 in FIG. 4), and then I / O is issued to ports B and C (not shown). Consider a case where a process of issuing an instruction (steps S3 and S4 in FIG. 4) is executed.

In this case, as shown in FIG. 5, after issuing an I / O instruction to the port A (11), an idle cycle (12) fixed for a fixed time is inserted to define the port A. The recovery time (13) has been secured.

Further, even after performing other processing (14),
After issuing I / O commands (15) and (19) to ports B and C in the same manner as the above processing, the idle cycle (1
6) and (20) are inserted to secure the recovery times (17) and (21) specified by the ports B and C. At this time, the idle cycle (16), (20) is the recovery time (1
7) and (21), so unnecessary idle cycles (1
8) and (22) occur.

[0006]

In the conventional processor as described above, a certain idle cycle is automatically inserted after the I / O instruction is issued, so that the idle cycle is defined by the I / O device. If it is much longer than the recovery time, the idle cycle will be inserted unnecessarily, and this will reduce the processing capacity.

Further, when the idle cycle is shorter than the recovery time of the I / O device, a process for gaining time by software (for example, a routine composed of a plurality of NOP instructions) is executed to recover the I / O device. Need to guarantee.

Therefore, an object of the present invention is to solve the above problems, to provide a processor capable of preventing the insertion of an unnecessary idle cycle and reducing the deterioration of the processing capacity.

[0009]

A processor according to the present invention is a processor for inserting an idle cycle for guaranteeing a recovery time of an input / output device after issuing an input / output instruction to the input / output device. Detecting means for detecting to which input / output device the instruction is directed, and output means for selecting and outputting a preset idle cycle time corresponding to the input / output device detected by the detection result. .

Another processor according to the present invention is a processor which inserts an idle cycle for guaranteeing a recovery time of the input / output device after issuing an input / output instruction to the input / output device, and which is configured to set an address of the input / output device. Holding means for holding in advance, storing means for storing an idle cycle time preset corresponding to the input / output device, comparing means for comparing the address of the input / output instruction with the contents of the holding means, Selecting means for selecting and outputting the idle cycle time corresponding to the input / output device for which a match is detected by the comparing means from the idle cycle times stored in the storing means.

Another processor according to the present invention is a processor for inserting an idle cycle for guaranteeing a recovery time of the input / output device after the input / output instruction is issued to the input / output device, and the idle cycle is the same. Holding means for holding a plurality of address spaces each of which includes an address of each output device, storage means for storing a preset idle cycle time for each of the plurality of address spaces, and addresses for the input / output instructions are Detection means for detecting which one of the address spaces it belongs to, and selection for selecting and outputting the idle cycle time corresponding to the address space detected by the detection means from the idle cycle times stored in the storage means. And means.

[0012]

The I / O address space consisting of the addresses of I / O devices is held in the register group in advance, and each I / O address space is made to correspond to the I / O address space held in this register group.
The idle cycle time for guaranteeing the recovery time of the / O device is stored in advance in another register group.

The I / O address space held in the register group is compared with the address of the I / O instruction by the comparator group, and another I / O address space corresponding to the I / O address space in which the match is detected by the comparator group is compared. The idle cycle time of the register group is selected by the selector, and the idle cycle time selected by the selector is output to the bus interface unit which inserts the idle cycle.

As a result, the idle cycle inserted after the I / O instruction is issued can be selected for each arbitrary I / O address space. Therefore, it becomes possible to prevent the insertion of unnecessary idle cycles, and it is possible to mitigate the decrease in the processing capability of the processor.

[0015]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a processor according to an exemplary embodiment of the present invention includes an idle cycle control signal generation circuit (hereinafter,
Idle cycle generation circuit) 1, instruction decoder 2, bus interface unit (BIU) 3, general-purpose register program counter 4, and accumulator 5
A temporary holding register 6, an arithmetic circuit (ALU) 7,
It is composed of an instruction register 8.

Here, in the processor, the idle cycle generation circuit 1, the general-purpose register program counter 4, the accumulator 5, the temporary holding register 6, the arithmetic circuit 7, and the instruction register 8 are connected to the data bus 100, respectively, and the idle cycle is generated. The generation circuit 1 and the general-purpose register program counter 4 are connected to the address bus 101.

The idle cycle generation circuit 1 receives the M / IO signal 102 and the write signal 103 from the instruction decoder 2 and outputs an idle cycle control signal 104 to the bus interface unit 3.

Here, the M / IO signal 102 indicates whether the cycle being executed in the microprocessor is a memory access (M) or an I / O cycle (I / O).
Further, the write signal 103 is the idle cycle generation circuit 1
Or, it indicates a write cycle to the outside.

The bus interface unit 3 outputs the output of the instruction decoder 2, the M / IO signal 102 and the write signal 103.
In response to the idle cycle control signal 104, the idle cycle is inserted according to the idle cycle control signal 104.

FIG. 2 shows the idle cycle generation circuit 1 of FIG.
3 is a block diagram showing a detailed configuration of FIG. In the figure, the idle cycle generation circuit 1 includes an address decoder 10, 1
1, register groups 12 and 13, NAND circuits 14-1 to 14-n, a comparator group 15, and a selector 16
It consists of and.

The address decoder 10 is an address bus 10.
1, the M / IO signal 102 and the write signal 103,
The strobe signals 111 to 11n for setting the I / O address space in the register group 12 are output.

The address decoder 11 is the address bus 10.
1, the M / IO signal 102 and the write signal 103,
It is for decoding an internal I / O write instruction that sets an idle cycle time corresponding to the I / O address space set in the register group 12, and is a strobe signal 121 when the idle cycle time is set in the register group 13. Output ~ 12n.

The register group 12 includes n registers 12-1.
To 12-n, the registers 12-1 to 12-n are sequentially set in the registers 12-1 to 12-n from the lower address space of the I / O address space by an internal I / O write instruction.

That is, the register 12-1 has the first I
/ O address space is set, and the second register is set in the register 12-2.
I / O address space is set, the third I / O address space is set in the register 12-3, and the nth I / O address space is set in the nth register 12-n. Here, the I / O address space consists of addresses of one or more I / O devices.

The register group 13 has n registers 13-1.
13-n, the idle cycle time corresponding to the I / O address space is set by the internal I / O write command.

That is, the register 13-1 has the first I
The idle cycle time corresponding to the I / O address space is set, the idle cycle time corresponding to the second I / O address space is set to the register 13-2, and the register 1
An idle cycle time corresponding to the third I / O address space is set in 3-3, and an idle cycle time corresponding to the nth I / O address space is set in the nth register 13-n. .

The NAND circuits 14-1 to 14-n take the NAND of the M / IO signal 102 which becomes "H" at the time of executing the I / O instruction and the comparison result signals 151 to 15n from the comparator group 15 and perform the operation. The result is output to the comparator group 15.

The comparator group 15 includes n comparators 15-1 to 15-1.
5-n, each of the comparators 15-1 to 15-1.
5-n compares the upper part of the address on the address bus 100 with the set values 131 to 13n of the I / O address space from the corresponding registers 12-1 to 12-n.

At this time, in each of the comparators 15-1 to 15-n, the upper part of the address at the time of executing the I / O instruction is smaller than the set values 131 to 13n of the I / O address space, and the comparator is connected to the enable (E) terminal. When the signals input from the NAND circuits 14-1 to 14-n (calculation results of the NAND circuits 14-1 to 14-n) are "L", "L" is output to the comparison result signals 151 to 15n.

Therefore, when the address at the time of executing the I / O instruction is in the range of the first address, only the comparison result signal 151 of the comparator 15-1 becomes "L", and in the case of the range of the second address. Shows that only the comparison result signal 152 of the comparator 15-2 becomes "L", and only the comparison result signal 153 of the comparator 15-3 becomes "L" in the case of the third address range.
In the case of the nth address range, only the comparison result signal 15n of the comparator 15-n becomes "L".

When "L" is input from the comparator 15-1 to the select terminal S1, the selector 16 stores in the register 13-
1 to the input terminal I1 is selected, and the comparator 15-2
From the register 13-2 to the input terminal I2 when "L" is input to the select terminal S2 from the register 13-2, and when "L" is input from the comparator 15-3 to the select terminal S3. When the input from the register 13-3 to the input terminal I3 is selected and "L" is input from the comparator 15-n to the select terminal Sn, the input from the register 13-n to the input terminal In is selected.

Therefore, when the comparison result signal 151 of the comparator 15-1 is "L", the adrel cycle time set in the register 13-1 is selected, and the bus interface unit 3 as the idle cycle control signal 104 is selected.
Sent to.

Further, the comparison result signal 15 of the comparator 15-2
When 2 is "L", the adrel cycle time set in the register 13-2 is selected and sent to the bus interface unit 3 as the idle cycle control signal 104.

Further, the comparison result signal 1 of the comparator 15-3
When 53 is "L", the adrel cycle time set in the register 13-3 is selected and sent to the bus interface unit 3 as the idle cycle control signal 104.

Furthermore, when the comparison result signal 15n of the comparator 15-n is "L", the adrel cycle time set in the register 13-n is selected and the bus interface unit 3 is used as the idle cycle control signal 104.
Sent to.

FIG. 3 is a time chart showing the operation of the processor according to the embodiment of the present invention. The figure shows the operation when the processor shown in FIG. 1 performs the processing operation shown in FIG.

When the processor performs the processing operation as shown in FIG. 4, the I / O instruction is issued to the port A (step S1 in FIG. 4) and the other processing is executed (step S in FIG. 4).
2), issuance of I / O instruction to port B (step S in FIG. 4)
3), issuance of I / O instruction to port C (step S in FIG. 4)
The processing is executed in the order of 4).

At this time, an I / O instruction is issued to port A
After performing (1), an idle cycle (2) equivalent to the recovery time (3) specified in port A will be inserted.

After the other processing (4) is performed,
Similar to the above processing, after issuing I / O commands to ports B and C (5) and (8), the recovery times (7) and (10) specified by ports B and C Equivalent idle cycle
(6) and (9) will be inserted.

As a result, it is possible to prevent the insertion of an unnecessary idle cycle that occurs when the idle cycle is fixedly set to a value larger than the recovery time of the ports B and C in the prior art.

The idle cycles (2), (6), (9) inserted after the I / O instructions are issued (1), (5), (8) to the ports A, B, C respectively. ) Is preset by the processing for the register group 13 by the internal I / O instruction of the processor described above.

As described above, the idle cycle time for guaranteeing the recovery time of each I / O device corresponding to the I / O address space held in the register group 12 is stored in the register group 13 for comparison. The selector group 16 selects the idle cycle time of the register group 13 corresponding to the I / O address space in which the match with the address of the I / O instruction is detected by the selector group 14, and the idle cycle time is set to the idle cycle insertion. Bus interface unit 3
By outputting the I / O command, the idle cycle inserted after the I / O instruction is issued can be selected for each arbitrary I / O address space.

Therefore, it is possible to prevent the insertion of an unnecessary idle cycle that greatly exceeds the recovery time defined by the I / O device around the processor, and it is possible to reduce the deterioration of the processing capability of the processor.

[0045]

As described above, according to the present invention, it is detected to which input / output device the input / output instruction is directed, and an idle set in advance corresponding to the input / output device detected by the detection result is detected. By outputting the cycle time, it is possible to prevent an unnecessary idle cycle from being inserted, and it is possible to mitigate a decrease in processing capability.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an idle cycle control signal generation circuit in FIG.

FIG. 3 is a time chart showing the operation of the embodiment of the present invention.

FIG. 4 is a diagram illustrating an example of processing by a processor.

FIG. 5 is a time chart showing an operation of a conventional example.

[Explanation of symbols]

1 Idle cycle control signal generation circuit 2 Instruction decoder 3 Bus interface 10, 11 Address decoder 12, 13 Register group 12-1 to 12-3, 12-n, 13-1 to 13-3,
13-n register 14-1, 14-2, 14-n NAND circuit 15 comparator group 15-1 to 15-3, 15-n comparator 16 selector

Claims (3)

[Claims] 1. A processor for inserting an idle cycle for guaranteeing a recovery time of an input / output device after issuing an input / output instruction to the input / output device,
A detection means for detecting which input / output device the input / output instruction is directed to, and an output means for selecting and outputting a preset idle cycle time corresponding to the input / output device detected by the detection result. A processor having. 2. A processor for inserting an idle cycle for guaranteeing a recovery time of an input / output device after issuing an input / output instruction to the input / output device,
Holding means for holding the address of the input / output device in advance; storing means for storing an idle cycle time preset corresponding to the input / output device; address of the input / output instruction and contents of the holding means. Comprising: comparing means for comparing; and selecting means for selecting and outputting an idle cycle time corresponding to an input / output device for which a match is detected by the comparing means from among the idle cycle times stored in the storing means. Featured processor. 3. A processor for inserting an idle cycle for guaranteeing a recovery time of an input / output device after issuing an input / output instruction to the input / output device,
Holding means for holding in advance a plurality of address spaces each consisting of an address of each input / output device having the same idle cycle; storage means for storing a preset idle cycle time for each of the plurality of address spaces; Detecting means for detecting which one of the plurality of address spaces the address of the instruction belongs to; and idle cycle time corresponding to the address space detected by the detecting means from among idle cycle times stored in the storing means. And a selecting means for selecting and outputting the processor.