JPH05100848A - Instruction pre-fetch device - Google Patents

Abstract

(57) [Abstract] [Purpose] Even in a hardware configuration with a single bus, the idle cycle state of the pipeline due to the instruction prefetch wait state can be reduced, and the throughput of the processing currently being executed is reduced. [Structure] The number of cycles required to access the memory areas 1 and 2 is preset in the wait cycle setting registers 5 and 6 corresponding to the memory areas 1 and 2. The instruction prefetch address for accessing the memory areas 1 and 2 is prepared in the prefetch address register 9 and output to the address bus 3. At the same time that the prefetch address is output to the address bus 3, the cycle counters 7 and 8 start counting down the loaded values of the setting registers 5 and 6. When the count ends, flip-flop 13,
Output a match signal to 14. Flip-flops 13, 14 and A
The ND circuits 17 and 18 perform exclusive control and output output enable signals 15 and 16 for accessing one of the memory areas 1 and 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program prefetch device for accessing a large amount of memory in order to suppress a bus cycle wait state as much as possible when an instruction prefetch occurs in different memory areas.

[0002]

2. Description of the Related Art Conventionally, in a system in which instruction data is arranged in different memories and different spaces, a plurality of independent instruction prefetch units and a plurality of buses are provided, and instruction prefetch is performed by accessing a plurality of memory areas in parallel. A system that avoids waiting for instruction execution due to waiting has been considered. In such a system, the amount of hardware has increased and the entire system has become large-scale.

On the other hand, as the system becomes smaller, more multifunctional, more sophisticated, and more versatile, it is provided with a large-capacity memory having an external memory arranged from a conventional system having a CPU with a built-in ROM or RAM as a core. In some fields, there is a shift to a system, and it is difficult to configure with sufficient hardware as in the past to avoid waiting for instruction execution due to instruction prefetch. Therefore, when the system is configured by suppressing the hardware resources by the single bus and the single instruction prefetch unit, the system throughput due to the instruction prefetch waiting is lowered.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems of the prior art. Even in a hardware configuration with a single bus, it is possible to reduce the idle cycle state of the pipeline due to the instruction prefetch wait state, and An object of the present invention is to provide an instruction prefetch device capable of avoiding a decrease in processing throughput as much as possible.

[0005]

In order to achieve the above object, the instruction prefetch device of the present invention, when it is necessary to perform instruction prefetch for different memory spaces,
If a single bus is used, (1) multiple accesses are executed, and when program fetch data is acquired at the same timing, the one that has always been decided has priority, (2) the remaining fetch cycle of the memory area that occurred earlier And the fetch cycle of the memory area that occurred later are compared, and if it is confirmed that the acquisition of the program fetch data is not at the same timing, the subsequent program fetch is started. (3) Multiple access is executed and each memory is executed. One of the means is used, which has a priority of a program fetch operation that can be arbitrarily set for an area, and when the program fetch data is acquired at the same timing, the higher priority is given priority.

[0006]

With this configuration, even in the hardware configuration using a single bus, the instruction prefetch operation can be executed efficiently and the instruction prefetch waiting state can be reduced, so that the idle cycle of the pipeline can be eliminated. , The throughput of the system can be improved.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an instruction prefetch device which always gives priority to a determined one when the data acquisition of the present invention is at the same timing, and FIG. 2 is a timing diagram of the instruction prefetch device.

In FIG. 1, different memory areas 1 and 2 are connected to the same address bus 3 and data bus 4, and the number of cycles required to access these memory areas 1 and 2 depends on the memory area 1. Correspondingly, it is preset in wait cycle setting register 5 and in wait cycle setting register 6 corresponding to memory area 2. Although the wait cycles of the wait cycle setting registers 5 and 6 corresponding to the memory areas 1 and 2 can be set arbitrarily, it is necessary that the memory areas 1 and 2 have sufficient access time.

An instruction prefetch address for accessing the memory areas 1 and 2 is prepared in the prefetch address register 9 and output to the address bus 3 under the control of the control unit 10. At the same time that the prefetch address is output from the prefetch address register 9 to the address bus 3, a count start signal is output to the cycle counter 7 when the memory area 1 is accessed and a cycle start signal is output to the cycle counter 8 when the memory area 2 is accessed. .

The value of the wait cycle setting register 5 is stored in the cycle counter 7 and the value of the wait cycle setting register 6
Is loaded into the cycle counter 8, and the cycle counters 7 and 8 start down counting in synchronization with a system clock (not shown) that controls the memory areas 1 and 2. The count value of the cycle counter 7 is compared with "0" by the zero detection circuit 11, and if they match, the flip-flop
A match signal is output to 13 and held. Similarly, the count value of the cycle counter 8 is "0" by the zero detection circuit 12.
Is compared, and if they match, a match signal is output to the flip-flop 14 and held.

The signal held in the flip-flop 13 is output to the memory area 1 as the output enable signal 15, and in response to this, the memory area 1 outputs data. On the other hand, the signal held by the flip-flop 14 is input to the AND circuits 17 and 18 together with the output enable signal 15. A
The ND circuit 17 receives the output of the flip-flop 14 and the inverted data of the output enable signal 15 as input, and
Is "1" and the output enable signal 15 is "0", "1" is output to the memory area 2 as the output enable signal 16 for the memory area 2. That is,
When only the memory area 2 is in the data output timing, the output enable signal 16 is unconditionally output.

The AND circuit 18 receives the output of the flip-flop 14 and the output enable signal 15 as input, and
When the output of 14 is "1" and the output enable signal 15 is "1", "1" is output and is held by the flip-flop 19 and serves as a reset input of the flip-flop 14. That is, when the data output timings of the memory area 1 and the memory area 2 are the same timing (when the coincidence signals of the zero detection circuits 11 and 12 are simultaneously output), the AND circuit 18
Means that access to the memory area 2 is prohibited.

The output enable signals 15 and 16 are input to the control unit 10 and serve as trigger signals for starting the next instruction prefetch operation for the memory area 1 or the memory area 2 according to the update of the prefetch address register 9 or the updated prefetch address. The hold signal of the flip-flop 19 is input to the control unit 10 as the interruption signal 20 and the instruction prefetch operation is started again for the memory area 2.

In FIG. 2, it is assumed that the address output to the memory area 1 ("area 1AB" in the figure) is first executed, and the address output to the memory area 2 ("area 2AB" in the figure) is executed in the next cycle. Then, an address bus enable signal (“ABE” in the figure, not shown in FIG. 1) is output to the memory areas 1 and 2 at respective timings. When the data is acquired at the same timing, the output enable signal (“D” in the figure) corresponding to the memory area 1
BE1 ") and the output enable signal (" DBE2 "in the figure) corresponding to the memory area 2 become" 1 "at the same timing.

However, since access to the memory area 1 is prioritized, an interruption signal is output and the output enable signal corresponding to the memory area 2 is set to "0". Although the data in the memory area 1 is output by the output enable signal corresponding to the memory area 1 (“area 1DB” in the figure), the output enable signal corresponding to the memory area 2 becomes “0”, so the data in the memory area 2 is output. Is not output (“area 2D in the figure
B ″). By arranging a high-priority program and a memory with a long access cycle in the area 1, efficient instruction execution can be performed and throughput can be improved.

FIG. 3 compares the remaining fetch cycle of the memory area generated earlier and the fetch cycle of the memory area generated later, and when it is confirmed that the program fetch data is not acquired at the same timing, the subsequent program fetch is performed. FIG. 3 is a block diagram showing a configuration of an instruction prefetch device for starting the. The value of the wait cycle setting register 21 in which the memory access cycle of the instruction prefetch operation that occurred earlier is set is the cycle counter 22 composed of a down counter indicating the remaining wait cycle at the present time.
When an instruction prefetch address (not shown) is generated, it is loaded and starts counting.

When an instruction prefetch occurs in an area different from the currently executing memory area, the value of the wait cycle setting register 23 corresponding to the newly generated instruction prefetch area and the value of the current cycle counter 22 are compared with each other.
Compare with 24 (value of wait cycle setting register 23)
If ≠ (current value of the cycle counter 22), the access permission signal 25 is output, the address is output, and the instruction prefetch operation is started. When the bus is composed of a single bus, bus contention can be easily suppressed and waste of memory access does not occur. Even if (value of wait cycle setting register 23) = (current value of cycle counter 22), if address generation is delayed by one cycle,
It is accessible and the reduction in instruction prefetch efficiency is minimized.

FIG. 4 is a block diagram showing the configuration of an instruction prefetch device which gives priority to a higher priority when program fetch data is acquired at the same timing. When there are multiple instruction prefetch operations for the memory area 26 and the memory area 27 and the data acquisition timings occur at the same time, which data of the memory area 26 or the memory area 27 is to be preferentially acquired is determined by the frequency of priority. The priority register 28 corresponding to the specified memory area 26 and the priority register 29 corresponding to the memory area 27 are data setting address buses.
It is arranged on the data bus 30 and the data setting data bus 31, and can be arbitrarily set by software.

The setting values of the priority registers 28 and 29 are set in the comparator 32.
Is input to, and the magnitude relation is determined (priority of memory area 26) ≥ (priority of memory area 27), the comparison result signal
33 becomes “1” and becomes “0” when (priority of memory area 26) <(priority of memory area 27). When the comparison result signal 33 is "1 (memory area 26 has priority)", the memory area 26,
27 data acquisition timings occur simultaneously (memory area 26
If the internal output enable signal 36 of the memory area 26 and the internal output enable signal 38 of the memory area 27 are simultaneously enabled) or if the internal output enable signal 36 of the memory area 26 is generated independently, the AND / OR circuit 34 An output enable signal 37 for the memory area 26 is generated.

When the comparison result signal 33 is "0 (the memory area 27 has priority)", the data acquisition timings of the memory areas 26 and 27 occur simultaneously (the internal output enable signal 36 of the memory area 26 and the internal output enable signal of the memory area 27). If the internal output enable signal 38 of the memory area 27 is generated independently, AND / OR
The circuit 35 generates an output enable signal 39 for the memory area 27. With this configuration, when data acquisition timings occur at the same time, exclusive processing is possible, and a system configuration with a single instruction fetch bus is possible.

[0021]

As described above, according to the present invention, when it is necessary to prefetch instructions for different memory spaces, multiple instruction fetches can be executed even with a hardware configuration using a single bus. In addition, if there is bus contention, the avoidance operation can be performed and the instruction data can be acquired by effectively using the bus cycle.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an instruction prefetch device which always gives priority to a determined one when data is acquired at the same timing according to an embodiment of the present invention.

FIG. 2 is a timing diagram of the same instruction prefetch device according to one embodiment of the present invention.

FIG. 3 compares the remaining fetch cycle of the memory area generated earlier and the fetch cycle of the memory area generated later according to another embodiment of the present invention, and it has been confirmed that the program fetch data is not acquired at the same timing. FIG. 16 is a block diagram showing a configuration of an instruction prefetch device for starting a later program fetch.

FIG. 4 is a block diagram showing a configuration of an instruction prefetch device that prioritizes higher priority when program fetch data is acquired at the same timing according to still another embodiment of the present invention.

[Explanation of symbols]

 1, 2, 26, 27 Memory area 3 Address bus 4 Data bus 5, 6, 21, 23 Wait cycle setting register 7, 8, 22 Cycle counter 9 Prefetch address register 10 Control unit 11, 12 Zero detection circuit 13, 14, 19 Flip-flop 15, 16 Output enable signal 20 Interrupt signal 24, 32 Comparator 25 Access enable signal 28, 29 Priority register 30 Data setting address bus 31 Data setting data bus 36, 38 Internal output enable signal 37, 39 output Enable signal

Claims (3)

[Claims] 1. A means for accessing different memory areas in which a program fetch operation exists using the same bus, and the necessity of program fetch of a second memory area during program fetch of a first memory area that has already occurred. When the fetch operation of the second memory area is executed, or when the need for the program fetch of the first memory area occurs during the program fetch of the already generated second memory area, When the means for executing the fetch operation of the first memory area and the acquisition of the program fetch data of the first memory area and the acquisition of the program fetch data of the second memory area have the same timing, the first memory Means for giving priority to the program fetch of the area and invalidating the program fetch of the second memory area Equipped instruction prefetch device. 2. A means for accessing different memory areas in which a program fetch operation exists using the same bus, a means for counting a fetch cycle with the start of the program fetch operation of the first memory area which has occurred previously, and When the program fetch of the second memory area is necessary during the program fetch of the first memory area, the count number of the fetch cycle of the first memory area and the fetch cycle of the second memory area are set. When it is confirmed that the means for comparing and the acquisition of the program fetch data in the first memory area and the acquisition of the program fetch data in the second memory area are not at the same timing, the program fetch in the second memory area is started. Instruction prefetch device having means for performing. 3. A means for accessing different memory areas in which a program fetch operation exists using the same bus, a means for arbitrarily setting the priority of the program fetch operation for each memory area, and a means which has already occurred. When the need for program fetch of the second memory area occurs during program fetch of the first memory area,
When the means for executing the fetch operation of the second memory area and the acquisition of the program fetch data of the first memory area and the acquisition of the program fetch data of the second memory area have the same timing, the first memory An instruction prefetch device comprising means for comparing the priority of an area with the priority of the first memory area and executing the program fetch of the higher priority.