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JPH07312405A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH07312405A
JPH07312405A JP6102369A JP10236994A JPH07312405A JP H07312405 A JPH07312405 A JP H07312405A JP 6102369 A JP6102369 A JP 6102369A JP 10236994 A JP10236994 A JP 10236994A JP H07312405 A JPH07312405 A JP H07312405A
Authority
JP
Japan
Prior art keywords
semiconductor device
lead
semiconductor chip
semiconductor
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6102369A
Other languages
Japanese (ja)
Other versions
JP3243116B2 (en
Inventor
Koichi Kanemoto
光一 金本
Takafumi Nishida
隆文 西田
Akiro Sumiya
彰朗 角谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP10236994A priority Critical patent/JP3243116B2/en
Publication of JPH07312405A publication Critical patent/JPH07312405A/en
Application granted granted Critical
Publication of JP3243116B2 publication Critical patent/JP3243116B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W90/726

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce mounting area, and improve mounting efficiency in board mounting, by protruding a part of an inner lead from the bottom surface or the upper surface of a sealing resin part. CONSTITUTION:An inner lead part 1 is electrically connected with a semiconductor chip 3 via a bump 2 formed on the inner lead part 1. An outer lead part 5 protruding from a resin molded part 4 is surface-mounted on a board or the like. By protruding a part of the inner lead from the bottom surface or the upper surface of the sealing resin part of a semiconductor device, the outer leads are provided in the area occupied by the sealing resin part of the semiconductor device, so that the mounting area is reduced and the mounting efficiency in the board mounting of a semiconductor device is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置に適用して
有効な技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique effectively applied to a semiconductor device.

【0002】[0002]

【従来の技術】従来の半導体装置には、一般に内部リー
ドと半導体チップをワイヤで接続したものとバンプで接
続するものとがあり、それら外部リードはともに半導体
装置の封止樹脂部の側面から突出した構造を持つ。
2. Description of the Related Art Generally, conventional semiconductor devices include those in which internal leads and semiconductor chips are connected by wires and those in which bumps are connected, and both of these external leads protrude from the side surface of a sealing resin portion of the semiconductor device. It has a structure.

【0003】[0003]

【発明が解決しようとする課題】本発明者は、上記従来
技術を検討した結果、以下の問題点を見いだした。
DISCLOSURE OF THE INVENTION The present inventors have found the following problems as a result of examining the above prior art.

【0004】近年の半導体装置を使用したシステム機器
等のダウンサイジングに伴い、半導体装置を搭載する基
板のサイズ等を縮小する必要がでてきた。このため、半
導体装置のサイズを縮小する等で基板の実装効率を上げ
て基板サイズを縮小してきた。
With the recent downsizing of system equipment and the like using semiconductor devices, it has become necessary to reduce the size of the substrate on which the semiconductor devices are mounted. Therefore, the size of the semiconductor device has been reduced and the mounting efficiency of the substrate has been increased to reduce the size of the substrate.

【0005】この半導体装置の縮小は、主に半導体チッ
プの縮小によりなされたものであり、外部リードはその
縮小の対象とはなっていなかった。
This reduction in the size of the semiconductor device is mainly done by reducing the size of the semiconductor chip, and the external lead has not been the target of the reduction.

【0006】このため、基板上の半導体装置の外部リー
ドが占める面積に対する縮小対策はなされていないのが
現状である。
For this reason, there is currently no countermeasure for reducing the area occupied by the external leads of the semiconductor device on the substrate.

【0007】したがって、従来の半導体装置における外
部リードは、一般に半導体装置の封止樹脂部の側面から
突出した構造を持っていることから、その封止樹脂部の
側面から突出した外部リードの分だけ実装面積を余分に
とり、基板実装における実装効率が悪いという問題点が
あった。
Therefore, since the external leads in the conventional semiconductor device generally have a structure protruding from the side surface of the sealing resin portion of the semiconductor device, only the external leads protruding from the side surface of the sealing resin portion are formed. There is a problem in that the mounting area is taken up and the mounting efficiency in board mounting is poor.

【0008】本発明の目的は、半導体装置の基板実装に
おける実装効率を向上することが可能な技術を提供する
ことにある。
An object of the present invention is to provide a technique capable of improving the mounting efficiency in mounting a semiconductor device on a substrate.

【0009】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0010】[0010]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。
Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【0011】半導体チップとそれに電気的に接続された
内部リードを樹脂で封止した半導体装置であって、前記
半導体装置の封止樹脂部の底面もしくは、上面から内部
リードの一部を突出させる。
In a semiconductor device in which a semiconductor chip and an internal lead electrically connected to the semiconductor chip are sealed with a resin, a part of the internal lead is projected from a bottom surface or an upper surface of a sealing resin portion of the semiconductor device.

【0012】[0012]

【作用】上述した手段によれば、半導体チップとそれに
電気的に接続された内部リードを樹脂で封止した半導体
装置であって、前記半導体装置の封止樹脂部の底面もし
くは、上面から内部リードの一部を突出させることによ
り、半導体装置の封止樹脂部の占める面積内に外部リー
ドが収まり、従来の外部リードの突出によって余分にと
られていた実装面積を縮小できるので、半導体装置の基
板実装における実装効率を向上することが可能となる。
According to the above-mentioned means, the semiconductor device is a semiconductor device in which the semiconductor chip and the internal leads electrically connected to the semiconductor chip are encapsulated with resin, and the internal leads are provided from the bottom surface or the top surface of the encapsulating resin portion of the semiconductor device. By projecting a part of the external leads, the external leads can be accommodated within the area occupied by the sealing resin portion of the semiconductor device, and the mounting area taken up by the protrusion of the conventional external leads can be reduced. It is possible to improve the mounting efficiency in mounting.

【0013】以下、本発明の構成について、実施例とと
もに説明する。
The structure of the present invention will be described below together with embodiments.

【0014】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。
In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

【0015】[0015]

【実施例】図1は、本発明の一実施例である半導体装置
の構造を説明するためのものである。
1 is a view for explaining the structure of a semiconductor device according to an embodiment of the present invention.

【0016】図1に示した本実施例の半導体装置は長方
形型であり、図2に長方形の短辺側からみた側面図、図
3に長辺側からみた側面図、図4に底面からみた平面図
をそれぞれ示す。
The semiconductor device of this embodiment shown in FIG. 1 is of a rectangular type, and FIG. 2 is a side view seen from the shorter side of the rectangle, FIG. 3 is a side view seen from the longer side, and FIG. 4 is seen from the bottom side. Each top view is shown.

【0017】図1〜図4において、1は内部リード部
分、2はバンプ、3はチップ、4は樹脂封止部、5は外
部リード部分をそれぞれ示す。
1 to 4, 1 is an internal lead portion, 2 is a bump, 3 is a chip, 4 is a resin sealing portion, and 5 is an external lead portion.

【0018】本実施例の半導体装置は、図1に示すよう
に、リードに段差が設けられており、内部リードとして
機能する内部リード部分1と外部リードとして機能する
外部リード部分5とからなる。
As shown in FIG. 1, the semiconductor device of this embodiment is provided with a step on the lead, and comprises an inner lead portion 1 functioning as an inner lead and an outer lead portion 5 functioning as an outer lead.

【0019】このリードの段差は、リードの内部リード
部分1をハーフエッチしたり、リードを段違いに2枚貼
り合わせて切断することによって得られる。
The step of the lead can be obtained by half-etching the inner lead portion 1 of the lead or by cutting two leads which are attached in different steps.

【0020】樹脂封止部4内においては、内部リード部
分1上に設けられた、例えば半田より成るバンプ2が設
けられ、そのバンプ2を介して半導体チップ3と電気的
に接続されている。なお、このときの内部リード部分1
と半導体チップ3を電気的に接続する手段として、半導
体チップ3側にあらかじめ設けたバンプであってもよ
い。また、ワイヤ等を用いてもよい。
In the resin encapsulation portion 4, bumps 2 made of, for example, solder are provided on the internal lead portions 1 and are electrically connected to the semiconductor chip 3 via the bumps 2. The internal lead portion 1 at this time
As a means for electrically connecting the semiconductor chip 3 and the semiconductor chip 3, a bump provided in advance on the semiconductor chip 3 side may be used. Alternatively, a wire or the like may be used.

【0021】そして、図2〜図4に示した樹脂封止部4
から突出する外部リード部分5は、基板等に面付け実装
される。
Then, the resin sealing portion 4 shown in FIGS.
The external lead portion 5 projecting from is mounted on a substrate or the like by imposition.

【0022】これにより、従来、樹脂封止部4の側面部
から突出していた外部リードの分だけ、実装スペースを
切り詰めたり、他の部品等の実装に割り当てたりするこ
とが可能になる。
As a result, the mounting space can be cut down or allocated for mounting other components by the amount of the external leads that have conventionally protruded from the side surface of the resin sealing portion 4.

【0023】次に、図5を用いて、本実施例の半導体装
置のリードフレームについて説明する。
Next, the lead frame of the semiconductor device of this embodiment will be described with reference to FIG.

【0024】図5において、3Aは大きめの半導体チッ
プ、3Bは小さめの半導体チップ、2Aは大きめの半導
体チップと内部リード部分を接合するバンプ、2Bは大
きめの半導体チップと内部リード部分を接合するバンプ
をそれぞれ示す。
In FIG. 5, 3A is a large semiconductor chip, 3B is a small semiconductor chip, 2A is a bump for joining a large semiconductor chip to an internal lead portion, and 2B is a bump for joining a large semiconductor chip to an internal lead portion. Are shown respectively.

【0025】図5に示すように、本実施例の半導体装置
のリードフレームの形状は、フレームの中心付近から内
部リードが放射上に広がっている。
As shown in FIG. 5, in the shape of the lead frame of the semiconductor device of this embodiment, the inner leads radiate from the vicinity of the center of the frame.

【0026】これにより、破線で示した異なるサイズの
半導体チップである大きめの半導体チップ3Aを搭載す
る場合でも、小さめの半導体チップ3Bを搭載する場合
でも、各半導体チップ3A,3Bのパッド位置を内部リ
ード1上の接続可能位置に変更し、その位置にバンプ2
A,2Bを設けることで半導体チップ3A,3Bと内部
リード部分1とを接続できる。このバンプ適用による内
部リードと半導体チップとの電気的な接続はワイヤ接続
では得られない有用な手段である。
As a result, the pad positions of the respective semiconductor chips 3A and 3B are set inside regardless of whether the large semiconductor chip 3A, which is a semiconductor chip of a different size indicated by the broken line, or the small semiconductor chip 3B is mounted. Change to a connectable position on the lead 1 and bump 2 at that position
By providing A and 2B, the semiconductor chips 3A and 3B can be connected to the internal lead portion 1. The electrical connection between the internal lead and the semiconductor chip by applying the bump is a useful means that cannot be obtained by wire connection.

【0027】すなわち、本実施例のリードフレーム一つ
で多種の半導体チップを適用できる。
That is, various semiconductor chips can be applied with one lead frame of this embodiment.

【0028】次に、本発明の他の実施例を図6と図7に
示す。
Next, another embodiment of the present invention is shown in FIGS.

【0029】図6に示す半導体装置の例は、前述の図1
に示した半導体装置の内部リード部分1と外部リード部
分の段差をなくしたものであり、内部リードと外部リー
ドを共用化したリードを設けてある。すなわち、本実施
例によれば、リードの板厚のほぼ2/3がレジンにより
埋め込まれ、その埋め込まれたリード一主面(上面)が
半導体チップとの電気的接続部をなし、一方、リードの
板厚のほぼ1/3がレジンから露出、その露出した他主
面は実装基板への接続端子、つまり外部リードとなる。
The example of the semiconductor device shown in FIG. 6 is the same as that shown in FIG.
The semiconductor device shown in FIG. 1 eliminates the step between the inner lead portion 1 and the outer lead portion, and is provided with a lead that shares the inner lead and the outer lead. That is, according to the present embodiment, approximately 2/3 of the plate thickness of the lead is embedded by the resin, and the embedded one main surface (upper surface) of the lead forms an electrical connection portion with the semiconductor chip, while the lead is formed. Approximately one-third of the board thickness is exposed from the resin, and the exposed other main surface becomes a connection terminal to the mounting board, that is, an external lead.

【0030】これにより、実装時における基板と外部リ
ードの接触部分の面積を確保できるとともに、薄型化パ
ッケージが得られる。リードフレームに段差をつけなく
てもよくなる。
As a result, the area of the contact portion between the substrate and the external lead during mounting can be secured, and a thin package can be obtained. There is no need to make a step on the lead frame.

【0031】図7に示す半導体装置の例は、前述の図1
に示した半導体装置の半導体チップ3上に放熱用フィン
6を設け、半導体チップから発せられる熱を逃がしてや
るものである。
An example of the semiconductor device shown in FIG. 7 is the same as that shown in FIG.
The heat radiation fins 6 are provided on the semiconductor chip 3 of the semiconductor device shown in FIG. 2 to release the heat generated from the semiconductor chip.

【0032】なお、本実施例は長方形型の半導体装置を
それぞれ取り挙げたが正方形型の半導体装置についても
同様である。
In this embodiment, the rectangular semiconductor devices are mentioned, but the same applies to the square semiconductor devices.

【0033】また、本実施例のCOL(CHIP ON
LEAD)構造の半導体装置は、底面から外部リード
を突出させた例を取り挙げたが、LOC(LEAD O
NCHIP)構造等の半導体装置においては、上面から
外部リードを突出させる。
Further, the COL (CHIP ON) of this embodiment is
For the semiconductor device having the LEAD structure, an example in which the external lead is projected from the bottom surface is given.
In a semiconductor device having a NCHIP) structure or the like, external leads are projected from the upper surface.

【0034】したがって、半導体チップとそれに電気的
に接続された内部リードを樹脂で封止した半導体装置で
あって、前記半導体装置の封止樹脂部の底面もしくは、
上面から内部リードの一部を突出させることにより、半
導体装置の封止樹脂部の占める面積内に外部リードが収
まり、従来の外部リードの突出によって余分とられてい
た実装面積を縮小できるので、半導体装置の基板実装に
おける実装効率を向上することが可能となる。
Therefore, in a semiconductor device in which a semiconductor chip and internal leads electrically connected to the semiconductor chip are sealed with resin, the bottom surface of the sealing resin portion of the semiconductor device or
By projecting a part of the internal leads from the upper surface, the external leads can be contained within the area occupied by the sealing resin portion of the semiconductor device, and the mounting area that has been taken up by the protrusion of the conventional external leads can be reduced. It is possible to improve the mounting efficiency in mounting the device on the substrate.

【0035】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。
The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

【0036】[0036]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

【0037】半導体チップとそれに電気的に接続された
内部リードを樹脂で封止した半導体装置であって、前記
半導体装置の封止樹脂部の底面もしくは、上面から内部
リードの一部を突出させることにより、半導体装置の封
止樹脂部の占める面積内に外部リードが収まり、従来の
外部リードの突出によって余分とられていた実装面積を
縮小できるので、半導体装置の基板実装における実装効
率を向上することが可能となる。
A semiconductor device in which a semiconductor chip and an internal lead electrically connected to the semiconductor chip are sealed with a resin, and a part of the internal lead is projected from a bottom surface or an upper surface of a sealing resin portion of the semiconductor device. This allows the external leads to fit within the area occupied by the encapsulation resin portion of the semiconductor device, and reduces the mounting area that was left over by the protrusion of the conventional external leads, thus improving the mounting efficiency of the semiconductor device on a substrate. Is possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例である半導体装置の構造を説
明するための図である。
FIG. 1 is a diagram illustrating a structure of a semiconductor device that is an embodiment of the present invention.

【図2】本実施例の半導体装置の側面図である。FIG. 2 is a side view of the semiconductor device of this embodiment.

【図3】本実施例の半導体装置の側面図である。FIG. 3 is a side view of the semiconductor device of this embodiment.

【図4】本実施例の半導体装置の底面からみた平面図で
ある。
FIG. 4 is a plan view of the semiconductor device according to the present embodiment as seen from the bottom surface.

【図5】本実施例の半導体装置におけるリードフレーム
の構造を説明するための図である。
FIG. 5 is a diagram for explaining the structure of a lead frame in the semiconductor device of this embodiment.

【図6】本発明の他の実施例である半導体装置の構造を
説明するための図である。
FIG. 6 is a diagram for explaining the structure of a semiconductor device according to another embodiment of the present invention.

【図7】本発明の他の実施例である半導体装置の構造を
説明するための図である。
FIG. 7 is a diagram for explaining the structure of a semiconductor device that is another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…内部リード部分、2…バンプ、3…チップ、4…樹
脂封止部、5…外部リード部分、6…放熱用フィン。
DESCRIPTION OF SYMBOLS 1 ... Internal lead part, 2 ... Bump, 3 ... Chip, 4 ... Resin sealing part, 5 ... External lead part, 6 ... Heat dissipation fin.

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 23/28 Z 8617−4M (72)発明者 角谷 彰朗 東京都小平市上水本町5丁目20番1号 株 式会社日立製作所半導体事業部内Continuation of front page (51) Int.Cl. 6 Identification number Office reference number FI technical display location H01L 23/28 Z 8617-4M (72) Inventor Akio Sumiya 5-20-1 Kamimizumotocho, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップとそれに電気的に接続され
た内部リードを樹脂で封止した半導体装置であって、前
記半導体装置の封止樹脂部の底面もしくは、上面から内
部リードの一部を突出させることを特徴とする半導体装
置。
1. A semiconductor device in which a semiconductor chip and an internal lead electrically connected to the semiconductor chip are sealed with a resin, and a part of the internal lead is projected from a bottom surface or an upper surface of a sealing resin portion of the semiconductor device. A semiconductor device characterized by the above.
【請求項2】 前記半導体チップと内部リードとはバン
プを介して電気的接続して成ることを特徴とする請求項
1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the semiconductor chip and the internal lead are electrically connected via a bump.
【請求項3】 半導体チップとそれに電気的に接続され
た複数のリードを樹脂で封止して成る半導体装置であっ
て、樹脂封止体の一主面部に、それぞれのリードの板厚
の一部がレジンにより埋め込まれ、その埋め込まれたリ
ード主面が半導体チップとの電気的接続部をなし、それ
ぞれリードの他部がレジンから露出し、その露出した他
主面が外部リードをなしていることを特徴とする半導体
装置。
3. A semiconductor device in which a semiconductor chip and a plurality of leads electrically connected to the semiconductor chip are encapsulated with a resin, wherein a principal surface portion of the resin encapsulant has a plate thickness of each lead. Part is embedded with resin, the main surface of the embedded lead forms an electrical connection with the semiconductor chip, the other part of the lead is exposed from the resin, and the exposed other main surface forms an external lead. A semiconductor device characterized by the above.
JP10236994A 1994-05-17 1994-05-17 Semiconductor device Expired - Fee Related JP3243116B2 (en)

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