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KR20010058586A - semiconductor package and mounting method using it - Google Patents

semiconductor package and mounting method using it Download PDF

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Publication number
KR20010058586A
KR20010058586A KR1019990065936A KR19990065936A KR20010058586A KR 20010058586 A KR20010058586 A KR 20010058586A KR 1019990065936 A KR1019990065936 A KR 1019990065936A KR 19990065936 A KR19990065936 A KR 19990065936A KR 20010058586 A KR20010058586 A KR 20010058586A
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KR
South Korea
Prior art keywords
semiconductor
semiconductor package
chip
mounting plate
package
Prior art date
Application number
KR1019990065936A
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Korean (ko)
Inventor
도병태
임세진
Original Assignee
마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Application filed by 마이클 디. 오브라이언, 앰코 테크놀로지 코리아 주식회사 filed Critical 마이클 디. 오브라이언
Priority to KR1019990065936A priority Critical patent/KR20010058586A/en
Publication of KR20010058586A publication Critical patent/KR20010058586A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

이 발명은 반도체패키지 및 이를 이용한 실장 방법에 관한 것으로, 반도체칩의 방열 성능을 향상시키고, 또한 반도체패키지를 중첩하여 실장할 수 있도록, 다수의 입출력 패드가 형성된 반도체칩과, 상기 반도체칩의 저면에 접착제가 개재되어 접착된 칩탑재판과, 상기 칩탑재판의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드와, 상기 내부리드로부터 외측으로 연장된 외부리드와, 상기 반도체칩과 내부리드를 전기적으로 접속시키는 다수의 도전성와이어와, 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 외부 환경으로부터 보호하기 위해 봉지재로 봉지하여 형성된 패키지몸체를 포함하여 이루어진 반도체패키지에 있어서, 상기 패키지몸체의 저면에는 일정깊이의 요부(凹部)가 형성된 것을 특징으로 함.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a mounting method using the same. A chip mounting plate bonded by an adhesive, a plurality of inner leads formed at a predetermined distance apart from the outer circumference of the chip mounting plate, an outer lead extending outward from the inner lead, and the semiconductor chip and the inner lead A semiconductor package comprising a plurality of conductive wires connected to each other, and a package body formed by encapsulating the semiconductor chip, the conductive wire, the chip mounting plate and the inner lead with an encapsulant to protect the external environment from the package body. The bottom surface of the recess is characterized in that a predetermined depth is formed.

Description

반도체패키지 및 이를 이용한 실장 방법{semiconductor package and mounting method using it}Semiconductor package and mounting method using it

본 발명은 반도체패키지 및 이를 이용한 실장 방법에 관한 것으로, 더욱 상세하게 설명하면 반도체칩의 방열 성능을 향상시키고, 또한 반도체패키지를 중첩하여 실장할 수 있는 반도체패키지 및 이를 이용한 실장 방법에 관한 것이다.The present invention relates to a semiconductor package and a mounting method using the same, and more particularly, to a semiconductor package and a mounting method using the same, which can improve heat dissipation performance of a semiconductor chip and can be mounted by overlapping the semiconductor package.

일반적으로 리드프레임을 이용한 반도체패키지(100')는 도1에 도시된 바와 같이 다수의 입출력패드(4)가 형성된 반도체칩(2)과, 접착제가 개재되어 상기 반도체칩(2)을 탑재하는 칩탑재판(6)과, 상기 칩탑재판(6)의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드(8)와, 상기 내부리드(8)로부터 외측으로 연장된 외부리드(10)와, 상기 반도체칩(2)과 내부리드(8)를 전기적으로 접속시키는 다수의 도전성와이어(12)와, 상기 반도체칩(2), 도전성와이어(12), 칩탑재판(6) 및 내부리드(8) 등을 외부 환경으로부터 보호하기 위해 봉지재로 봉지하여 형성된 패키지몸체(14)로 이루어져 있다.In general, a semiconductor package 100 ′ using a lead frame includes a semiconductor chip 2 having a plurality of input / output pads 4 as shown in FIG. 1, and a chip mounting the semiconductor chip 2 with an adhesive interposed therebetween. A mounting plate 6, a plurality of inner leads 8 formed at a predetermined distance apart from the outer circumference of the chip mounting plate 6, outer leads 10 extending outward from the inner leads 8, A plurality of conductive wires 12 electrically connecting the semiconductor chip 2 and the inner lead 8, the semiconductor chip 2, the conductive wire 12, the chip mounting plate 6 and the inner lead 8 The package body 14 is formed by encapsulating with an encapsulant to protect the back and the like from the external environment.

이러한 반도체패키지는 패키지몸체 외측으로 연장된 외부리드가 솔더에 의해 마더보드에 실장된다. 또한 반도체칩과 마더보드 사이의 신호 교환은 도전성와이어, 내부리드 및 외부리드를 통해서 서로 전달된다.The semiconductor package is mounted on the motherboard by soldering an external lead extending outside the package body. In addition, the signal exchange between the semiconductor chip and the motherboard is transferred to each other through the conductive wire, the inner lead and the outer lead.

이상에서와 같은 리드프레임을 이용한 반도체패키지는 최종 입출력단자인 외부리드가 패키지몸체 외주연으로 연장된 채 마더보드에 실장됨으로써 반도체패키지가 마더보드에서 차지하는 면적이 크고, 또한 패키지몸체가 반도체칩의 상,하면을 완전히 감싸는 형태로서 그 두께가 클뿐만 아니라 반도체칩의 방열성능도 저조한 문제점이 있다.The semiconductor package using the lead frame as described above is mounted on the motherboard with the external lead, which is the final input / output terminal, extended to the outer periphery of the package body. In this case, the bottom surface is completely enclosed, and the thickness thereof is not only large but also a heat dissipation performance of the semiconductor chip is poor.

따라서 본 발명은 상기와 같은 종래의 문제점을 해결하기 위해 안출한 것으로, 반도체칩이 탑재된 칩탑재판의 저면을 외부로 노출시키거나 또는 그 칩탑재판 저면의 패키지몸체 두께를 감소시킴으로써 반도체칩의 방열성능을 향상시킴은 물론, 다수의 반도체패키지를 중첩하여 실장할 수 있는 반도체패키지 및 이를 이용한 실장 방법을 제공하는데 있다.Therefore, the present invention has been made to solve the above-mentioned conventional problems, by exposing the bottom surface of the chip mounting board on which the semiconductor chip is mounted to the outside or reducing the thickness of the package body of the bottom surface of the chip mounting board. In addition to improving the heat dissipation performance, there is provided a semiconductor package and a mounting method using the same, which can be mounted by overlapping a plurality of semiconductor packages.

도1은 종래의 통상적인 반도체패키지를 도시한 단면도이다.1 is a cross-sectional view showing a conventional conventional semiconductor package.

도2a 및 도2b는 본 발명에 의한 반도체패키지를 도시한 단면도이다.2A and 2B are cross-sectional views showing a semiconductor package according to the present invention.

도3은 본 발명의 반도체패키지를 이용한 실장 방법을 도시한 단면도이다.3 is a cross-sectional view showing a mounting method using a semiconductor package of the present invention.

- 도면중 주요 부호에 대한 설명 --Description of the main symbols in the drawings-

100; 본 발명에 의한 반도체패키지100; Semiconductor package according to the present invention

2; 반도체칩 4; 입출력패드2; Semiconductor chip 4; I / O pad

6; 칩탑재판 8; 내부리드6; Chip mounting plate 8; Internal lead

10; 외부리드 12; 도전성와이어10; Outer lead 12; Conductive Wire

14; 패키지몸체 20; 요부(凹部)14; Package body 20; Lumbar

22; 바닥면 24; 경사면22; Bottom surface 24; incline

101; 제1반도체패키지 102; 제2반도체패키지101; First semiconductor package 102; Second Semiconductor Package

상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지는 다수의 입출력 패드가 형성된 반도체칩과, 상기 반도체칩의 저면에 접착제가 개재되어 접착된 칩탑재판과, 상기 칩탑재판의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드와, 상기 내부리드로부터 외측으로 연장된 외부리드와, 상기 반도체칩과 내부리드를 전기적으로 접속시키는 다수의 도전성와이어와, 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 외부 환경으로부터 보호하기 위해 봉지재로 봉지하여 형성된 패키지몸체를 포함하여 이루어진 반도체패키지에 있어서, 상기 패키지몸체의 저면에는 일정깊이의 요부(凹部)가 형성된 것을 특징으로 한다.In order to achieve the above object, the semiconductor package according to the present invention includes a semiconductor chip having a plurality of input / output pads formed thereon, a chip mounting plate bonded with an adhesive interposed on a bottom surface of the semiconductor chip, and a predetermined outer periphery of the chip mounting plate. A plurality of inner leads formed at a distance from each other, an outer lead extending outwardly from the inner lead, a plurality of conductive wires electrically connecting the semiconductor chip and the inner lead, the semiconductor chip, the conductive wire, the chip mounting plate, A semiconductor package including a package body formed by encapsulating with an encapsulant to protect an inner lead from an external environment, wherein a bottom portion of the package body has a predetermined depth.

여기서, 상기 요부의 바닥면 전체는 칩탑재판의 저면에 근접하여 형성됨이 바람직하다.Here, the entire bottom surface of the recess is preferably formed close to the bottom surface of the chip mounting plate.

또한, 상기 칩탑재판은 요부의 바닥면을 통해 외부로 노출되도록 할 수도 있다.In addition, the chip mounting plate may be exposed to the outside through the bottom surface of the recess.

더불어, 상기한 목적을 달성하기 위해 본 발명에 의한 반도체패키지의 실장 방법은 통상의 제1반도체패키지를 마더보드에 실장하는 단계와; 상기 요부가 형성된 반도체패키지중 어느 한 반도체패키지를 상기 제1반도체패키지의 상부에 위치하도록 마더보드에 실장하는 단계로 이루어진 것을 특징으로 한다.In addition, the method for mounting a semiconductor package according to the present invention for achieving the above object comprises the steps of mounting a conventional first semiconductor package on the motherboard; And mounting one of the semiconductor packages having the recessed portion on the motherboard so as to be positioned above the first semiconductor package.

상기 제1반도체패키지는 그 높이가 상기 반도체패키지중 어느 하나에 형성된 요부 높이보다 작게 형성됨이 바람직하다.It is preferable that the height of the first semiconductor package is smaller than the height of the recessed portion formed in any one of the semiconductor packages.

상기와 같이 하여 본 발명에 의한 반도체패키지 및 그 실장 방법에 의하면, 반도체칩이 탑재된 칩탑재판의 저면을 외부로 노출시키거나 또는 그 칩탑재판 저면의 패키지몸체 두께를 감소시킴으로써 반도체칩의 방열성능을 향상시킴은 물론, 다수의 반도체패키지를 중첩하여 실장할 수 있게 된다.According to the semiconductor package and the mounting method of the present invention as described above, the heat dissipation of the semiconductor chip by exposing the bottom surface of the chip mounting plate on which the semiconductor chip is mounted to the outside or reducing the thickness of the package body of the bottom surface of the chip mounting plate. In addition to improving performance, a plurality of semiconductor packages can be superimposed and mounted.

이하 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 용이하게 실시할 수 있을 정도로 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세하게 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings such that those skilled in the art can easily implement the present invention.

도2a 및 도2b는 본 발명에 의한 반도체패키지(100)를 도시한 단면도이다.2A and 2B are cross-sectional views illustrating a semiconductor package 100 according to the present invention.

도시된 바와 같이 다수의 입출력패드(4)가 형성된 반도체칩(2)이 구비되어 있고, 상기 반도체칩(2)의 저면에는 접착제가 개재되어 칩탑재판(6)이 접착되어 있다. 상기 칩탑재판(6)의 외주연으로부터 일정 거리 이격되어서는 다수의 내부리드(8)가 위치되어 있고, 상기 내부리드(8)로부터 외측으로 연장되어서는 외부리드(10)가 위치되어 있다. 상기 반도체칩(2)의 입출력패드(4)와 내부리드(8)는 도전성와이어(12)에 의해 전기적으로 접속되어 있다. 상기 반도체칩(2), 도전성와이어(12), 칩탑재판(6) 및 내부리드(8) 등은 외부 환경으로부터 보호되도록 봉지재로 봉지되어 패키지몸체(14)를 형성하고 있다.As shown in the drawing, a semiconductor chip 2 having a plurality of input / output pads 4 is provided, and a chip mounting plate 6 is bonded to a bottom surface of the semiconductor chip 2 by an adhesive. A plurality of inner leads 8 are positioned to be spaced from the outer circumference of the chip mounting plate 6 by a predetermined distance, and outer leads 10 are positioned to extend outward from the inner leads 8. The input / output pad 4 and the inner lead 8 of the semiconductor chip 2 are electrically connected by conductive wires 12. The semiconductor chip 2, the conductive wire 12, the chip mounting plate 6, the inner lead 8, and the like are encapsulated with an encapsulant so as to be protected from the external environment to form the package body 14.

이상의 구조는 종래와 유사하다. 다만 본 발명은 상기 패키지몸체(14) 저면에 일정깊이의 요부(20)(凹部)가 더 형성된 것이 특징이다.The above structure is similar to the conventional one. However, the present invention is characterized in that the recessed portion 20 (凹 部) of a predetermined depth is further formed on the bottom surface of the package body 14.

즉, 상기 요부(20)는 단면상 대략 사다리꼴로 되어 있으며, 상부에 형성된 바닥면(22)은 도2a에 도시된 바와 같이 칩탑재판(6)의 저면에 근접하여 형성될 수 있다. 또한, 상기 요부(20)의 측부는 경사면(24)으로 형성됨이 바람직하며 이는 봉지 공정 완료후 상기 패키지몸체(14)가 바텀몰드(도시되지 않음)에서 용이하게 취출되도록 하기 위함이다.That is, the recessed portion 20 is substantially trapezoidal in cross section, and the bottom surface 22 formed on the upper portion may be formed close to the bottom surface of the chip mounting plate 6 as shown in FIG. 2A. In addition, the side portion of the recess 20 is preferably formed with an inclined surface 24, so that the package body 14 is easily taken out from the bottom mold (not shown) after the sealing process is completed.

한편, 도2b에 도시된 바와 같이 상기 칩탑재판(6)의 저면은 상기 요부(20)를 통해 패키지몸체(14)의 저면으로 노출될 수도 있다. 따라서 상기 반도체칩(2)의 열은 상기 칩탑재판(6)을 통해 외부로 보다 용이하게 방출된다. 물론, 도2a에 도시된 반도체패키지(100)에서도 상기 칩탑재판(6)과 요부(20)의 바닥면(22) 사이의 거리가 작게 되어 있음으로써 그 반도체칩(2)의 방열 성능이 종래보다 우수하다.Meanwhile, as shown in FIG. 2B, the bottom surface of the chip mounting plate 6 may be exposed to the bottom surface of the package body 14 through the recessed portion 20. Therefore, the heat of the semiconductor chip 2 is more easily discharged to the outside through the chip mounting plate (6). Of course, in the semiconductor package 100 shown in FIG. 2A, the distance between the chip mounting plate 6 and the bottom surface 22 of the recessed portion 20 is reduced, so that the heat dissipation performance of the semiconductor chip 2 is conventional. Better than

상기와 같은 반도체패키지(100)는 통상 몰드(도시되지 않음) 구조를 개선하여 형성할 수 있다. 즉, 봉지재가 채워지는 탑몰드와 바텀몰드 사이에 형성되는 캐비티에 있어서, 상기 바텀몰드의 캐비티 내측 구조가 사다리꼴로 돌출되도록 함으로써 상기와 같이 패키지몸체(14)에 요부(20)가 형성되도록 할 수 있다.The semiconductor package 100 as described above may be formed by improving a mold (not shown) structure. That is, in the cavity formed between the top mold and the bottom mold in which the encapsulant is filled, the inner structure of the cavity of the bottom mold may protrude in a trapezoidal shape so that the recessed portion 20 may be formed in the package body 14 as described above. have.

한편, 도3은 본 발명에 의한 반도체패키지의 실장 방법을 도시한 단면도이다. 여기서 설명의 편의상 하부에 실장된 것을 제1반도체패키지(101), 그 상부에 위치된 것을 제2반도체패키지(102)로 칭한다.3 is a cross-sectional view showing a method for mounting a semiconductor package according to the present invention. Here, for convenience of description, the first semiconductor package 101 and the second semiconductor package 102 are located at the lower portion thereof.

먼저 도시된 바와 같이 통상의 제1반도체패키지(101)를 마더보드(M)에 실장하여 고정시킨다. 비록, 도면에서 상기 제1반도체패키지(101)는볼그리드어레이(Ball Grid Array) 형 패키지를 도시하였지만 이것에만 한정되지 않고, 모든 종류의 반도체패키지가 가능할 것이다.First, as shown in the drawing, the conventional first semiconductor package 101 is mounted on the motherboard M and fixed. Although the first semiconductor package 101 in the drawing shows a ball grid array type package, the present invention is not limited thereto, and all kinds of semiconductor packages may be used.

다음으로, 상기 제1반도체패키지(101)의 상부를 덮으면서 또다른 제2반도체패키지(102)가 실장되도록 하되, 상기 제2반도체패키지(102)는, 다수의 입출력패드(4)가 형성된 반도체칩(2)과, 상기 반도체칩(2)의 저면에 접착제가 개재되어 접착된 칩탑재판(6)과, 상기 칩탑재판(6)의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드(8)와, 상기 내부리드(8)로부터 외측으로 연장된 외부리드(10)와, 상기 반도체칩(2)과 내부리드(8)를 전기적으로 접속시키는 다수의 도전성와이어(12)와, 상기 반도체칩(2), 도전성와이어(12), 칩탑재판(6) 및 내부리드(8) 등을 외부 환경으로부터 보호하기 위해 봉지재로 봉지하여 형성된 패키지몸체(14)를 포함하여 이루어진 것에 있어서, 상기 패키지몸체(14)의 저면에는 일정깊이의 요부(20)(凹部)가 형성되고, 상기 요부(20)에 상기 제1반도체패키지(101)가 위치하도록 한다.Next, another second semiconductor package 102 is mounted while covering the upper portion of the first semiconductor package 101, wherein the second semiconductor package 102 is a semiconductor having a plurality of input / output pads 4 formed thereon. The chip 2, the chip mounting plate 6 bonded to the bottom surface of the semiconductor chip 2 by an adhesive, and a plurality of internal leads formed at a predetermined distance apart from the outer periphery of the chip mounting plate 6 ( 8), an outer lead 10 extending outward from the inner lead 8, a plurality of conductive wires 12 electrically connecting the semiconductor chip 2 and the inner lead 8, and the semiconductor The package body 14 is formed by encapsulating the chip 2, the conductive wire 12, the chip mounting plate 6 and the inner lead 8, etc. with an encapsulant to protect it from the external environment. The bottom surface of the package body 14 is provided with a recessed portion 20 having a predetermined depth, and the first half is formed on the recessed portion 20. And a package body 101 is positioned.

따라서, 제2반도체패키지(102)가 차지하는 실장 면적에 또다른 제1반도체패키지(101)가 실장되도록 함으로써, 그 실장 밀도를 최대화하게 된다.Therefore, the first semiconductor package 101 is mounted on the mounting area occupied by the second semiconductor package 102, thereby maximizing the mounting density.

이상에서와 같이 본 발명은 비록 상기의 실시예에 한하여 설명하였지만 여기 예만 한정되지 않으며, 본 발명의 범주 및 사상을 벗어나지 않는 범위내에서 여러가지로 변형된 실시예도 가능할 것이다.As described above, although the present invention has been described with reference to the above embodiments, only the examples are not limited thereto, and various modified embodiments may be possible without departing from the scope and spirit of the present invention.

따라서, 본 발명에 의한 반도체패키지 및 그 실장 방법에 의하면 반도체칩이탑재된 칩탑재판의 저면을 외부로 노출시키거나 또는 그 칩탑재판 저면의 패키지몸체 두께를 감소시킴으로써 반도체칩의 방열성능을 향상시킴은 물론, 다수의 반도체패키지를 중첩하여 실장할 수 있게 되는 효과가 있다.Therefore, according to the semiconductor package and the mounting method of the present invention, the heat dissipation performance of the semiconductor chip is improved by exposing the bottom of the chip mounting board on which the semiconductor chip is mounted to the outside or by reducing the thickness of the package body of the bottom of the chip mounting board. Of course, there is an effect that can be mounted by overlapping a plurality of semiconductor packages.

Claims (5)

다수의 입출력 패드가 형성된 반도체칩과, 상기 반도체칩의 저면에 접착제가 개재되어 접착된 칩탑재판과, 상기 칩탑재판의 외주연에 일정 거리 이격되어 형성된 다수의 내부리드와, 상기 내부리드로부터 외측으로 연장된 외부리드와, 상기 반도체칩과 내부리드를 전기적으로 접속시키는 다수의 도전성와이어와, 상기 반도체칩, 도전성와이어, 칩탑재판 및 내부리드 등을 외부 환경으로부터 보호하기 위해 봉지재로 봉지하여 형성된 패키지몸체를 포함하여 이루어진 반도체패키지에 있어서,A semiconductor chip having a plurality of input / output pads formed thereon, a chip mounting plate bonded with an adhesive on a bottom surface of the semiconductor chip, a plurality of inner leads formed at a predetermined distance apart from an outer circumference of the chip mounting plate, and from the inner lead An outer lead extending outward, a plurality of conductive wires electrically connecting the semiconductor chip and the inner lead, and encapsulated with an encapsulant to protect the semiconductor chip, the conductive wire, the chip mounting plate and the inner lead from the external environment. In the semiconductor package comprising a package body formed by, 상기 패키지몸체의 저면에는 일정깊이의 요부(凹部)가 형성된 것을 특징으로 하는 반도체패키지.A semiconductor package, characterized in that the bottom portion of the package body is formed with a recessed portion of a predetermined depth. 제1항에 있어서, 상기 요부의 바닥면 전체는 칩탑재판의 저면에 근접하여 형성된 것을 특징으로 하는 반도체패키지.The semiconductor package according to claim 1, wherein the entire bottom surface of the recess is formed close to the bottom surface of the chip mounting plate. 제2항에 있어서, 상기 칩탑재판은 요부의 바닥면을 통해 외부로 노출된 것을 특징으로 하는 반도체패키지.The semiconductor package of claim 2, wherein the chip mounting plate is exposed to the outside through the bottom surface of the recess. 통상의 제1반도체패키지를 마더보드에 실장하는 단계와;Mounting a conventional first semiconductor package on a motherboard; 청구항1 내지 청구항3에 기재된 반도체패키지중 어느 한 반도체패키지를 상기 제1반도체패키지의 상부에 위치하도록 마더보드에 실장하는 단계로 이루어진 것을 특징으로 하는 반도체패키지의 실장 방법.A semiconductor package mounting method comprising the steps of mounting any one of the semiconductor packages according to claim 1 on the motherboard so as to be located above the first semiconductor package. 제4항에 있어서, 상기 제1반도체패키지는 그 높이가 청구항1 내지 청구항3에 기재된 반도체패키지중 어느 하나에 형성된 요부 높이보다 작게 형성된 것을 특징으로 하는 반도체패키지의 실장 방법.The method of mounting a semiconductor package according to claim 4, wherein the height of the first semiconductor package is smaller than the height of recesses formed in any one of the semiconductor packages according to claim 1.
KR1019990065936A 1999-12-30 1999-12-30 semiconductor package and mounting method using it KR20010058586A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030001032A (en) * 2001-06-28 2003-01-06 동부전자 주식회사 Mount structure of multi stack type package
KR20030057186A (en) * 2001-12-28 2003-07-04 동부전자 주식회사 semiconductor package and its manufacturing method
KR101025771B1 (en) * 2004-01-31 2011-04-04 삼성테크윈 주식회사 RFID tag and manufacturing method thereof
KR101091908B1 (en) * 2005-10-24 2011-12-08 삼성테크윈 주식회사 RFID tag and method of manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62261166A (en) * 1986-05-08 1987-11-13 Matsushita Electronics Corp Semiconductor device
JPH02239651A (en) * 1989-03-13 1990-09-21 Hitachi Ltd Semiconductor device and mounting method thereof
JPH05183103A (en) * 1992-01-07 1993-07-23 Fujitsu Ltd Semiconductor device and semiconductor device unit
JPH06350025A (en) * 1993-06-08 1994-12-22 Toshiba Corp Semiconductor device
JPH11243175A (en) * 1998-02-25 1999-09-07 Rohm Co Ltd Composite semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62261166A (en) * 1986-05-08 1987-11-13 Matsushita Electronics Corp Semiconductor device
JPH02239651A (en) * 1989-03-13 1990-09-21 Hitachi Ltd Semiconductor device and mounting method thereof
JPH05183103A (en) * 1992-01-07 1993-07-23 Fujitsu Ltd Semiconductor device and semiconductor device unit
JPH06350025A (en) * 1993-06-08 1994-12-22 Toshiba Corp Semiconductor device
JPH11243175A (en) * 1998-02-25 1999-09-07 Rohm Co Ltd Composite semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030001032A (en) * 2001-06-28 2003-01-06 동부전자 주식회사 Mount structure of multi stack type package
KR20030057186A (en) * 2001-12-28 2003-07-04 동부전자 주식회사 semiconductor package and its manufacturing method
KR101025771B1 (en) * 2004-01-31 2011-04-04 삼성테크윈 주식회사 RFID tag and manufacturing method thereof
KR101091908B1 (en) * 2005-10-24 2011-12-08 삼성테크윈 주식회사 RFID tag and method of manufacturing the same

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