JPH0730437A - Sequence estimating device - Google Patents

Abstract

PURPOSE:To attain a sequence estimating device capable of following up a high speed variation transmission line by small processing quantity or small device size. CONSTITUTION:Non-degenerate states corresponding to respective degenerate states are stored in a non-degenerate state storing circuit 108 and a transmission line response calculating circuit 103 solves an equation determined by a transmission signal sequence candidate, a transmission line response and a received signal only for a transmission signal sequence corresponding to the stored non- degenerate states to obtain respective transmission line response estimated values. Branch metric values corresponding to respective sequences are calculated based upon the transmission line response estimated values and respective signal sequence candidates constituted based upon the stored contents of respective non-degenerate states, viterbi algorithm is driven based upon a degenerated state transition diagram and a maximum likelihood transmission signal sequence is estimated by a Viterbi processor 107.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence estimating device for estimating a transmission signal sequence by following a temporal change in transmission line characteristics.

[0002]

2. Description of the Related Art A maximum likelihood sequence estimator (MLSE) is known as an equalization system with the best equalization capability (for example,
Reference 1: G. D. Forney, "Maximum L
ikelihood Sequence Estima
tion of Digital Sequences
in the presence of inter
symbol interference, "IEEE
Transaction on Information
on Theory, vol. IT-18, no. Three
May 1972). The maximum likelihood sequence estimator generally comprises a single channel response estimator, and this channel response estimator is used when receiving a channel for which channel channel estimation is known.

Also, an adaptive maximum likelihood sequence estimation apparatus has been proposed which follows the temporal variation of the characteristic of the transmission line when the characteristic of the transmission channel varies with time (for example, Document 2). : G. Ungerboeck, "Adapt
Ive Maximum Like Likehood Re
caver for Carrier-Modula
ted data transmission sys
tems, “IEEETransaction on
Communications, vol. COM-2
2, no. 5, May 1974). The adaptive maximum likelihood sequence estimator first obtains a channel response when receiving a known sequence, and thereafter, when receiving an information data sequence, operates the channel estimator using an adaptive algorithm to sequentially transmit the channel response. It is characterized in that it updates to follow the temporal fluctuations of the transmission line characteristics. However, in the adaptive maximum likelihood sequence estimation device, the adaptive operation of the transmission channel estimator cannot catch up when the transmission channel characteristic changes rapidly.

On the other hand, Japanese Patent Application No. 2-203436 proposes a sequence estimating device of a new type capable of following a transmission line that changes at high speed. This device is characterized in that the Viterbi algorithm is applied by estimating the corresponding transmission path response for each series, assuming that not only the transmission signal series but also the characteristics of the transmission path are unknown. The transmission path response is estimated by solving the transmission path equation determined by the transmission signal series candidate, the transmission path response, and the received signal for each series. Since this corresponds to sequentially obtaining the optimum solution of the transmission line response, the sequence estimating device of Japanese Patent Application No. 2-203436 can follow a high-speed transmission line fluctuation. Less than,
This device will be referred to as a basic type blind Viterbi equalizer, or simply a basic type.

[0005]

However, in the basic blind Viterbi equalizer, the state of the state transition diagram (trellis diagram) to which the Viterbi algorithm is applied has the number of symbols required for the channel response calculation as its length. Since it is given by the transmission signal sequence candidate of, the number of states becomes large when the number of symbols required for the transmission path response calculation is large, and the circuit for realizing the sequence estimation device becomes complicated, or realized by using a digital signal processor or the like. However, there is a drawback in that the amount of processing required is extremely large.

Therefore, an object of the present invention is to provide a sequence estimation device capable of following a transmission line that changes at high speed with a smaller number of states, that is, with a simpler circuit or a smaller processing amount. It is in.

[0007]

A sequence estimation device according to a first aspect of the present invention inputs a plurality of sample values from a register for storing a plurality of sample values of a received signal,
A transmission line response calculation circuit that estimates a transmission line response at the current time only for a plurality of designated signal sequences from M (integer of 2 or more) value signal sequences that may be transmitted, and the transmission line response The legitimacy of the value of the transmission line response at the current time with respect to the plurality of signal sequences obtained by the calculation circuit is checked, and if the value is correct, the output of the transmission line response calculation circuit is checked, and if it is not, the same signal sequence is output. A transmission line response inspection circuit that outputs the transmission line response estimation value at the previous time as a transmission line response estimation value at the current time, and the transmission line response estimation value at the current time output by the transmission line response inspection circuit are stored. Along with, the transmission line response storage circuit that supplies the transmission line response estimation value stored at the previous time to the transmission line response inspection circuit in reverse, and the transmission line response estimation value at the current time output by the transmission line response inspection circuit. Each degenerate letter A branch metric calculation for obtaining a virtual reception signal point for each of the plurality of sequences based on the three of the non-degenerate state corresponding to and the transmission signal candidate at the current time, and obtaining the distance from the sample value of the reception signal. A circuit, a Viterbi processor that receives the output of the branch metric calculation circuit while outputting a non-degenerate state corresponding to each degenerate state at each time, and determines a received signal by a Viterbi algorithm, and stores the non-degenerate state. A non-degenerate state storage circuit that specifies the plurality of signal sequences for calculating the channel response to the channel response calculation circuit, and estimates the transmission signal sequence based on the degenerated state transition diagram. It is characterized by performing.

The sequence estimating apparatus of the second invention is such that a register for storing a plurality of sample values of a received signal and a plurality of M (2 or more) which may be transmitted by inputting a plurality of the sample values from the register. An integer) value signal sequence, and a transmission line response calculation circuit that estimates the transmission line response at the current time only for a plurality of designated signal sequences, and the current transmission line response calculation circuit for the plurality of sequences obtained by the transmission line response calculation circuit. The validity of the value of the transmission line response at the time is checked, and if it is valid, the output of the transmission line response calculation circuit is used. A transmission path response conversion circuit that outputs a value converted according to a rule defined by the storage of the non-degenerate state as a transmission path response estimation value at the current time, and the transmission path response at the current time output by the transmission path response conversion circuit. A transmission line response storage circuit that stores a constant value and supplies the transmission line response estimation value stored at the previous time to the transmission line response conversion circuit in reverse, and the transmission line response at the current time output by the transmission line response conversion circuit. Based on the estimated value, the non-degenerate state corresponding to each degenerate state, and the transmission signal candidate at the current time, virtual reception signal points for each sequence of the plurality of sequences are obtained, and A branch metric calculation circuit for obtaining a distance and a non-degenerate state corresponding to each degenerate state at each time, receiving the output of the branch metric calculation circuit and determining the maximum likelihood sequence by the Viterbi algorithm, the maximum likelihood sequence Of the non-degenerate state corresponding to the oldest state of the non-degenerate state, a non-degenerate state storage circuit for storing the non-degenerate state, and the non-degenerate state A state conversion circuit for converting the non-degenerate state given by a storage circuit and designating the plurality of signal sequences for calculating the transmission line response to the transmission line response calculation circuit based on the converted state. ,
It is characterized in that the transmission signal sequence is estimated based on the degenerated state transition diagram.

[0009]

In the basic blind Viterbi equalizer, each state (referred to as a basic state or a non-degenerate state) of the state transition diagram (trellis diagram shown in FIG. 4) to which the Viterbi algorithm is applied is the transmission path response. It is given by a transmission signal sequence candidate whose length is the number of symbols required for calculation.
On the other hand, in the sequence estimation device of the present invention, the state of the trellis diagram (this is called the degenerate state) is given by the transmission signal sequence candidates in which the number of symbols is less than the number required for the channel response calculation. Then, for each degenerate state, the past symbols are supplemented from the history of the survivor paths at each time, and the transmission signal sequence candidates necessary for the transmission path response calculation, that is, the basic state corresponding to the state is reproduced, and Is used to estimate the transmission path. Therefore, according to the present invention, it is possible to realize a sequence estimation device capable of following a transmission line that changes at high speed, while significantly reducing the number of states as compared with the basic form.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, first, Japanese Patent Application No. 2-2
The basic blind Viterbi equalizer shown in 03436 will be described and then the invention will be described in comparison therewith.

A basic branded Viterbi equalizer is shown in FIG. In the basic form, the transmission path response at time t is obtained for each of a plurality of potential signal sequence candidates by the least squares method, and these are used in the branch metric calculation at time (t + 1).

In the following, it is assumed that the transmission path impulse response at time t is (L + 1) symbols, and this is taken as the vector h.
_{It is represented by t} ^T = [h _t ⁰ , h _t ¹ , ..., H _t ^L ]. The received signal {r _t} is gradually stored in the register 302 at each time. Now, the received signal at time (t + 1) is the register 30
Pay attention when it is input to 2. At this time, register 3
Transmit signal to the delay element group 02 is N times amount, that is, stored in the form of a vector _{[r t ... r t -N +} 1].
This is the received signal vector r _t at time t.

[0013] ^{_{r t T = [r t,}} r t - 1, ..., r t - N + 1] (1) At time (t + 1), the components of the vector r _t is towards the transmission path calculation circuit 303 outputs To be done.

The transmission path calculation circuit 303 obtains the transmission path response at time t for each of a plurality of signal sequences that may be transmitted using the vector r _t by the least square method. Now, a sequence in which signals transmitted by time t are collected for L times is a vector S _t ^T = [s _t , s _{t -1} , ... S
_{t − L} ], where v _t is the additive transmission line noise including the observation process independent of the transmitted signal, the received signal r _t at time t is a vector as shown in equation (1). It is given by the sum of the noise and the convolution of h _t with the vector s _t .

R _t = s _t ^T · h _t + v _t (2) Hereinafter, the equation (1) is referred to as a transmission line equation at time t. When N transmission path equations are put together from time t−N + 1 to time t, they are multiplied by the equation (3).

R _t = S _t ^T · h _t + v _t (3) Here, the transmission signal matrix S _t and the noise vector v _t are defined below.

[0017]

V _t ^T = [v _t , v _{t -1} , ..., v _{t -N + 1} ] (5) The transmission line characteristic calculation circuit 303 is (condition) N symbols (N
The fluctuation of the transmission line between ≧ L + 1) can be ignored, that is, h _t = h _{t −1} = h _{t −N +1} . Under the condition that the transmission line impulse response vector h _t is least squares estimated from the transmission line equation for N times of the equation (3). Specifically, a plurality of signal sequences that may be sent, i.e. _{(s t, s t - 1} , ..., s t - L - N + 1) respectively transmitted to all signal sequences contemplated The signal matrix S _t is constructed, and the transmission line impulse response vector h _{t, 1 s} is obtained by the equation (6).

H _{t, 1 s} = (S _t ^T · S _t ) ⁻¹ · S _t ^T · r _t (6) Particularly, the number of received signals (N) used for impulse response estimation.
Is equal to the number of transmission line responses (L + 1), the transmission signal matrix S _t is a square matrix. Therefore, the transmission line response estimation value by least square estimation is simply obtained by multiplying the reception signal by the inverse matrix of the transmission signal matrix S _t. Is obtained.

[0020] _{h t, 1 s = S t} - to ¹ · r _t (7) Based on these estimates, the branch metric calculation circuit 30
4 is all combinations of transmitted signals (s _t , _{st -1} ,
, St _{-L-N + 1} , the likelihood (branch metric) shown in Expression (8) is calculated every time.

M _t (s _t , _{st − 1} , ..., _{St − L − N + 1} : _{st + 1} ) = | rt _{+ 1-} s _{t + 1} ^T · h _{t, 1 s} | ² (8) Then, the Viterbi processor 305 determines the total time t of this value.
The Viterbi algorithm is used to find the transmission signal sequence over all times that minimizes the value (pastomeric) determined by the sum over.

For simplicity, a binary signal, a two-wave model (L =
Taking the case of estimating the transmission path response from two (N = 2) received signals in 1) as an example, the basic operation is as follows. The channel response is the vector h _t ^T = [h _t ⁰ , h _t ¹ ]
The transmission line equations for two times can be written by equation (9).

[0023]

In its basic form, the state of the trellis diagram for operating the Viterbi algorithm is the combination of the three transmitted signals appearing in the components of the transmitted signal matrix S _t , ie (s _t ,
_{s t -1, s t - 2} ) is determined. Let binary transmission signals be {1, -1}, and for the sake of convenience, use them as {1, 0}.
In If to express, the signal sequence candidates that may be transmitted _{(s t s t - 1 s} t - 2) , the (000),
(001), (010), (011), (100),
There are eight ways: (101), (110), and (111). Therefore, the number of states of the basic form is 8, and the state transition diagram can be written as shown in FIG. In Figure 4, in accordance with the set convention symbols in the ellipse representing each state, the order of older time _{s t + 2 s t - 1} s t) has symbolic representations, for example state (110), s _{t + 2} = 1, _st -1 = 1, s
_It represents _t = 0. Further, in FIG. 4, a line connecting each state represents a state transition, and a signal candidate (hereinafter, referred to as a transition signal) sent with the state transition is a state placed on the right side of the state transition (this is a transition destination). It is called a state, and the state placed on the left side of the state transition is called the transition source state) and appears in the lowest digit (rightmost digit).

The transmission line characteristic calculation circuit 303 has a transmission line response vector h _t ^T = [h _t ⁰ , h _t ¹ ] for each of them.
And find the least squares solution of the vector h _{t, 1 s} (0,
0,0), vector h _{t, 1 s} (0,0,1), vector h _{t, 1 s} (0,1,0), vector h
_{t, 1 s} (0 _{, 1, 1} ), vector h _{t, 1 s} (1,
0,0), vector h _{t, 1 s} (1,0,1), vector h _{t, 1 s} (1,1,0), vector h
Let _{t, 1 s} (1 _{, 1,} 1). Vector h
_{t, 1 s (s t -} 2, s t - 1, s t) is, s _{t - 2,}
Transmission line response vector h _t ^T = [h _t ⁰ , h _t ¹ ] when s _{t -1} and s _t are either 0 or 1, respectively.
Indicates.

The branch metric calculation circuit 304 uses the vector h calculated by the transmission line characteristic calculation circuit 303.
_{t, 1 s (s t -} 2, s t - 1, s t) and the time (t +
From the received signal r _{t +1 in} 1), the following 16 branch metrics are obtained.

[0027]

Here, M _t (s _{t -2, st -1} ,
s _t: s _{t + 1) is, s t, s t - 1} , s t - 2 and s
It is a branch metric value when _{t + 1} is set to either 0 or 1. These correspond to the respective state transitions 7a to 7p shown in FIG. 7, and the corresponding relationship is shown in FIG.
2 in detail. These branch metric _{{M t (s t - 2} , s t - 1, s t: s t + 1)} is output to the Viterbi processor 305, a Viterbi processor 3
Reference numeral 05 performs maximum likelihood reception by selecting a path having the smallest metric, and mainly receives signals from the terminal 306. The operation of the Viterbi processor 305 is described in Reference 1,
Since it is exactly the same as that described in 2,
Detailed description thereof will be omitted.

Although the metric is calculated as the squared error as shown in the equation (10), the equation (10) is developed so that it can be used for ordinary maximum likelihood estimation, and literatures 1 and 2 are used.
Or a type using a matched filter described in, further omitting common r _{t + 1} ² term to all branch metrics at the same time, or the maximum metric by changing the sign of the expression (10) It is obvious that the same effect can be obtained even if it is obtained.

Now, in the basic form, the transmission signal is a binary signal,
Even if the transmission line is a two-wave model and the number of received signals to be observed is two, eight states are required as described above. However, the number of states can be reduced to 4 and even 2 using the present invention. Specifically, in the present invention, the combination of the states of the trellis diagram for operating the Viterbi algorithm, three transmit visual signals appearing at the component of the transmission signal matrix _{S t (s t - 2 s} t - 1 s t) Instead, degenerate it once and combine two transmitted signals (s ¹ _t-1 s ¹ _t )
Or by degenerating twice, one transmission signal (s ²
Each state is represented by _t ). In the following, (s _t -2 s
_{t - 1} s _t) and ^{_{(s 0 t - 2 s 0}} t - to ₁ s ⁰ _t) and also write it.

There are the following two methods for degenerating the state. 1) Simple degeneracy: Simple degeneracy is a method of degenerating the state by the commonality of the lower digits of the symbolic representation of the state. It is realized by erasing the upper digits of the symbolic representation of the basic state of FIG. 4 one by one. If degenerate k times, the symbolic representation of the state is reduced by k digits. From a different point of view, it is a method of extracting a plurality of recent transmission signal candidates from the transmission signal candidates forming the basic state and setting them in a degenerate state. For example, the degenerate state for the basic state (110) is (110) → (10) in one degeneration (this is called first-order degeneracy), and is (10) in the second degeneration (this is called second-order degeneracy). ) → (0). Conversely, the primary degenerate state (00) has two basic states (000) and (100), and the secondary degenerate state (0) has four basic states (000), (100),
It may correspond to (010) and (110). However, each degenerate state corresponds to only one of the corresponding basic states when the time is designated.

FIG. 5 shows a trellis diagram when the trellis diagram of FIG. 4 is degenerated by one simple degeneration. In Figure 5, the set of symbols in the ellipse representing each degenerate state old order of time in accordance with convention _- has symbolic representations of (s _{t 1} s _t), for example, the state (10), s _{t - 1} = 1 , _St = 0. Also, shown in parentheses in the ellipse of each degenerate state are the corresponding two basic states. The correspondence between the state transitions in the trellis diagram of FIG. 5 and the state transitions in the basic trellis diagram of FIG. 4 is shown in FIG.

Further, since the transition signal between the simple degenerate states is the same regardless of the corresponding basic state, the transition signal can be specified by storing the degenerate state. For example, the transition from the primary degenerate state (00) to (00) is 0 regardless of the basic state corresponding to the transition source state (000) or (100). 2) Rotational degeneration: A signal sequence (s ⁰ _t- 2) representing a basic state
_{^{s 0 t - 1 s 0 t}} ) in the phase rotation in the there is also a method to adapt the same to each other in the same degenerate state. The degenerate state of rotational degeneracy is given recursively.

First-order degeneration: (s ¹ _{t -1} s ¹ _t ) = (s
_{^{0 t - 2 '+ s 0}} t - 1 s 0 t - 2' + s 0 t) However, the addition in the case of M-value signal, the sum of mod M.

Also, s ⁰ _t -2 '+ s ⁰ _{t -2} = 0
(Mod M) Second-order degeneracy: (s ² _t ) = (s ¹ _{t −1} ′ + s ¹ _t ) However, when the addition is an M-value signal, the sum of mod M.

Also, s ¹ _{t -1} '+ s ¹ _{t -1} = 0
(Mod M) For example, the rotationally degenerate state for the basic state (110) is given by (110) → (01) in the first-order degeneracy and (01) → (1) in the second-order degenerate. Conversely, the primary degenerate state (00) has two basic states (000) and (111), and the secondary degenerate state (0) has four basic state (00).
0, (111), (011), (100). However, each degenerate state corresponds to only one of the corresponding basic states when the time is designated. Figure 6
4 shows a trellis diagram when the trellis diagram of FIG. 4 is degenerated by rotational degeneracy. Since the transition symbol between the rotationally degenerate states is determined by the corresponding transition symbol between the basic states, the rotationally degenerate state cannot be uniquely determined. For example,
The transition from the primary degenerate state (00) to (00) is 0 when the basic state corresponding to the transition source state is (000), but is 1 when (111). Therefore, the transition signal is specified from the basic state stored for each degenerate state.

Since the number of states in the degenerate trellis diagram is small, the number of transitions in the entire trellis diagram is also small. If the Viterbi algorithm is operated based on this trellis diagram, the processing amount of the Viterbi processor can be reduced exponentially.

On the other hand, the transmission line response calculation that enables the sequence estimation device to perform high-speed tracking is performed as follows on the degenerated trellis diagram. First, in the Viterbi algorithm, it is made to memorize from the history of the survival series what kind of basic state each degenerate state at each time actually corresponds to. Then, the transmission line response calculation is performed by combining the transmission signals (s _t , s _{t -1} , ..., S) corresponding to the basic state.
_{t-L-N + 1} ) to solve the transmission line equation, and use the obtained transmission line response for branch metric calculation as a transmission line response estimation value for the degenerate state. In the branch metric calculation at time (t + 1), the transmission signal sequence candidate for obtaining the virtual reception signal point is time t
Sequence (s _t , _{st -1} , ..., s) obtained by removing the oldest signal from the transmission signal signal related to the non-degenerate state corresponding to the degenerate state of
_t-L-N ) and a new transmission signal candidate at time (t + 1). That is, the channel response estimate obtained previously and _{(s t + 1, s t} , ...,
s _{t -L -N} ) and a virtual reception signal point is calculated, and the distance between this and the actual reception signal is calculated and used as a branch metric. The transmission line response calculation and the branch metric calculation enable the transmission line estimation at every time by the direct solution even in the sequence estimating apparatus of the present invention which operates based on the degenerated trellis diagram. Further, in the present invention, the transmission line response calculation need not be performed for all the basic states, but for the number of degenerate states, and the calculation amount related to the transmission line response estimation is exponentially reduced. Has the advantage that

As described above, it is possible to realize a sequence estimation device having a transmission path estimation function similar to that of the basic type, with a smaller processing amount and storage amount than those of the basic type blind Viterbi equalizer.

FIG. 1 shows an embodiment of the sequence estimating apparatus according to the first invention. The sequence estimation device of FIG. 1 operates the Viterbi algorithm based on the simple degenerate trellis diagram shown in FIG.

The receiver input rt at the time t supplied to the input terminal 101 is stored in the register 102 and sent to the branch metric calculation circuit 104. N from the time t−N + 1 stored in the register 102 to the time t
The received signal signals are input to the transmission path response calculation circuit 103. The transmission line response calculation circuit 103 calculates the vectors h _{t and ls} according to the equation (6) or the equation (7) only for the basic state corresponding to each degenerate state of FIG. 5 at each time. For example, as shown in FIG. 8, (00) at time t,
The basic states corresponding to the degenerate states (01), (10), and (11) are (100), (101), and (01), respectively.
0) and (011) (basic state underlined), the transmission line response calculation is performed only for these four signal sequences. On the other hand, in the conventional sequence estimation device of FIG. 3, calculation is executed for eight signal sequences (all basic states) from (000) to (111).

For a matrix S _t ^T S _t or a combination of transmission signals with which the matrix S _t is singular, the transmission line response calculation circuit 103 outputs a predetermined value (for example, 0) and the vectors h _{t, ls} Is transmitted to the transmission line response inspection circuit 105. Here, the transmission line response estimation value obtained when the state is not indefinite is called a valid estimation value. The transmission line response inspection circuit 105 uses the individual transmission line response vectors h calculated by the transmission line response calculation circuit 103.
Check if _{t and ls} are indeterminate. For an indefinite state, the surviving sequence transitioning to that state has the channel response estimation value adopted in the state at the previous time and replaces it with the channel response estimation value at the current time. For example, when the basic state corresponding to the degenerate state (01) at the time t is (101), the signal matrix S _t ^T S _t or the matrix S _t becomes singular. At this time, as the transmission line response estimation value for the degenerate state (01) at time t, the degenerate state (1) at the previous time (t-1) of the surviving path transiting to the degenerate state (01) is obtained.
0) (because the stored value of the basic state at time t is (10
1), the degenerate state at time (t-1) is (1
0)) is used instead. The transmission line response storage circuit 106 supplies the estimated transmission line response value at the previous time. On the other hand, if not indefinite, the transmission path response at the current time calculated by the transmission path response calculation circuit 103 is used as it is. The transmission line response estimated value at the present time obtained in this way is stored in the transmission line response storage circuit 106 together with the basic state having the value.

The current time channel response estimation value vector h _t 'obtained for the degenerate state is supplied to the branch metric calculation circuit 104. Branch metric calculation circuit 1
Reference numeral 04 individually calculates the branch metric determined by the equation (8) for all transitions from the degenerate state based on the current time channel response estimation value vector _ht 'provided by the channel response inspection circuit 105. . Here, in the branch metric calculation at time (t + 1), the transmission signal sequence candidate for obtaining the virtual reception signal point is a sequence (excluding the oldest signal from the transmission signal signal related to the basic state corresponding to the degenerate state at time t). _{s t, s t - 1,} ..., s t - L - N) and time (t
+1) in combination with a new transmission signal candidate. That is, the transmission line response estimated value obtained earlier and (s
^{_{t + 1, s t, ...}} , s t - L - determined virtual received signal point from the _N), the distance the calculated branch metric and the actual received signal and this. When the degenerate state at time t is (01), a virtual reception point is obtained for a combination of the latest signal 1 and a new transmission signal candidate 0 or 1 at time (t + 1), that is, the sequence 10 or the sequence 11.

The branch metric calculation circuit 104 is shown in FIG.
The eight branch metric values calculated for the transitions shown in No. 3 are output to the Viterbi processor 107. The Viterbi processor 107 searches for a sequence in which the sum of all the times of the metric of the equation (8) is the minimum by the Viterbi algorithm, and outputs the determination output to the output terminal 109. At the same time, the Viterbi processor 107 checks the basic state corresponding to the degenerate state at each time from the history of the surviving paths and outputs it to the non-degenerate state storage circuit 108. For example, when the degenerate state (11) at time (t + 1) transits from the degenerate state (01) at time t described above, the basic state for the degenerate state (11) is (011), and this value is the degenerate state (11). ) Non-degenerate state storage circuit 108
Be registered with. The stored value of the basic state is used for the transmission line response calculation at time (t + 1) and the branch metric calculation at time (t + 2). The operation of the Viterbi processor 107 is the same as that of the sequence estimation devices of References 1 and 2 except that it is based on the degenerated trellis diagram, and thus detailed description thereof will be omitted.

FIG. 2 shows an embodiment of the sequence estimating apparatus according to the second invention. In an example of estimating a channel response from two (N = 2) received signals in a binary signal, two-wave model (L = 1), the sequence estimation device of FIG. 2 is degenerate as shown in FIG. The Viterbi algorithm is operated based on the trellis diagram. Although the degenerate method is different, operating the Viterbi algorithm on the trellis diagram based on the degenerate state is common to the first invention.

The receiver input r _t at the time t supplied to the input terminal 201 is stored in the register 202 and sent to the branch metric calculation circuit 204. From time t-N + 1 stored in the register 202 to time t, N
The received signal signals are input to the transmission path response calculation circuit 203. The transmission line response calculation circuit 203 differs from the transmission line response calculation circuit 103 of FIG. 1 only in accordance with the equation (6) or the equation (7) according to the equation (6) or the equation (7) for the basic state corresponding to the predetermined first-order degenerate state. Compute _{t, ls} . For example, as shown in FIG. 9, (00), (0
The basic states corresponding to the degenerate states of (1), (10), and (11) are (111), (001), and (10), respectively.
1), (100) (underlined basic form), (000), (001), (010), (01
It suffices to perform the transmission path response calculation only for the four predetermined signal sequences of 1).

This is for the following reason. For example, in FIG.
, The non-degenerate state (000) and (111) share the degenerate state (00), but the transmission line response vectors h _{t, ls} (000) and (111) obtained by using (000) are calculated. The transmission line response vector h _{t, ls} (111) obtained by calculation using is rotated by 180 degrees. In the transition from (00) to (01), the transition signal is 1 when the basic state is (000) and 0 when it is (111). When the virtual reception signal point is obtained, the values are exactly the same. Therefore, the same metric will be calculated.

Therefore, in the rotation degenerate state, in order to calculate the transmission line response, the transmission line response for any one of the basic degenerate states is fixed ((000) to (000). ) And so on). 16 and 17 are examples of this conversion rule. The state conversion circuit 209 is a circuit that converts a basic state into a basic state having the same first-order degenerate state according to a predetermined conversion rule, and the transmission line response calculation circuit 203 is only for these predetermined basic states. The transmission line response may be calculated.

For a matrix S _t ^T S _t or a combination of transmission signals with which the matrix S _t is singular, the transmission path response calculation circuit 203 outputs a predetermined value (for example, 0), and the vectors h _{t, ls} Is transmitted to the transmission line response conversion circuit 205. The transmission line response conversion circuit 205
It is checked whether or not the individual transmission line response vectors h _{t and ls} calculated by the transmission line response calculation circuit 203 are indefinite. If it is not indefinite, the transmission path response at the current time calculated by the transmission path response calculation circuit 203 is used as it is. on the other hand,
The processing when the output of the transmission line response calculation circuit 203 is improper (unique) is different from that of the transmission line response inspection circuit 105. For an indefinite state, the transmission line response estimation value at the current time is calculated based on the transmission line response estimation value adopted in the state of the previous time of the surviving sequence transitioning to the state. For example, in FIG. 9, when the basic state corresponding to the degenerate state (00) at time t is (000), the signal matrix S _t ^T S _t
Alternatively, the matrix S _t becomes singular. According to the conversion rule of FIG. 16, it is necessary to calculate the response to the basic state (000) as the transmission line response estimation value for the degenerate state (00) at time t. In addition, the degenerate state at the previous time t-1 of the surviving path transiting to the degenerate state (00) is (1
In the case of 1), the transmission line response stored in the transmission line response storage circuit 206 is a value for the basic state (011). Here, there is no transition from the basic form state (011) to the basic form state (000), and there is the transition from the basic form state (011) to the basic form state (111). The basic state (111) may directly inherit the response of the basic state (011). Since the transmission line response of the basic state (000) is obtained by rotating the transmission line response of the basic state (111) by 180 degrees, the value for the basic state (011) at the previous time is set as the response to the basic state (000). It needs to be rotated 180 degrees. As described above, in the rotation degeneracy, it is necessary to use the value obtained by rotating the previous time transmission path response according to the transition at the singular time. The transmission path response estimated value at the current time obtained in this way is stored in the transmission path response storage circuit 206.

The current time channel response estimation value vector h _t 'obtained for the degenerate state is supplied to the branch metric calculation circuit 204. Branch metric calculation circuit 2
Reference numeral 04 individually calculates the branch metric defined by the equation (8) for all transitions from the degenerate state based on the current time channel response estimation value vector h _t 'provided by the channel response conversion circuit 205. . Here, in the branch metric calculation at time (t + 1), the transmission signal sequence candidate for obtaining the virtual reception signal point is a sequence (excluding the oldest signal from the transmission signal signal related to the basic state corresponding to the degenerate state at time t). _{s t, s t - 1,} ..., s t - L - N) and time (t
+1) in combination with a new transmission signal candidate. That is, the transmission line response estimated value obtained earlier and (s
^{_{t + 1, s t, ...}} , s t - L - determined virtual received signal point from the _N), the distance the calculated branch metric and the actual received signal and this. For the degenerate state at time t (10), a virtual reception point is obtained for the combination of the latest signal 0 and the new transmission signal candidate 0 or 1 at time (t + 1), that is, the sequence 00 or 01.

The branch metric calculation circuit 204 is shown in FIG.
The eight branch metric values calculated for the transitions shown in No. 4 are output to the Viterbi processor 207. The Viterbi processor 207 searches for a sequence in which the sum of all the times of the metric of Expression (8) is the minimum by the Viterbi algorithm, and outputs the determination output to the output terminal 210.

In the rotation degenerate state, the transition symbols between the degenerate states are determined depending on the transition symbols between the basic states.
The transition signal is identified by first checking the degenerate state at a time point that is a specific time earlier than the current time with respect to the sequence in which the sum of all the time points of the metric is the smallest, and then determining the non-correlation state corresponding to the past degenerate state. This is performed by searching the non-degenerate state storage circuit 208 for the degenerate state and finally outputting the transition signal value of the non-degenerate state to the output terminal 210.

At the same time, the Viterbi processor 207 checks the basic state corresponding to the degenerate state at each time from the history of the surviving paths and outputs it to the non-degenerate state storage circuit 208. For example, when the degenerate state (11) at time (t + 1) transits from the degenerate state (01) at time t described above, the basic state for the degenerate state (11) is (011), and this value is the degenerate state (11). ) Is registered in the non-degenerate state storage circuit 208 as the non-degenerate state. The stored value of this basic state is the transmission line response conversion at time (t + 1) and the time (t + 2).
It is used to calculate the branch metric of. The operation of the Viterbi processor 207 is the same as that of the sequence estimation apparatus of References 1 and 2 except that it is based on the degenerated trellis diagram, and thus detailed description thereof will be omitted.

In the above embodiments, an example in which the transmission signal has a binary or two-wave level has been described. However, in the case of a multi-valued signal other than a binary signal, even when there are a plurality of responses of three or more waves, It is also clear that the sequence estimation device of the invention is effective. Further, in the above embodiment, an example of the state transition diagram in which the base state transition diagram is degenerated once is described, but the state transition diagram in which the sequence estimation device of the present invention is degenerated twice or more is used. It is also possible to operate based on the figure.

[0055]

As described above in detail, the present invention is
By using the degeneracy of states, it is possible to operate the Viterbi algorithm on a transition diagram with a reduced number of states. Therefore, less storage and processing than the conventional method,
Alternatively, it is possible to provide a sequence estimation device that follows a transmission line that changes at high speed with a small device scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sequence estimation device according to the first invention.

FIG. 2 is a block diagram showing an embodiment of a sequence estimation device according to the second invention.

FIG. 3 is a block diagram showing a conventional sequence estimation device.

[Fig. 4] Example of basic state transition diagram before degeneracy

FIG. 5 is an example of a degenerate state transition diagram which is the basis of the operation of the sequence estimation device of the first invention.

FIG. 6 is an example of a degenerate state transition diagram which is the basis of the operation of the sequence estimation device of the second invention.

FIG. 7 is a trellis diagram for explaining branch metric calculation of a conventional sequence estimation device.

FIG. 8 is a trellis diagram for explaining branch metric calculation of the sequence estimation device of the first invention.

FIG. 9 is a trellis diagram for explaining a branch metric calculation of the sequence estimation device of the second invention.

FIG. 10 is a state conversion table for primary simple degeneracy

FIG. 11 is a state conversion table for first-order rotational degeneration.

FIG. 12 is a table for explaining branch metric calculation of a conventional sequence estimation device.

FIG. 13 is a table for explaining branch metric calculation of the sequence estimation device of the first invention.

FIG. 14 is a table for explaining a branch metric calculation of the sequence estimation device of the second invention.

FIG. 15 is a table for explaining branch metric calculation of the sequence estimation device of the second invention.

16 is a table for explaining conversion rules of the state conversion circuit 209. FIG.

FIG. 17 is a table for explaining conversion rules of the state conversion circuit 209.

[Explanation of symbols]

 101, 201, 301 Input terminals 102, 202, 302 Registers 103, 203, 303 Transmission line response calculation circuit 105, 106 Matrix switch 104, 204, 304 Branch metric calculation circuit 105 Transmission line response inspection circuit 205 Transmission line response conversion circuit 106 , 206 Transmission line response storage circuit 107, 207, 305 Viterbi processor 108, 208 Non-degenerate state storage circuit 209 State conversion circuit 109, 210, 306 Output terminal

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 13, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a sequence estimation device according to the first invention.

FIG. 2 is a block diagram showing an embodiment of a sequence estimation device according to the second invention.

FIG. 3 is a block diagram showing a conventional sequence estimation device.

[Fig. 4] Example of basic state transition diagram before degeneracy

FIG. 5 is an example of a degenerate state transition diagram which is the basis of the operation of the sequence estimation device of the first invention.

FIG. 6 is an example of a degenerate state transition diagram which is the basis of the operation of the sequence estimation device of the second invention.

FIG. 7 is a trellis diagram for explaining branch metric calculation of a conventional sequence estimation device.

FIG. 8 is a trellis diagram for explaining branch metric calculation of the sequence estimation device of the first invention.

FIG. 9 is a trellis diagram for explaining a branch metric calculation of the sequence estimation device of the second invention.

FIG. 10 is a state conversion chart of first-order simple degeneracy.

FIG. 11 is a state conversion diagram of the first-order rotational degeneration.

FIG. 12 is a diagram for explaining branch metric calculation of a conventional sequence estimation device.

FIG. 13 is a diagram for explaining a branch metric calculation of the sequence estimation device of the first invention.

FIG. 14 is a diagram for explaining branch metric calculation of the sequence estimation device of the second invention.

FIG. 15 is a diagram for explaining a branch metric calculation of the sequence estimation device of the second invention.

16 is a chart for explaining a conversion rule of the state conversion circuit 209. FIG.

FIG. 17 is a chart for explaining the conversion rule of the state conversion circuit 209.

[Explanation of reference numerals] 101, 201, 301 Input terminals 102, 202, 302 Registers 103, 203, 303 Transmission line response calculation circuit 105, 106 Matrices switch 104, 204, 304 Branch metric calculation circuit 105 Transmission line response inspection circuit 205 Transmission Path response conversion circuit 106, 206 Transmission path response storage circuit 107, 207, 305 Viterbi processor 108, 208 Non-degenerate state storage circuit 209 State conversion circuit 109, 210, 306 Output terminal

Claims (2)

[Claims] 1. A register for storing a plurality of sample values of a received signal, and a plurality of the sample values input from the register, and designated from an M (integer of 2 or more) value signal sequence that may be transmitted. The transmission path response calculation circuit for estimating the transmission path response at the current time only for the selected plurality of signal series, and the transmission path response at the current time for the plurality of signal series obtained by the transmission path response calculation circuit. The validity of the value is checked, and if it is valid, the output of the transmission path response calculation circuit is used, and if it is not valid, the transmission path response estimation value at the previous time for the same signal sequence is used as the transmission time response estimation value at the current time. The transmission line response inspection circuit that outputs the transmission line response inspection circuit and the transmission line response estimation value at the current time output by the transmission line response inspection circuit are stored, and the transmission line response estimation value stored at the previous time is reversed to the transmission line response. Inspection A transmission line response storage circuit to be supplied to the circuit, a transmission line response estimation value at the current time output by the transmission line response inspection circuit, a non-degenerate state corresponding to each degenerate state, and a transmission signal candidate at the current time. A branch metric calculation circuit that obtains a virtual received signal point for each of the plurality of streams based on the above, and a branch metric calculation circuit that obtains a distance from the sample value of the received signal, and a non-degenerate state corresponding to each degenerate state at each time. A Viterbi processor that receives the output of the branch metric calculation circuit while determining the received signal by a Viterbi algorithm, stores the non-degenerate state, and calculates a transmission line response to the transmission line response calculation circuit. A non-degenerate state storage circuit that specifies a plurality of signal sequences, and estimates a transmission signal sequence based on a degenerated state transition diagram. That sequence estimation apparatus. 2. A register for storing a plurality of sample values of a received signal and a plurality of the sample values input from the register, and designated from an M (integer of 2 or more) value signal sequence that may be transmitted. Transmission path response calculation circuit that estimates the transmission path response at the current time only for the selected plurality of signal sequences, and the value of the transmission path response at the current time for the plurality of sequences obtained by the transmission path response calculation circuit. The legitimacy is checked, and if it is legitimate, the output of the channel response calculation circuit is determined, and if it is not legitimate, the channel response estimation value at the previous time for the same signal sequence is determined by the state transition diagram and the memory of the non-degenerate state. A transmission line response conversion circuit that outputs a value converted according to the rule as a transmission line response estimation value at the current time, and a transmission line response estimation value at the current time output by the transmission line response conversion circuit are stored and stored at the previous time. A transmission path response storage circuit that reversely supplies the transmission path response estimation value that is stored every moment to the transmission path response conversion circuit, the transmission path response estimation value at the current time output by the transmission path response conversion circuit, and each degenerate state. A branch metric calculation circuit that obtains a virtual received signal for each of the plurality of sequences based on the three of the non-degenerate state corresponding to and the transmission signal candidate at the current time, and obtains the distance from the sample value of the received signal. , The non-degenerate state corresponding to the oldest state of the maximum likelihood sequence is determined by the Viterbi algorithm by receiving the output of the branch metric calculation circuit while outputting the non-degenerate state corresponding to each degenerate state at each time. A Viterbi processor that outputs a determination value according to the state storage, a non-degenerate state storage circuit that stores the non-degenerate state, and a non-degenerate state that the non-degenerate state storage circuit provides And a state conversion circuit for designating the plurality of signal sequences for calculating the transmission path response to the transmission path response calculation circuit based on the converted state, and based on the degenerate state transition diagram. A sequence estimation device for estimating a transmission signal sequence.