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JP2560911B2 - Sequence estimation device - Google Patents

Sequence estimation device

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Publication number
JP2560911B2
JP2560911B2 JP2312035A JP31203590A JP2560911B2 JP 2560911 B2 JP2560911 B2 JP 2560911B2 JP 2312035 A JP2312035 A JP 2312035A JP 31203590 A JP31203590 A JP 31203590A JP 2560911 B2 JP2560911 B2 JP 2560911B2
Authority
JP
Japan
Prior art keywords
transmission line
response
circuit
transmission
sequence
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP2312035A
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Japanese (ja)
Other versions
JPH04183041A (en
Inventor
彰久 後川
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NEC Corp
Original Assignee
Nippon Electric Co Ltd
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Priority to JP2312035A priority Critical patent/JP2560911B2/en
Priority to US07/738,352 priority patent/US5272726A/en
Priority to CA002048210A priority patent/CA2048210C/en
Publication of JPH04183041A publication Critical patent/JPH04183041A/en
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Publication of JP2560911B2 publication Critical patent/JP2560911B2/en
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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、伝送路の特性の時間的な変動に追随して送
信信号系列の推定を行う系列推定装置に関する。
Description: TECHNICAL FIELD The present invention relates to a sequence estimation device that estimates a transmission signal sequence by following a temporal change in characteristics of a transmission path.

(従来の技術) 最尤系列推定装置(MLSE)は等化能力の最も優れた等
化方式として知られている(例えば、文献1:G.D.Forne
y,“Maximum Likelihood Sequence Estimation of Digi
tal Sequences in the presence of intersymbol inter
eference,"IEEE Transaction on Information Theory,v
ol.IT−18,no.3,May 1972)。最尤系列推定装置は一般
に単一の伝送路応答推定器を備えており、伝送路応答の
推定はこれを用いて既知の系列を受信する際に行う。
(Prior Art) A maximum likelihood sequence estimator (MLSE) is known as an equalization method with the best equalization capability (for example, Reference 1: GDForne.
y, “Maximum Likelihood Sequence Estimation of Digi
tal Sequences in the presence of intersymbol inter
eference, "IEEE Transaction on Information Theory, v
ol.IT-18, no.3, May 1972). The maximum likelihood sequence estimator generally comprises a single channel response estimator, and the channel response is estimated by using this when receiving a known channel.

また、伝送路の特性が時間的に変動する場合には、こ
の伝送路の特性の時間的な変動に追従させるような適応
最尤系列推定装置も提案されている(例えば、文献2:G.
Ungerboeck,“Adaptive Maximum Likelihood Receiver
for Carrier−Modulated Data Transmission Systems,"
IEEE Transaction on Communications,vol.COM−22,no.
5,May 1974)。適応最尤系列推定装置は、まず既知系列
を受信する際に伝送路応答を求め、それ以後情報データ
系列を受信するとき適応アルゴリズムなどを用いて伝送
路推定器を動作させ、伝送路応答を逐次更新していくこ
とで伝送路特性の時間的変動に追従していくことを特徴
としている。しかし、伝送路特性が高速変動にする場合
は、伝送路推定器の適応動作が追いつかなくなり、適応
最尤系列推定装置による良好な系列推定は困難である。
Further, when the characteristics of the transmission line fluctuate with time, an adaptive maximum likelihood sequence estimator that follows the temporal fluctuation of the characteristics of the transmission line has also been proposed (for example, Reference 2: G.
Ungerboeck, “Adaptive Maximum Likelihood Receiver
for Carrier-Modulated Data Transmission Systems, "
IEEE Transaction on Communications, vol.COM-22, no.
5, May 1974). The adaptive maximum likelihood sequence estimator first obtains a channel response when receiving a known sequence, and subsequently operates an channel estimator using an adaptive algorithm when receiving an information data sequence to sequentially transmit the channel response. It is characterized in that it updates to follow the temporal fluctuations of the transmission line characteristics. However, when the channel characteristics change rapidly, the adaptive operation of the channel estimator cannot catch up, and it is difficult for the adaptive maximum likelihood sequence estimator to perform good sequence estimation.

これに対して、特願平2−203436では高速に変動する
伝送路に対しても追従することが可能な新しい型の系列
推定装置を提案している。この装置は、送信信号系列の
みならず伝送路の特性も未知であるとして、系列毎に対
応する伝送路応答を推定してビタビアルゴリズムを適用
することを特徴とする。伝送路応答の推定は、送信信号
系列候補、伝送路応答、受信信号の三者で定まる伝送路
方程式を系列毎に解くことによって行っている。これは
伝送路応答の最適解を逐次求めることに相当するので、
特願平2−203436の系列推定装置は高速な伝送路変動に
対しても追従できる。
On the other hand, Japanese Patent Application No. 2-203436 proposes a new type sequence estimation device that can follow a transmission line that changes at high speed. This device is characterized in that the Viterbi algorithm is applied by estimating the corresponding transmission path response for each series, assuming that not only the transmission signal series but also the characteristics of the transmission path are unknown. The transmission path response is estimated by solving the transmission path equation determined by the transmission signal series candidate, the transmission path response, and the received signal for each series. This is equivalent to sequentially finding the optimum solution of the channel response, so
The sequence estimation device of Japanese Patent Application No. 2-203436 can follow high-speed transmission line fluctuations.

(発明が解決しようとする課題) しかしながら、特願平2−203436の系列推定装置で
は、送信信号系列候補のパターンによっては送信信号系
列候補、伝送路応答、受信信号の三者で定まる伝送路方
程式が本質的に解けず、伝送路応答が不定になる場合が
存在するという欠点がある。また、特願平2−203436の
系列推定装置は解を逐次得ているため、雑音などにより
伝送路応答推定値が時間毎に過度に敏感に変動し、系列
推定を誤るという欠点がある。
(Problems to be Solved by the Invention) However, in the sequence estimation device of Japanese Patent Application No. 2-203436, a transmission line equation determined by three of the transmission signal sequence candidate, the transmission line response, and the reception signal depending on the pattern of the transmission signal sequence candidate. However, there is a drawback that there is a case where the transmission line response becomes indefinite because it cannot be solved by nature. Further, since the sequence estimation device of Japanese Patent Application No. 2-203436 successively obtains the solution, it has a drawback that the channel estimation value fluctuates excessively sensitively due to noise or the like, resulting in erroneous sequence estimation.

そこで、本発明の目的は、伝送路推定を系列毎に安定
に行いながら、高速に変動する伝送路に追従することが
可能な系列推定装置を提供することにある。
Therefore, an object of the present invention is to provide a sequence estimation device capable of following a transmission line that changes at high speed while stably performing transmission line estimation for each sequence.

(課題を解決するための手段) 本発明に係る第1の系列推定装置は、受信信号のサン
プル値を複数個記憶するレジスタと、前記レジスタから
複数個の前記サンプル値を入力し複数の系列に対してそ
れぞれ現時刻の伝送路応答を直接解法により推定する伝
送路応答計算回路と、前記伝送路応答計算回路で求めた
複数の系列に対する前記伝送路応答の正当性を検査し、
正当である場合は現時刻の伝送路応答として前記伝送路
応答計算回路の出力を、正当でない場合は現時刻の伝送
路応答として前時刻の複数の伝送路応答から生き残り系
列の接続情報が指示する前時刻の伝送路応答を出力する
伝送路特性検査回路と、前記伝送路特性検査回路が出力
する伝送路応答を複数の系列に対してそれぞれ複数時刻
分記憶する伝送路特性記憶回路と、前記伝送路応答記憶
回路が記憶した前記現時刻の伝送路応答に基づいてそれ
ぞれの系列に対しての仮想受信信号点を求め前記受信信
号のサンプル値との距離を求めるブランチメトリック計
算回路と、前記ブランチメトリック計算回路の出力を受
けてビタビアルゴリズムにより受信信号を判定するとと
もに生き残り系列の接続情報を前記伝送路応答検査回路
に出力するビタビプロセッサと、から構成されることを
特徴とする。
(Means for Solving the Problem) A first sequence estimation apparatus according to the present invention includes a register that stores a plurality of sample values of a received signal, and a plurality of sample values that are input from the register to generate a plurality of sequences. On the other hand, the transmission line response calculation circuit for estimating the transmission line response at the current time by the direct solution method, and the validity of the transmission line response for the plurality of sequences obtained by the transmission line response calculation circuit are inspected,
If it is valid, the output of the transmission path response calculation circuit is designated as the current time transmission path response, and if it is not valid, the survival sequence connection information is instructed from the plurality of transmission path responses at the previous time as the current time transmission path response. A transmission line characteristic inspection circuit for outputting a transmission line response at a previous time; a transmission line characteristic storage circuit for storing the transmission line response output by the transmission line characteristic inspection circuit for a plurality of times respectively for a plurality of streams; A branch metric calculation circuit for obtaining a virtual reception signal point for each series based on the transmission path response at the current time stored by the path response storage circuit, and for obtaining a distance from the sample value of the reception signal; Viterbi that receives the output of the calculation circuit and determines the received signal by the Viterbi algorithm and outputs the connection information of the survival sequence to the transmission line response inspection circuit Wherein the processor, in that it is composed of.

また、本発明に係る第2の系列推定装置は、受信信号
のサンプル値を複数個記憶するレジスタと、前記レジス
タから複数個の前記サンプル値を入力し複数の系列に対
してそれぞれ現時刻の伝送路応答を直接解法により推定
する伝送路応答計算回路と、前記伝送路応答計算回路で
求めた複数の系列に対する前記伝送路応答の正当性を検
査し、正当である場合は現時刻の伝送路応答として前記
伝送路応答計算回路の出力を、正当でない場合は現時刻
の伝送路応答として前時刻の複数の伝送路応答から生き
残り系列の接続情報が指示する前時刻の伝送路応答を出
力する伝送路特性検査回路と、前記伝送路特性検査回路
が出力する伝送路応答を複数の系列に対してそれぞれ複
数時刻分記憶する伝送路特性記憶回路と、前記伝送路特
性記憶回路から供給されるそれぞれの系列に対する現在
と過去複数時刻分の前記伝送路応答からあらかじめ定め
る変換規則に従ってそれぞれ伝送路応答変換値を求める
伝送路応答変換回路と、前記伝送路応答変換回路が与え
る伝送路応答変換値に基づいてそれぞれの系列に対して
の仮想受信信号点を求め前記受信信号のサンプル値との
距離を求めるブランチメトリック計算回路と、前記ブラ
ンチメトリック計算回路の出力を受けてビタビアルゴリ
ズムにより受信信号を判定するとともに生き残り系列の
接続情報を前記伝送路応答検査回路に出力するビタビプ
ロセッサと、から構成されることを特徴とする。
A second sequence estimation device according to the present invention is a register for storing a plurality of sample values of a received signal, and a plurality of the sample values are input from the register to transmit a current time to each of a plurality of sequences. A channel response calculation circuit for estimating a channel response by a direct solution method, and the legitimacy of the channel response for a plurality of sequences obtained by the channel response calculation circuit is inspected. The output of the transmission line response calculation circuit is output as a transmission line response of the previous time indicated by the connection information of the surviving sequence from a plurality of transmission line responses of the previous time as the transmission line response of the current time if not valid. Supplied from a characteristic inspection circuit, a transmission path characteristic storage circuit that stores the transmission path response output from the transmission path characteristic inspection circuit for a plurality of times for a plurality of times, and the transmission path characteristic storage circuit And a transmission line response conversion value given by the transmission line response conversion circuit, which obtains a transmission line response conversion value according to a predetermined conversion rule from the transmission line responses for the present and past plural times for each sequence A branch metric calculation circuit that obtains a virtual reception signal point for each sequence based on the above and obtains a distance from the sample value of the reception signal, and a reception signal is determined by a Viterbi algorithm by receiving the output of the branch metric calculation circuit. And a Viterbi processor that outputs the connection information of the surviving sequence to the transmission line response inspection circuit.

(作用) 以下では、第4図に示すように主波に対して複数の遅
延波の応答が存在する伝送路を考える。伝送路インパル
ス応答をベクトルt T=(ht 0,ht 1,…,ht L)(上付き添
字Tは転置を意味する)、送信信号系列をベクトルt T
=(st,st-1,…,st-L)、観測過程の雑音を含めた送信
信号とは独立な加法性雑音をvtとする。このとき、時刻
tでの受信器入力rtは、式(1)で示されるようにベク
トルhtとベクトルとの畳み込みと雑音の和で与えら
れる。
(Operation) In the following, consider a transmission line in which responses of a plurality of delayed waves exist with respect to the main wave as shown in FIG. The transmission line impulse response is a vector t T = (h t 0 , h t 1 , ..., H t L ) (the superscript T means transposition), and the transmission signal sequence is a vector t T.
= (S t , s t-1 , ..., S tL ), and let v t be additive noise that is independent of the transmitted signal and includes noise in the observation process. In this case, the receiver input r t at time t, given by the sum of the convolution and noise between the vector h t and the vector t as shown in equation (1).

rtt T+vt (1) この様子を第5図に示す。以下、式(1)を時刻tで
の伝送路方程式と呼ぶ。
r t = t T · t + v t (1) This state is shown in FIG. Hereinafter, Expression (1) will be referred to as a transmission line equation at time t.

次に、時刻t−N+1(送信信号時間間隔を1とす
る)から時刻tまでのN個の受信信号から伝送路インパ
ルス応答ベクトルを最小二乗推定する方法を述べ
る。まず、そのために時刻t−N+1から時刻tまでN
個の送信信号系列ベクトルsτ(t−N+1≦τ≦t)
から次のように送信信号行列Stを定義する。
Next, a method of least-squares estimating the transmission path impulse response vector t from N received signals from time t−N + 1 (where the transmission signal time interval is 1) to time t will be described. First, for that purpose, from time t-N + 1 to time t, N
Transmission signal sequence vectors s τ (t−N + 1 ≦ τ ≦ t)
Then, the transmission signal matrix S t is defined as follows.

また、受信信号ベクトル、雑音ベクトルを以
下で定義する。t T =(rt,rt-1,…,rt-N+1) (3)t T =(vt,vt-1,…,vt-N+1) (4) 以上より、N時点にわたる伝送路方程式は式(5)で
書ける。 =St T (5) このとき、最小二乗推定による伝送路インパルス応答
ベクトルt,lsは、t,ls =(St T・St-1・St T (6) で得られる。(例えば、文献3:中溝「信号解析とシステ
ム同定」コロナ社、1988)。特に、インパルス応答推定
に用いる受信信号の数(N)が伝送路応答の数(L+
1)に等しいときは送信信号行列Stが正方行列となるの
で、受信信号に単に送信信号行列Stの逆行列をかけるこ
とで最小二乗推定による伝送路応答推定値が得られる。t,ls =St -1 (7) 第3図に示す特願平2−203436の系列推定装置は、全
ての送信信号行列St、すなわち取り得る送信信号の全て
の組み合せ(St、St-1、…、St-L-N+1)に対して、それ
ぞれ伝送路応答推定値ベクトルt,lsの解を求める。そ
して、現時刻から次の時刻への遷移に対して式(8)で
求める尤度(ブランチメトリック)計算においてそれぞ
れの伝送路応答推定値を用いる。
Further, the received signal vector t 1 and the noise vector t 1 are defined below. t T = (r t , r t-1 ,, ..., r t-N + 1 ) (3) t T = (v t , v t-1 ,, ..., v t-N + 1 ) (4) From the above , The transmission line equation over N time points can be written by the equation (5). t = S t T · t + t (5) At this time, the transmission line impulse response vector t, ls by the least-squares estimation is t, ls = (S t T · S t ) −1 · S t T · t ( Obtained in 6). (For example, Reference 3: Nakamizo "Signal Analysis and System Identification", Corona, 1988). In particular, the number of received signals (N) used for impulse response estimation is the number of transmission path responses (L +
When it is equal to 1), the transmission signal matrix S t becomes a square matrix, and therefore the transmission signal response estimation value by least square estimation is obtained by simply multiplying the reception signal by the inverse matrix of the transmission signal matrix S t . t, ls = S t −1 · t (7) The sequence estimation device of Japanese Patent Application No. 2-203436 shown in FIG. 3 has all transmission signal matrices S t , that is, all possible combinations of transmission signals (S t , S t-1 , ..., S tL-N + 1 ) , the solution of the channel response estimation value vector t, ls is obtained. Then, each transmission line response estimation value is used in the likelihood (branch metric) calculation obtained by Expression (8) for the transition from the current time to the next time.

|rt+1t+1 Tt,ls|2 (8) ただし、t+1 T=(St+1、St,…、St-L+1) そして、この値の全時刻に渡る和で定まる値(パスメ
トリック)を最小にする全時刻に渡る送信信号系列をビ
タビアルゴリズムにより求める。ここで、ビタビアルゴ
リズムを動作させるトレリス線図の状態は、送信信号行
列Stの成分に現れる送信信号の組み合せ(st,st-1,…,s
t-L-N+1)が定める。この意味で、以下では送信信号の
組み合せ(st,st-1,st-L-N+1)のことを単に状態と呼ぶ
ことにする。ビタビアルゴリズムによって求めた最尤状
態の全時刻に渡る連なりが送信信号系列推定値となる。
| r t + 1t + 1 T · t, ls | 2 (8) where t + 1 T = (S t + 1 , S t , ..., S t-L + 1 ) and all of this value The Viterbi algorithm is used to find the transmission signal sequence over all times that minimizes the value (path metric) determined by the sum over time. Here, the state of the trellis diagram for operating the Viterbi algorithm is the combination of the transmission signals appearing in the components of the transmission signal matrix S t (s t , s t−1 , ..., s
tL-N + 1 ). In this sense, the combination of transmission signals (s t , s t-1 , s tL-N + 1 ) will be simply referred to as a state hereinafter. The sequence of the maximum likelihood states obtained by the Viterbi algorithm over the entire time is the transmission signal sequence estimated value.

さて、この特願平2−203436の系列推定装置では、式
(6)あるいは式(7)で伝送路応答ベクトルt,ls
求める際にそれぞれ行列(St TSt-1、行列St -1を計算
している。そのため、行列St TStあるいは行列Stが特異
になる状態に対しては、そのままでは伝送路応答を求め
ることができない。伝送路応答が不定となるブランチメ
トリック計算が行えず、ビタビアルゴリズムを動作させ
ることができないという欠点がある。これに対して、一
般に伝送路変動は送信信号行列Stの成分に現れる信号の
時間間隔(L+N−1)において無視できるほど小さい
という性質がある。この性質を利用すれば、行列St TSt
あるいは行列Stが特異になる状態に対する伝送路応答推
定値ベクトルt,lsとして、該状態に遷移する生き残り
系列の前時刻状態での伝送路応答推定値ベクトルベクト
t−1,lsで代用することができる。すなわち、本発
明に係る第1の系列推定装置では、行列St TStあるいは
行列Stが特異となる状態に対しては生き残り系列が前時
刻でとった状態に関する伝送路応答推定値を利用し、行
列St TStあるいは行列Stが非特異となる状態に対しては
受信信号にそれぞれの行列の逆行列をかけて求めた伝送
路応答を利用するように設定する。これにより、ブラン
チメトリック計算回路に対して常に安定に伝送路応答推
定値を供給することができ、これを基に従来のビタビア
ルゴリズムを動作させれば、高速に変動する伝送路に安
定して追従することが可能な系列推定装置を実現でき
る。
By the way, in the sequence estimation device of this Japanese Patent Application No. 2-203436, the matrix (S t T S t ) -1 and the matrix S are obtained when the transmission path response vectors t and ls are obtained by the formula (6) or (7), respectively. You are calculating t -1 . Therefore, for the matrix S t T S t or the state where the matrix S t becomes singular, the transmission line response cannot be obtained as it is. There is a disadvantage that the branch metric calculation in which the transmission path response is indefinite cannot be performed and the Viterbi algorithm cannot be operated. In contrast, generally channel variations is the property that the smaller negligible in the time interval of the signal appearing on the components of the transmission signal matrix S t (L + N-1 ). Using this property, the matrix S t T S t
Alternatively, the channel response estimate vector t, ls for the state in which the matrix S t is singular is substituted by the channel response estimate vector vector t−1, ls in the previous time state of the surviving sequence transitioning to the state. You can That is, in the first sequence estimation device according to the present invention, the channel response estimation value regarding the state in which the surviving sequence was taken at the previous time is used for the state in which the matrix S t T S t or the matrix S t is singular. Then, for a state in which the matrix S t T S t or the matrix S t is nonsingular, it is set to use the channel response obtained by multiplying the received signal by the inverse matrix of each matrix. As a result, the channel response estimation value can always be stably supplied to the branch metric calculation circuit, and if the conventional Viterbi algorithm is operated based on this, it can stably follow the channel that fluctuates at high speed. It is possible to realize a sequence estimation device that can do this.

また、特願平2−203436の系列推定装置では、伝送路
応答推定値を毎時刻逐次求めるだけで、各時刻の推定値
間の相関を利用していない。そのため、雑音によりそれ
ぞれの状態に対する伝送路応答推定値が各時刻で大きく
変化し、系列推定を誤ることがある。しかるに、雑音を
無視すれば、本来伝送路応答はドップラー周波数に従っ
て連続的に変化するという性質がある。すなわち、時変
とはいえ、伝送路応答の変化はシンボル伝送間隔に比べ
一般に穏やかで、各時刻の伝送路応答の間には高い相関
がある。そこで、本発明に係る第2の系列推定装置で
は、伝送路応答間の高い相関を利用するような変換操作
を新たに導入する。すなわち、それぞれの状態に対し
て、過去の時点での伝送路応答推定値と伝送路方程式を
解いて求めた現時点の推定値とからこの変換操作により
新たな現時点の推定値を得るようにする。これにより、
伝送路応答推定値が各時刻で大きく変化する現象を防止
でき、真の状態に対して安定して確からしい伝送路応答
推定値を求めることができるようになる。また、伝送路
応答推定値を平滑化することにより伝送路推定過程にお
ける雑音を効果的に取り除くことができる。その結果、
高速に変動する伝送路に安定して追従することが可能な
系列推定装置が実現できる。
Further, the sequence estimation device of Japanese Patent Application No. 2-203436 only sequentially obtains the channel response estimated value at each time, and does not use the correlation between the estimated values at each time. Therefore, the channel response estimation value for each state may change significantly at each time due to noise, and the sequence estimation may be erroneous. However, if noise is ignored, the transmission line response originally has the property of continuously changing according to the Doppler frequency. That is, although it is time-varying, the change in the transmission path response is generally gentler than the symbol transmission interval, and there is a high correlation between the transmission path responses at each time. Therefore, the second sequence estimation apparatus according to the present invention newly introduces a conversion operation that utilizes a high correlation between channel responses. That is, for each state, a new estimated value at the current time is obtained by this conversion operation from the estimated value of the transmission path response at the past time and the estimated value at the current time obtained by solving the transmission path equation. This allows
It is possible to prevent the phenomenon that the estimated value of the channel response greatly changes at each time, and to obtain the estimated value of the channel response that is stable and reliable in the true state. Further, by smoothing the channel response estimation value, noise in the channel estimation process can be effectively removed. as a result,
A sequence estimation device capable of stably following a transmission line that changes at high speed can be realized.

(実施例) 次に、図面を参照して本発明を説明する。(Example) Next, this invention is demonstrated with reference to drawings.

第1図に本発明に係る第1の系列推定装置の一実施例
を示す。入力端子101に供給された時刻tでの受信器入
力rtは、レジスタ102に記憶されるとともにブランチメ
トリック計算回路106に送られる。レジスタ102に記憶さ
れた時刻t−N+1から時刻tまでN個の受信信号は伝
送路応答計算回路103に入力される。伝送路応答計算回
路103は、式(6)ないし式(7)にしたがって各状態
に対してベクトルt,lsを計算し、伝送路応答検査回路
104に出力する。式(6)ないし式(7)における伝送
路応答計算では、行列(St TSt-1、行列St -1はともに
送信信号のみで決まるので、全ての状態、すなわち
(st,st-1,…,st-L-N+1)の取り得る全ての送信信号の
組み合せに対してあらかじめ計算し、その結果を記憶し
ておいてもよい。行列St TStあるいは行列Stが特異とな
る送信信号の組み合せに対しては、伝送路応答計算回路
103はあらかじめ定めた値(例えば0)を出力し、ベク
トルt,lsが不定である旨を伝送路応答検査回路104に
伝える。ここでは、各状態に対して不定でない場合に得
られる伝送路応答推定値を正当な推定値と呼ぶ。伝送路
応答検査回路104は、全ての状態に対してそれぞれベク
トルt,lsが不定であるか否かを検査し、不定でないと
きはそのベクトルt,lsの値をそのまま伝送路応答記憶
回路105に出力する。不定であるときは、まずその状態
に接続する生き残りパスが前時刻でとった状態をビタビ
プロセッサ107から供給される生き残り系列の接続情報
から調べる。次に前時刻でとった状態に対応する前時刻
の伝送路応答推定値ベクトルt−1,lsを伝送路応答記
憶回路105から読み出し、その値を現時刻の伝送路応答
推定ベクトルt,lsとし、再び伝送路記憶回路105に出
力する。したがって、伝送路記憶回路105には全ての状
態に対して常に正当な伝送路応答推定値が記憶させる。
伝送路記憶回路105はこれらの伝送路応答推定値をブラ
ンチメトリック計算回路106に出力する。ブランチメト
リック計算回路106は、この伝送路応答推定値を基に取
り得る全ての状態に対して式(8)で定まるブランチメ
トリックを個別に計算する。ブランチメトリック計算回
路106は個々の状態に対して計算して得られたブランチ
メトリックをビタビプロセッサ107に出力する。ビタビ
プロセッサ107は、式(8)のメトリックの全ての時刻
の和が最小となる系列のある特定時刻の送信信号推定値
を出力端子108に出力する。ビタビプロセッサ107の動作
は文献1、2、または特願平2−203436の系列推定装置
と同様であるので、詳細は省略する。
FIG. 1 shows an embodiment of the first sequence estimation apparatus according to the present invention. Receiver input r t in the supplied time t to an input terminal 101 is sent to the branch metric calculating circuit 106 while being stored in the register 102. From time t−N + 1 to time t, the N received signals stored in the register 102 are input to the transmission path response calculation circuit 103. The transmission line response calculation circuit 103 calculates the vector t, ls for each state according to the equations (6) to (7), and the transmission line response inspection circuit
Output to 104. In the channel response calculation in the equations (6) to (7), since the matrix (S t T S t ) -1 and the matrix S t -1 are both determined only by the transmission signal, all states, that is, (s t , s t-1, ..., previously calculated for the combination of s tL-N + 1) all transmission signals may take the may be stored the results. For the matrix S t T S t or the combination of transmitted signals with which the matrix S t is singular, the transmission line response calculation circuit
103 outputs a predetermined value (for example, 0) and informs the transmission path response inspection circuit 104 that the vectors t and ls are indefinite. Here, the transmission line response estimation value obtained when the state is not indefinite is called a valid estimation value. The transmission line response inspection circuit 104 inspects whether or not the vectors t and ls are indefinite for all states, and when they are not indefinite, the values of the vectors t and ls are directly stored in the transmission line response storage circuit 105. Output. If it is indefinite, first, the state taken by the survivor path connecting to that state at the previous time is checked from the surviving sequence connection information supplied from the Viterbi processor 107. Next, the transmission line response estimation value vector t−1, ls at the previous time corresponding to the state taken at the previous time is read from the transmission line response storage circuit 105, and the value is set as the transmission line response estimation vector t, ls at the current time. , To the transmission path storage circuit 105 again. Therefore, the transmission path storage circuit 105 always stores valid transmission path response estimated values for all states.
The transmission path storage circuit 105 outputs these transmission path response estimated values to the branch metric calculation circuit 106. The branch metric calculation circuit 106 individually calculates the branch metric determined by the equation (8) for all possible states based on the transmission path response estimated value. The branch metric calculation circuit 106 outputs the branch metric obtained by calculation for each state to the Viterbi processor 107. The Viterbi processor 107 outputs, to the output terminal 108, the transmission signal estimation value at a certain specific time in the sequence in which the sum of all the times of the metric of the equation (8) is the smallest. The operation of the Viterbi processor 107 is similar to that of the sequence estimation device of Documents 1 and 2 or Japanese Patent Application No. 2-203436, and thus the details will be omitted.

第2図に本発明に係る第2の系列推定装置の一実施例
を示す。第1図の系列推定装置の伝送路応答記憶回路10
5(第2図では伝送路記憶回路205に相当)とブランチメ
トリック計算回路106(第2図ではブランチメトリック
計算回路207に相当)との間に、伝送路応答変換回路206
を挿入した構成になっている。伝送路応答変換回路206
は、伝送路応答検査回路204と同様にビタビプロセッサ2
08から生き残り系列の接続情報を供給されるとともに、
伝送路記憶回路205から現時刻の伝送路応答推進値ベク
トルt,lsだけでなく、過去の時刻に対する伝送路応答
推定値ベクトルt−1,ls、ベクトルt−2,ls,…の
供給を受ける。そして、伝送路応答変換回路206は、生
き残り系列の接続情報に基づいて現時刻の全ての状態に
対して現時刻の該状態に対する伝送路応答推定値ベクト
t,lsと、該状態に遷移する生き残りパスに関する過
去の複数時刻に対する伝送路応答推定値ベクトル
t−1,ls、ベクトルt−2,ls…とからあらかじめ定め
た変換操作により、新たな現時刻の該状態に対する伝送
路応答推定値ベクトルを求める。例えば、現時刻と
過去2時刻の伝送路応答推定値から新たな現時刻の推定
値を単純平均により求める場合、 1)該状態の現時刻の伝送路応答推定値ベクトルt,ls
を伝送路応答記憶回路205より得る、 2)該状態に遷移する生き残りパスが1時刻前、2時刻
前に通った状態をビタビプロセッサ208から供給された
生き残り系列の接続情報から調べる、 3)2)で調べた1時刻前、2時刻前の状態に対する過
去のその時刻の伝送路応答推定値ベクトルt−1,ls
ベクトルt−2,lsを伝送路応答記憶回路205より得
る、 4)新たな現時刻の該状態に対する伝送路応答推定値ベ
クトル =(t,lst−1,lst−2,ls)/3 (9) により求める、 というようにすればよい。この変換操作により伝送路応
答推定値は平滑化され、伝送路推定過程における雑音は
効果的に取り除かれる。また、変換操作により伝送路応
答推定値には過去の推定値と高い相関を持つような慣性
が付与され、ブランチメトリック計算回路で利用する伝
送路応答に連続性が存在するようになる。すなわち、伝
送路応答推定値が各時刻で大きく変化する現象を防止で
き、真の状態に対して安定して確からしい伝送路応答推
定値を求めることができるようになる。本実施例では、
伝送路応答変換回路206における変換操作として単純平
均を用いたが、加重平均などの他の線形操作、しきい値
を設けて複数の伝送路応答推定値を選択的に用いて平均
をとるなど他の非線形な統計操作を施してもよい。
FIG. 2 shows an embodiment of the second sequence estimation apparatus according to the present invention. Transmission line response storage circuit 10 of the sequence estimation device of FIG.
5 (corresponding to the transmission path storage circuit 205 in FIG. 2) and the branch metric calculation circuit 106 (corresponding to the branch metric calculation circuit 207 in FIG. 2), the transmission path response conversion circuit 206
Has been inserted. Transmission line response conversion circuit 206
Is the Viterbi processor 2 similarly to the transmission line response inspection circuit 204.
While the connection information of the surviving series is supplied from 08,
From the transmission path memory circuit 205, not only the transmission path response driving value vector t, ls at the present time but also the transmission path response estimation value vector t−1, ls , vector t−2, ls , ... . Then, the transmission path response conversion circuit 206, based on the connection information of the survival series, the transmission path response estimation value vector t, ls for the current state for all states at the current time, and the surviving transition to the state. Vectors of estimated channel response values for past multiple times regarding the path
A transmission path response estimated value vector t for the state at the new current time is obtained by a predetermined conversion operation from t−1, ls and vectors t−2, ls . For example, in the case of obtaining a new estimated value of the current time from the estimated values of the channel response at the current time and the past two times by simple averaging, 1) The estimated channel response value vector t, ls at the current time of the state
From the transmission path response storage circuit 205, 2) check the state of the surviving path transiting to the state one hour before, two hours before, from the surviving sequence connection information supplied from the Viterbi processor 208, 3) 2 ), The transmission line response estimation value vector t−1, ls at that time in the past with respect to the state of one hour before and two hours before,
The vector t-2, ls is obtained from the transmission line response storage circuit 205. 4) The transmission line response estimation value vector t for the state at the new current time is t = ( t, ls + t-1, ls + t-2 , ls ) / 3 (9), and so on. By this conversion operation, the channel response estimation value is smoothed, and noise in the channel estimation process is effectively removed. In addition, the conversion operation gives the transmission path response estimated value an inertia having a high correlation with the past estimated value, so that the transmission path response used in the branch metric calculation circuit has continuity. That is, it is possible to prevent the phenomenon that the estimated value of the transmission line response greatly changes at each time, and it is possible to obtain the estimated value of the transmission line response that is stable and reliable in the true state. In this embodiment,
Although the simple averaging is used as the conversion operation in the transmission path response conversion circuit 206, other linear operations such as weighted averaging, a threshold is provided, and a plurality of transmission path response estimation values are selectively used to take an average. Non-linear statistical manipulation of may be performed.

以上の実施例では、伝送路応答検査回路104または204
は伝送路応答推定値の不定か否かのみを検査したが、不
定の場合に加え、ブランチメトリック計算回路106また
は207にとって好ましくない伝送路応答が伝送路応答計
算回路103から供給される場合も選択的に不定の場合と
同じく正当な推定値ではないとして処理し、前時刻の伝
送路応答推定値を代替値とする操作を行ってもよい。さ
らに、以上の実施例では、主波に対して複数の遅延波が
存在する伝送路をもとに説明を行ったが、主波に対して
複数の先行波の応答が存在するような伝送路、先行波と
遅延波が混在するような伝送路に対しても本発明の系列
推定装置が有効であることは明らかである。
In the above embodiment, the transmission line response inspection circuit 104 or 204
Checked only whether or not the transmission path response estimation value is indefinite, but in addition to the case where it is indefinite, it is also selected when a transmission path response unfavorable to the branch metric calculation circuit 106 or 207 is supplied from the transmission path response calculation circuit 103. The processing may be performed assuming that the estimated value is not a valid estimated value as in the case of uncertainties, and the transmission path response estimated value at the previous time may be used as an alternative value. Further, in the above embodiments, the description has been given based on the transmission line in which a plurality of delayed waves exist with respect to the main wave, but the transmission line in which there are responses of a plurality of preceding waves to the main wave. Obviously, the sequence estimation device of the present invention is effective even for a transmission line in which a preceding wave and a delayed wave are mixed.

(発明の効果) 以上に詳しく述べたように、本発明に係る系列推定装
置は、雑音がある場合にも系列毎の伝送路推定を常に安
定に行い、高速に変動する伝送路に追従することができ
る。
(Effects of the Invention) As described in detail above, the sequence estimation apparatus according to the present invention can always perform stable channel estimation for each sequence even in the presence of noise and follow a channel that changes at high speed. You can

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る第1の系列推定装置の一実施例を
示すブロック図、第2図は本発明に係る第2の系列推定
装置の一実施例を示すブロック図、第3図は従来の系列
推定装置を示すブロック図、第4図は伝送路応答を説明
するための図、第5図は伝送路モデルを説明するための
図である。 101,201,301,501……入力端子、102,202,302……レジス
タ、103,203 303……伝送路応答計算回路、104,204……
伝送路応答検査回路、105,205……伝送路応答記憶回
路、206……伝送路応答変換回路、106,207,304……ブラ
ンチメトリック計算回路、107,208,305……ビタビプロ
セッサ、108,209,305,506……出力端子、401……主波応
答、402……遅延波応答、502……遅延素子、503……乗
算器、504,505……加算器。
FIG. 1 is a block diagram showing an embodiment of a first sequence estimation device according to the present invention, FIG. 2 is a block diagram showing an embodiment of a second sequence estimation device according to the present invention, and FIG. FIG. 4 is a block diagram showing a conventional sequence estimation device, FIG. 4 is a diagram for explaining a transmission line response, and FIG. 5 is a diagram for explaining a transmission line model. 101,201,301,501 ...... Input terminal, 102,202,302 ...... Register, 103,203 303 ...... Transmission line response calculation circuit, 104,204 ......
Transmission line response inspection circuit, 105,205 ... Transmission line response storage circuit, 206 ... Transmission line response conversion circuit, 106,207,304 ... Branch metric calculation circuit, 107,208,305 ... Viterbi processor, 108,209,305,506 ... Output terminal, 401 ... Main wave response , 402 ... delayed wave response, 502 ... delay element, 503 ... multiplier, 504, 505 ... adder.

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】受信信号のサンプル値を複数個記憶するレ
ジスタと、前記レジスタから複数個の前記サンプル値を
入力し複数の系列に対してそれぞれ現時刻の伝送路応答
を直接解法により推定する伝送路応答計算回路と、前記
伝送路応答計算回路で求めた複数の系列に対する前記伝
送路応答の正当性を検査し、正当である場合は現時刻の
伝送路応答として前記伝送路応答計算回路の出力を、正
当でない場合は現時刻の伝送路応答として前時刻の複数
の伝送路応答から生き残り系列の接続情報が指示する前
時刻の伝送路応答を出力する伝送路特性検査回路と、前
記伝送路特性検査回路が出力する伝送路応答を複数の系
列に対してそれぞれ複数時刻分記憶する伝送路特性記憶
回路と、前記伝送路応答記憶回路が記憶した前記現時刻
の伝送路応答に基づいてそれぞれの系列に対しての仮想
受信信号点を求め前記受信信号のサンプル値との距離を
求めるブランチメトリック計算回路と、前記ブランチメ
トリック計算回路の出力を受けてビタビアルゴリズムに
より受信信号を判定するとともに生き残り系列の接続情
報を前記伝送路応答検査回路に出力するビタビプロセッ
サと、から構成されることを特徴とする系列推定装置。
1. A register for storing a plurality of sample values of a received signal, and a transmission for inputting a plurality of the sample values from the register and estimating a channel response at a current time for each of a plurality of sequences by a direct solution method. Path response calculation circuit, and checks the legitimacy of the channel response for a plurality of sequences obtained by the channel response calculation circuit, and outputs the channel response calculation circuit as the current time channel response if the channel response is correct. If not valid, a transmission line characteristic inspection circuit that outputs the transmission line response at the previous time indicated by the connection information of the survival sequence from the plurality of transmission line responses at the previous time as the transmission line response at the current time, and the transmission line characteristic A transmission line characteristic storage circuit that stores the transmission line response output by the inspection circuit for a plurality of times respectively for a plurality of series, and a transmission line response storage circuit that stores the transmission line response at the current time stored in the transmission line response storage circuit. And a branch metric calculation circuit that obtains a virtual received signal point for each sequence and obtains a distance from the sample value of the received signal, and a received signal is determined by a Viterbi algorithm by receiving the output of the branch metric calculation circuit. A sequence estimation device, comprising: a Viterbi processor that outputs connection information of a survival sequence to the transmission line response inspection circuit.
【請求項2】受信信号のサンプル値を複数個記憶するレ
ジスタと、前記レジスタから複数個の前記サンプル値を
入力し複数の系列に対してそれぞれ現時刻の伝送路応答
を直接解法により推定する伝送路応答計算回路と、前記
伝送路応答計算回路で求めた複数の系列に対する前記伝
送路応答の正当性を検査し、正当である場合は現時刻の
伝送路応答として前記伝送路応答計算回路の出力を、正
当でない場合は現時刻の伝送路応答として前時刻の複数
の伝送路応答から生き残り系列の接続情報が指示する前
時刻の伝送路応答を出力する伝送路特性検査回路と、前
記伝送路特性検査回路が出力する伝送路応答を複数の系
列に対してそれぞれ複数時刻分記憶する伝送路特性記憶
回路と、前記伝送路特性記憶回路から供給されるそれぞ
れの系列に対する現在と過去複数時刻分の前記伝送路応
答からあらかじめ定める変換規則に従ってそれぞれ伝送
路応答変換値を求める伝送路応答変換回路と、前記伝送
路応答変換回路が与える伝送路応答変換値に基づいてそ
れぞれの系列に対しての仮想受信信号点を求め前記受信
信号のサンプル値との距離を求めるブランチメトリック
計算回路と、前記ブランチメトリック計算回路の出力を
受けてビタビアルゴリズムにより受信信号を判定すると
ともに生き残り系列の接続情報を前記伝送路応答検査回
路に出力するビタビプロセッサと、から構成されること
を特徴とする系列推定装置。
2. A register for storing a plurality of sample values of a received signal, and a transmission for inputting a plurality of the sample values from the register and estimating a channel response at a current time for each of a plurality of sequences by a direct solution method. Path response calculation circuit, and checks the legitimacy of the channel response for a plurality of sequences obtained by the channel response calculation circuit, and outputs the channel response calculation circuit as the current time channel response if the channel response is correct. If not valid, a transmission line characteristic inspection circuit that outputs the transmission line response at the previous time indicated by the connection information of the survival sequence from the plurality of transmission line responses at the previous time as the transmission line response at the current time, and the transmission line characteristic A transmission path characteristic storage circuit that stores transmission path responses output by the inspection circuit for a plurality of times respectively for a plurality of series, and for each series supplied from the transmission path characteristic storage circuit. A transmission line response conversion circuit that obtains a transmission line response conversion value from the transmission line responses for the current and past plural times according to a predetermined conversion rule, and a transmission line response conversion value given by the transmission line response conversion circuit. A branch metric calculation circuit that obtains a virtual received signal point for the sequence and obtains a distance from the sample value of the received signal, and a received signal is determined by a Viterbi algorithm by receiving the output of the branch metric calculation circuit and the survival sequence A sequence estimation device comprising a Viterbi processor that outputs connection information to the transmission path response inspection circuit.
JP2312035A 1990-07-31 1990-11-16 Sequence estimation device Expired - Lifetime JP2560911B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2312035A JP2560911B2 (en) 1990-11-16 1990-11-16 Sequence estimation device
US07/738,352 US5272726A (en) 1990-07-31 1991-07-31 Blind type sequence estimator for use in communications system
CA002048210A CA2048210C (en) 1990-07-31 1991-07-31 Blind type sequence estimator for use in communications system

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JP2795935B2 (en) * 1989-11-24 1998-09-10 三菱電機株式会社 Maximum likelihood sequence estimator
JPH03195129A (en) * 1989-12-22 1991-08-26 Mitsubishi Electric Corp Maximum likelihood series estimating device

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