JPH0728744A - Direct memory access controller - Google Patents

Abstract

PURPOSE:To improve the fast processing performance and the economical properties of DMA transfer. CONSTITUTION:A DMA controller consists of a transferer circuit 19 which outputs data, a transfer circuit 20 which inputs data, a dynamic RAM 18 which stores data, a DMA circuit 12 which writes the data received from the circuit 19 into the RAM 18 and also read the data out of the RAM 18 to send them to the circuit 20, a DMA transfer bus 15 which transfers data at a high speed, a CPU 11 which transfers data via a CPU operation bus 14 and also controls the DMA access operation via the bus 15 and an arbitrating circuit 13 which divides by time the bus 15 into plural time slots when the data are transferred at a high speed via the bus 15, operates the corresponding circuit in each time slot, and also prepares for operation of the circuit to operate in the next time slot.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a direct memory
The present invention relates to a direct memory access control device that controls an access transfer bus to control high-speed data transfer.

[0002]

2. Description of the Related Art Conventionally, what is shown in FIG. 8 is known as a device for performing a DMA transfer operation using a direct memory access (hereinafter referred to as DMA) circuit.

This is a microprocessor (hereinafter, CPU)
Called. ) 1 is connected to the memory 3 and the peripheral LSI 4 via the CPU operation bus 2, and the DMA circuit 5 is connected to the dynamic memory 7 and the transfer source circuit 8 via the DMA transfer bus 6.
And the transfer destination circuit 9 are connected, and the DMA control CPU 10 is connected between the CPU 1 and the DMA transfer bus 6.
It is known that the U operation bus 2 and the DMA transfer bus 6 are separated.

In this apparatus, the CPU 1 is always CP
Data processing is performed using the U operation bus 2.

The DMA transfer is performed by the DMA control CPU 1
0 and the DMA circuit 5 exchange signals BUSREQ and BUSACK, the DMA circuit 5 controls the dynamic memory 7, the transfer source circuit 8 and the transfer destination circuit 9, and the DMA transfer bus 6
To perform a DMA transfer.

Further, when the DMA control for controlling the DMA circuit 5 by the CPU 1 occurs, the CPU 1 for DMA control
0 controls the DMA circuit 5 using the DMA transfer bus 6 during the period when the DMA circuit 5 is not performing the DMA transfer.

[0007]

In this device, the CPU 1 operates on the CPU operating bus 2 even during the DMA transfer control.
Although there is an effect that high-speed processing can be realized because data processing can be performed by using, the CPU 10 for DMA control is used separately from the main CPU 1, and this CPU 10
Since it is necessary to incorporate new software for controlling DMA transfer, the entire apparatus becomes expensive and the economy is poor.

Therefore, the present invention provides a direct memory access control device capable of realizing higher speed processing of DMA transfer and improving economical efficiency.

[0009]

The invention according to claim 1 is
A transfer source circuit that outputs a data output request signal and outputs data, a transfer destination circuit that outputs a data input request signal and inputs data, a memory that stores data, and access control and transfer of this memory A direct memory access circuit that controls the writing of data from the original circuit to the memory and reading of the memory data to the transfer destination circuit, and a direct memory access circuit that connects these circuits and transfers the data at high speed
Data is transferred using the memory access transfer bus and microprocessor operation bus, and direct
Uses the direct memory access transfer bus by interposing between the microprocessor that controls direct memory access operations using the memory access transfer bus and the direct memory access transfer bus and the microprocessor operation bus During high-speed data transfer, the direct memory access transfer bus is time-divided into multiple time slots, and the operation of the corresponding circuit is performed in each time slot and the operation of the circuit that should operate in the next time slot. It is provided with an arbitration circuit for making preparations.

[0010]

In the invention having such a structure, when the microprocessor accesses the direct memory access transfer bus, the arbitration circuit activates the direct memory access circuit. As a result, the direct memory access circuit controls access to the memory, writes the data from the transfer source circuit to the memory using the direct memory access transfer bus, and writes the data in the memory to the direct memory access transfer bus. Is used to control reading to the transfer destination circuit. At this time, the arbitration circuit time-divides the direct memory access transfer bus into a plurality of time slots and, for example, operates the direct memory access circuit in a certain time slot and prepares the transfer source circuit for operation. In the next time slot, the transfer source circuit is operated and the transfer destination circuit is prepared for operation.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

A CPU 11, a DMA circuit 12 and an arbitration circuit 13 are provided as shown in FIG.
The operation bus 14 is connected, and the DMA transfer bus 15 is connected to the DMA circuit 12.

The arbitration circuit 13 is connected to both the CPU operation bus 14 and the DMA transfer bus 15.

A memory 16 and a peripheral LSI 17 are connected to the CPU 11 via a CPU operation bus 14, and the DM
A dynamic RAM 18, a transfer source circuit 19, and a transfer destination circuit 20 are connected to the A circuit 12 via a DMA transfer bus 15.

As shown in FIG. 2, the arbitration circuit 13 includes an address decoder 21, buffers 22, 23, 24 and a CP.
U access detection circuit 25, clock generator 26, counter 27, refresh request detection circuit 28, refresh circuit 29, pair of DRQ detection circuits 30, 31 and DRA
An M control conversion circuit 32 is provided to connect the address bus from the CPU 11 to the address decoder 21 and the buffer 22.
, And the data bus to the buffer 23. Further, the control signals MRD, MWR, I from the CPU 11 are
ORD and IOWR are input to the buffer 22.

The clock from the clock generator 26 is supplied to a counter 27, and the counter 27 controls the control signal MO.
The EN / M1CHK, M1EN / M2CHK, M2EN / M3CHK, and M3EN / M0CHK are generated and output, and at the same time, a control signal REFCLK having a constant cycle for refresh is generated to generate the refresh request detection circuit 28.
Is output to.

The address decoder 21 includes circuits 12,
A chip select signal for selectively operating 19, 20, 32 is created and output to the buffer 24 and a signal WAIT is output to the CPU 11. This signal WAIT
Is also output to the CPU access detection circuit 25.

The buffers 22, 23 and 24 fetch the stored signals and data according to the control signal MOEN from the counter 27. The CPU access detection circuit 25 detects the signal WAIT from the address decoder 21 according to the control signal M0CHK from the counter 27, and waits for a certain period of time to wait for the signal WAIT.
CLR is output to the address decoder 21 to output to the CPU 11
Is notified that the DMA bus access is completed.

The control signal M1CHK from the counter 27 is supplied to the DRQ detection circuit 30 and the control signal M2C is supplied.
HK is supplied to the DRQ detection circuit 31. DR
The Q detection circuit 30 detects the data output request signal DRQOUT from the transfer source circuit 19 by inputting the control signal M1CHK,
If detected, the DMA circuit 12 is executed before the M1CHK sequence is completed.
To the DMA circuit 12 before the end of the M2CHK sequence when the data input request signal DRQIN from the transfer destination circuit 20 is detected by the control signal M2CHK. Is being supplied.

When the DMA circuit 12 detects the signal DRQ0, it outputs a signal BREQ and requests the use of the DMA transfer bus 15. This signal DRQ0 is directly input to the DMA circuit 12 as the signal BACK, so that the DMA circuit 12 immediately receives the DMA signal.
The right to use the transfer bus 15 is obtained.

The DMA circuit 12 has a dynamic RA.
The address of M18, signals IRD, MWR, and ACK0 are output, and DMA transfer is performed from the transfer source circuit 19 to the RAM 18.

When the signal RD is input, the transfer source circuit 19 outputs data to the DMA transfer bus 15 and ends the output of the signal DRQOUT.

When the DMA circuit 12 detects the signal DRQ1, it outputs a signal BREQ and requests the use of the DMA transfer bus 15. This signal DRQ0 is directly input to the DMA circuit 12 as the signal BACK, so that the DMA circuit 12 immediately receives the DMA signal.
The right to use the transfer bus 15 is obtained.

The DMA circuit 12 has a dynamic RA.
The address of M18, signals MRD, IWR, and ACK1 are output, and DMA transfer is performed from the RAM 18 to the transfer destination circuit 20.

When the signal WR is input, the transfer destination circuit 20 takes in the data of the DMA transfer bus 15 and ends the output of the signal DRQIN.

The refresh request detection circuit 28 detects the control signal REFCLK from the counter 27, and outputs the control signal REFREQ to the refresh circuit 29 when the signal is detected at the timing of the control signal M3CHK from the counter 27.

The refresh circuit 29 controls the control signal REFR.
When the EQ is detected at the timing of the control signal M3EN from the counter 27, a refresh address or the like is output to the DMA transfer bus 15 to refresh the dynamic RAM 18 via the DRAM control conversion circuit 32. When the refresh is completed, the signal REFREQCLR is output to clear the refresh request detection circuit 28.

In the embodiment having such a structure, the control signals MOEN / M1CHK, M1EN / M2CHK and M2EN / M are supplied from the counter 27.
When 3CHK and M3EN / M0CHK are output at the timings shown in FIG. 3, the transfer source circuit that prepares the DMA bus access by the CPU 11 and the next time-slock operation in the period in which the control signal MOEN / M1CHK is output, that is, in the time slots T1 and T5 The DMA transfer request from 19 is detected.

In the period in which the control signals M1EN / M2CHK are output, that is, in the time slots T2 and T6, the DMA transfer operation of the data from the transfer source circuit 19 and the DMA from the transfer destination circuit 20 which is the next time lock operation preparation are performed. Detects transfer request.

In the period when the control signals M2EN / M3CHK are output, that is, in the time slot T3, the refresh request detection circuit 28 for the DMA transfer operation of the data to the transfer destination circuit 20 and the next time lock operation prepares the refresh request. Detect.

Further, during the period when the control signal M3EN / M0CHK is output, that is, in the time slot T4, the refresh operation of the dynamic RAM 18 by the refresh circuit 29 and the DMA bus access of the CPU 11 by the CPU access detection circuit 25 for the preparation for the operation of the next time lock are performed. Detect.

That is, when the CPU 11 outputs an address for DMA bus access, the address decoder 21 outputs a chip select signal and a signal WAIT for each circuit. Then, the signal WAIT causes the CPU 11 to enter the standby state while outputting the address, the control signals MRD, MWR, IORD, IOWR and the like. When the control signal M0CHK is input to the CPU access detection circuit 25, the CPU access detection circuit 25 detects the signal WAIT.

When the control signal M0EN is input to each of the buffers 22, 23 and 24 in the next time slot, the buffer 22 outputs the control signals MRD, MWR, IORD and IOWR, and the buffer 2
3 outputs data, and the buffer 24 outputs a chip select signal.

Thus, the DMA circuit 1 by the CPU 11
2. The transfer source circuit 19, the transfer destination circuit 20, and the dynamic RAM 18 can be accessed, and the DMA bus access is executed.

Further, the CPU access detection circuit 25 outputs a signal
WAIT is detected and WAITCLR is output after a certain period of time
Notify U11 that the DMA bus access is complete. That is, the address decoder 21 is activated by the signal WAITCLR.
The CPU 11 confirms that the DMA bus access has ended and the output of the address, each control signal and the like ends. Thus, the DMA bus access by the CPU 11 is completed.

The timing chart of the above control is shown in FIG.

The control signal M1CHK is generated at the timing when the data output request signal DRQOUT is output from the transfer source circuit 19.
Is input to the DRQ detection circuit 30, the DRQ detection circuit 3
0 detects the signal DRQOUT and outputs the signal DRQ0 to the DMA circuit 12. As a result, the DMA circuit 12 outputs the signal BREQ and immediately inputs it as the signal BACK to obtain the right to use the DMA transfer bus 15. In this way, the DMA circuit 12 outputs the address of the dynamic RAM 18, the signals IRD, MWR, and ACK0 to perform high-speed data transfer from the transfer source circuit 19 to the RAM 18.

The timing chart of the above control is shown in FIG.

The control signal M2CHK is output at the timing when the data input request signal DRQIN is output from the transfer destination circuit 20.
Is input to the DRQ detection circuit 31, the DRQ detection circuit 3
1 detects the signal DRQIN and outputs the signal DRQ1 to the DMA circuit 12. As a result, the DMA circuit 12 outputs the signal BREQ and immediately inputs it as the signal BACK to obtain the right to use the DMA transfer bus 15. In this way, the DMA circuit 12 outputs the address of the dynamic RAM 18, the signals MRD, IWR, and ACK1 to perform high-speed data transfer from the RAM 18 to the transfer destination circuit 20.

FIG. 6 is a timing chart showing the above control.

When the control signals REFCLK and M3CHK are input from the counter 27 to the refresh request detection circuit 28 and the detection circuit 28 detects the control signal REFCLK, the control signal REFREQ is output to the refresh circuit 29.

When the refresh circuit 29 detects the control signal REFREQ with the control signal M3EN from the counter 27, the DMA circuit DMA
A refresh address or the like is output to the transfer bus 15 to refresh the dynamic RAM 18. When the refresh is completed, the refresh circuit 29 outputs the control signal REFREQCLR to the refresh request detection circuit 28 to clear the refresh request detection circuit 28.

FIG. 7 is a timing diagram showing the above control.

In this way, the operation of the circuit corresponding to each time slot and the operation preparation of the circuit to be operated in the next time slot are sequentially performed in time division, and the DMA transfer of data is processed at a higher speed.

Further, the arbitration circuit 13 is an address decoder,
Since it can be configured with hardware such as a buffer and a detection circuit, it can be assembled with a logic circuit.
It can be constructed at a lower cost than that which is processed by software using a PU, so that the economical efficiency can be improved and the data transfer rate can be improved.

[0046]

As described above, according to the present invention, the DMA transfer bus is time-division controlled, and the operation and the next operation preparation for the circuits involved in the DMA transfer are simultaneously performed by the hardware. The processing can be realized and the economical efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an arbitration circuit according to the same embodiment.

FIG. 3 is a diagram for explaining timing and control of each time slot in the embodiment.

FIG. 4 is a timing chart showing the timing of the detection of the DMA bus access and the access of the DMA bus of the CPU in the embodiment.

FIG. 5 is a timing chart showing the timing of detecting a DMA transfer request from the transfer source circuit and the timing of DMA transfer in the embodiment.

FIG. 6 is a timing chart showing the timing of detection of a DMA transfer request from the transfer destination circuit and DMA transfer to the transfer destination circuit in the embodiment.

FIG. 7 is a timing chart showing the timing of refresh request detection and refresh operation in the embodiment.

FIG. 8 is a block diagram showing a conventional example.

[Explanation of Codes] 11 ... CPU (microprocessor) 12 ... DMA (direct memory access) circuit 13 ... Arbitration circuit 14 ... CPU operation bus 15 ... DMA transfer bus 16 ... Dynamic RAM 19 ... Transfer source circuit 20 ... Transfer destination circuit

Claims (1)

[Claims] 1. A transfer source circuit that outputs a data output request signal and outputs data, and a data input request signal
A transfer destination circuit for inputting data, a memory for storing data, and access control for this memory, write data from the transfer source circuit to the memory, and read data in the memory to the transfer destination circuit. A direct memory access circuit for controlling, a direct memory access transfer bus for connecting these circuits to transfer data at high speed, and a microprocessor operation bus for data transfer and the direct memory access circuit. A microprocessor for controlling a direct memory access operation using an access transfer bus, and using the direct memory access transfer bus interposed between the direct memory access transfer bus and the microprocessor operation bus Direct memory access during high-speed data transfer The transfer bus is time-divided into a plurality of time slots, and an arbitration circuit is provided for making the corresponding circuit operate in each time slot and preparing the operation of the circuit to be operated in the next time slot. Direct memory access control device.