JPS63278168A - bus controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a DMA (DMA) for exchanging data between an I/O device and a memory device in a computer system.
Direct memory access Direct Memtyr
yAcctzz) control device.

[Conventional technology] −・・
The conventional device is disclosed in Japanese Unexamined Patent Publication No. 59-45571 "D.

One DMA as described in ``Transfer Control Device''.

Activation of memory device or I/O slave.

You can only access one of them.

ing. 1-
1 [Problems to be Solved by the Invention] In the above-mentioned conventional device, in preparation for DMA startup, the register in the device indicates whether the slave is a memory device or if the slave is an I/O device.
Selection information on whether it is an O slave device.

It is necessary to set, and in one DMA start, -
Either a memory device or an I/O slave.

I had a problem with only being able to access one.

The purpose of the present invention is to enable access to both the pre-processed memory device and the I/O slave with one DMA activation, and to transfer data between the memory device and the I/O slave once. The goal is to realize a bus control device that completes with DMA startup.

[Means for solving problems]

The above purpose is: ■ /O bus address space for the CPU.

A portion of the bus address space, and a portion of the I7°0 bus address space as the CPU bus.

Constructed to be the address of the combined memory device.

and, for each DMA transfer cycle, transfers data to and from the CPU bus based on address information from the M/O mass.

A bus control device that switches connections between I/O buses.

This is achieved by configuring.

[Effect]

I-1: The CPU bus address space is address information.

The I/O bus address space consists of addresses. .

If it consists of meB bits (A>B), then l-
Map the l/O (slave) space in the /O bus address space to the CPU bus address space, and conversely map the memory device DMA area in the CPU/U bus address space to the I/O bus address space. (between memory devices 95), and the I/O bus address space is composed of an I/O space and a memory device space.

The I/O master then uses the address information sent from the I/O master for each DMA cycle.

Data transfer cycle/O to master or I/O slave
Notoki does not connect the engineering/O bus and CPU bus.

Data transfer size from I/O mask to memory device.

When running a cruise, connect the engineering/O bus and the CPU bus.

Configure a bus control device that will One for this.

With one DMA activation, the memory device and
Data transfer between threads can be realized.

〔Example〕

First, FIG. 1 shows a bus control device according to the present invention.

About the microprocessor system using the machine.

Briefly explain.　　　　　　　　　　　　　.

, 5.

In the same figure, 1 is CPo, 2 is a memory device, and 3 is DM.
A controller 4 is an interface circuit, and these are all connected to each other via a CPU bus 11. Reference numeral 5 indicates an I/O master, and reference numeral 6 indicates an I/O slave, which are coupled together with the DMA controller 6 and the interface circuit 4 via an I/O bus 12. DM
The A controller 3, based on the address information from the CPU 1 or the address information from the I/O mask 5,
The interface/circuit 4 is operated to connect or disconnect the CPU bus 11 and the I/O bus 12/O. In addition, DMA con.

CP by the controller 3 and the interface circuit 4.

It constitutes a bus control device for the U bus 11 and the I/O bus 12.

ing. PATHl contains information on the engineering/O master 5.

The DMA data 15 path and PATH2 to be transferred to the memory device 2 or vice versa is the information of the /O master 5.

/O DMA transfer to slave 6 or vice versa.

- It is a road.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 6 is an embodiment of the bus control device according to the present invention. 4
.

, 30 is an AND circuit, 31° is an OFL circuit, 62 is a bus abandonment detection circuit, 33 is a synchronization circuit, 54 is a DMA request priority level table, 65 is a DMA request priority determination circuit, 36 is DMA stage co.
controller, 37 is address decoder, 3B, 40.4
15 is a three-state buffer, and 39 is a latch circuit.
・In the same figure, the DMA request priority level table 34
determines the reception priority of the DMA request signal CDRQ(E)/O4 for each of the plurality of I/O masters 5.
This is a table that is set by software, and the DMA request signal CD from multiple I/O masters 5 for simultaneous /O.

If there is RQ(e)/O4, it is passed through the synchronization circuit 36.

The request signal 113 is a DMA request priority level table.

The I/O master that issued the highest level request is inputted to the DMA request priority judgment circuit 65° along with the set value 112 of
DMA permission recognition signal CDACK taste only for 5 star 5)/O
Respond 5°.

Next, the operation of this embodiment is shown in the stage progression shown in Fig. 4.

Transfer, using the timing chart in Figure 5.6.

I will explain.

DMA request signal/CDR sent from I/O master 5
Q(e)/O4 is the OR circuit 31. AND circuit 30・
The bus request signal B R/O0 is sent to the CPU1.
sent to. CP[J1 receives and receives bus requests.
After that, assert the bus enable signal B G /O1 and assert the address strobe PA8/O2 as soon as possible.
After the gate, CPU bus 11 is abandoned, so %BG/O1
．． .

The bus abandonment detection circuit 32 starts DMA from PA8/O2.
Generates signal DMA0N11o.

From the DMA start signal DMA0N1/O, the %DMA stage of the controller (D8C) 36 is set.

As shown in Fig. 4), the CPU bus 11 no.

Assert permission recognition signal BGACK/O3 to CPU1.

and a DMA permission recognition signal to the I/O master 5.

Assert No. CDACK(g)/O5 and I/O bus 1
The address CAl2O of 2□5 is the address P of the CPU bus 11.

A3-state buffer 58° enable signal PAEN/O6 is interfaced to drive A121.

Assert to 4.

Here, the DMA data path is PATH1.

In the case of access, the DMA permission recognition signal CD “AC
I/O master 5 that received K(E)/O5 outputs it.

Address C゛A1 indicating the memory device space (Fig. 2)
19 is received by the address decoder 37 and stored in the memory.

Signal 5P05N1 indicating access to device 7
Assert 17.

5PON 117 causes the stage of D8C56 to transition from ■ to ■ (FIG. 4), and in order to drive the data CD 122 on the I/O bus 12 to the data PD 123 on the CPU bus 11, the 3-state buffer 41 Enape/
Assert the O signal P D EN /O8. memory device.

After receiving the data, D8C36 sends a response signal PD8ACK118, as shown in FIG.

The stage changes from ■ to ■ (Figure 4), CPU.

Negating the bus permission recognition signal BGACK/O5 of bus 11,
5- to give CPU bus exclusive right to CPU bus 11 to CPU1.

At the same time, the PAEN /O6, PDEN /
O8.

Negate.

Also, the DMA data path is PATH1 and read.

In case of access, 2°, 7 by the 5PON 117.

When the stage of DSC36 changes from ■ to ■, C・P
The memory device 2 asserts the enable signal CDEN/O9 of the tri-state bus 40 to drive the data PD 123 of the U bus 1 to the data CD j22 of the I/O bus 12. After sending out ′
Sends response signal PD8ACK11a and
The stage changes from ■ to ■, and the CPU (S11's
C.P. by negating the permission recognition signal BGACK/O3.
At the same time, the bus ownership of the U bus 1 is returned to the CPU 1.

Data P D 123 of CPU bus 11 is transferred to I/O bus 1
The I/O master 5 receives data on the 1° data CD 122 of 2.

Latch 39 to keep driving until you take it.

Pulse the timing signal CDLATCH/O7.

Close and send. After that, I/O master 5 receives data.

After receiving CDI22, the stage of %DSC36 is
Transition from 5■ to I, DMA permission recognition signal CDAC0K
6Jg)/negate O5.

If the DMA data path is PATH2, then the DMA permission acknowledgment signal CDACK, as shown in FIG.

(e) The I/O master 5 that received /O5 outputs the output.

・ 8 ・ Address "CA" indicating /O (slave) space (Figure 2)
119 is received by the address decoder 37, and ■/.

0 signal indicating access to slave 6.

Assert 88ON116. By 5SON116.

The stage of DSC36 is transition from ■ to V, and the first stage is 4.
), the enable signal PAgN/O6 is negated and the bus permission recognition signal BGA-CK of the CPU bus 11 is
/O3 is negated to take possession of the CPU bus 11.
Return to U1. After receiving/receiving data (during write access) or sending/outputting data (during read access), I/O slave 6 sends a response signal CDTAC.

The K115 is sent out and the DSC36 stage starts from ■.

After that, the I/O master 5 changes to data CD.

After receiving 122, DS (J6 stage is ■.

The DMA permission recognition signal CDACK1゜(
e) Negate /O5.

The above operation is performed for each DMA transfer cycle.

By doing so, the PA for one DMA activation.

Reading of information from the memory device 2 by THL.

Write to I/O slave 6 using PATH2. .

P for execution or one DMA activation.

Reading of information from I/O slave 6 by ATH2.

write to memory device 2 by PATHl.

Look at the CPU bus 11. This can be done without reducing the usage efficiency of the I/O bus 12.

〔Effect of the invention〕

As explained above, according to the present invention, one time.

Memory device and I/O slave by DMA activation.

It is possible to realize data transfer between the two, and the throughput of data transfer as a system can be improved. ■/] The specific example of 00 slave is 1 communication age.

Kobrose to support the computing power of pig I/O...
By making it possible to connect this coprocessor to the I/O bus, there is an effect that the throughput of the system can be significantly improved15.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor system using a bus control device according to the present invention, and FIG. 3 is an address map of the above system, FIG. 3 is a program diagram showing an embodiment of the bus control device according to the present invention, and FIG. 4 is a stage transition diagram for explaining the operation of FIG. 3. , FIG. 5, and FIG. 6 are timing charts. 1...CPU 2...Memory device 3...DMA controller 4...Interface 5...I/O mask 6, I/O slave 1
．． . 11...CPU bus 12...I/O bus

Claims (1)

[Claims] 1. A CPU bus that connects a CPU and a memory device;
The I/O bus that connects the O master and I/O slave is
The I/O bus address space is a part of the CPU bus address space;
By configuring a part of the O bus address space to be the address of the memory device, it is possible to access both the memory device and the I/O slave with one DMA activation. bus controller. 2. The control device includes an interface for switching connections between the CPU bus and the I/O bus, and a DMA controller, and the DMA controller includes an address decoder connected to the I/O bus and an address decoder connected to the I/O bus. 2. The bus control device according to claim 1, further comprising at least a DMA stage controller that outputs a control signal for the interface in accordance with an output.