JPH0727924B2 - Manufacturing method of mounting body - Google Patents
Manufacturing method of mounting bodyInfo
- Publication number
- JPH0727924B2 JPH0727924B2 JP12705584A JP12705584A JPH0727924B2 JP H0727924 B2 JPH0727924 B2 JP H0727924B2 JP 12705584 A JP12705584 A JP 12705584A JP 12705584 A JP12705584 A JP 12705584A JP H0727924 B2 JPH0727924 B2 JP H0727924B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- substrate
- electrode
- frame
- frame body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims abstract description 11
- 238000002844 melting Methods 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 239000011347 resin Substances 0.000 claims description 13
- 229920005989 resin Polymers 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 12
- 229920001187 thermosetting polymer Polymers 0.000 claims description 4
- 239000000463 material Substances 0.000 abstract description 5
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 229910020220 Pb—Sn Inorganic materials 0.000 abstract description 2
- 230000001678 irradiating effect Effects 0.000 abstract description 2
- 230000003287 optical effect Effects 0.000 abstract 1
- 238000005304 joining Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 240000002329 Inga feuillei Species 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は複数個の半導体素子を基板上に高密度に搭載す
るための製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method for mounting a plurality of semiconductor elements on a substrate with high density.
従来例の構成とその問題点 近年、半導体素子を多数個用いるデバイス，機器の開発
が促進されてきている。例えば、液晶やELディスプレイ
パネル、TVやVTRのデジタル回路、ICメモリーカード等
があり、これらはいずれも多数個のIC,LSIを定められた
基板面に高密度にしかも薄型に搭載しなければならな
い。基板上に複数個のIC,LSIを搭載するためには、前記
基板の配線電極とIC,LSIの電極とを効率良くしかも信頼
性良く接合しなければならない。このような手段として
従来ワイヤボンディング方式，フリップチップ方式，フ
ィルムキャリヤ方式がある。Configuration of Conventional Example and Problems Thereof In recent years, development of devices and equipment using a large number of semiconductor elements has been promoted. For example, there are liquid crystal and EL display panels, TV and VTR digital circuits, IC memory cards, etc., all of which must have a large number of ICs and LSIs mounted on a predetermined substrate surface with high density and thinness. . In order to mount a plurality of ICs and LSIs on a substrate, the wiring electrodes of the substrate and the electrodes of the ICs and LSIs must be joined efficiently and reliably. As such means, there are conventional wire bonding method, flip chip method, and film carrier method.
ワイヤボンディング方式は、先ず基板に半導体素子をダ
イ・ボンディングする必要があり、また半導体素子上の
電極と基板の配線電極とを一本づつ結線しなければなら
ない。このために、実装の効率が低下するばかりか、製
造コストも高価になるものであった。In the wire bonding method, it is necessary to die-bond the semiconductor element to the substrate first, and the electrodes on the semiconductor element and the wiring electrodes on the substrate must be connected one by one. For this reason, not only the mounting efficiency is lowered, but also the manufacturing cost is increased.
また、フリップチップ方式やフィルムキャリヤ方式にお
いては、半導体素子の一個づつの位置合わせが必要なば
かりか、半導体素子の電極と基板の配線電極との接合も
一個づつ実施しなければならない。数10個の半導体素子
を搭載する場合には、接合時間が長くなるばかりでな
く、一個づつ加熱し、電極を接合するために、隣接する
半導体素子を接合する時に、既に接合の終了した半導体
素子の接合が熱によって、はずれてしまい接合不良を発
生させてしまう等の問題があった。In addition, in the flip chip method and the film carrier method, not only the alignment of the semiconductor elements one by one but also the bonding of the electrodes of the semiconductor element and the wiring electrodes of the substrate must be performed one by one. When several tens of semiconductor elements are mounted, not only the bonding time becomes long, but also when the adjacent semiconductor elements are bonded to heat the electrodes one by one to bond the electrodes, the semiconductor elements that have already been bonded However, there is a problem in that the joining of the two pieces is dislocated due to heat and a joining failure occurs.
発明の目的 本発明は多数個の半導体素子を基板に搭載する場合に、
前記半導体素子の電極と基板上の対向した配線電極との
位置合わせ自己位置合わせするとともに、その場合を一
括して行なうことを目的とするものである。An object of the present invention is to mount a large number of semiconductor elements on a substrate,
The purpose of the invention is to align the electrodes of the semiconductor element with the opposing wiring electrodes on the substrate and to perform self-alignment, and to carry out the case collectively.
発明の構成 本発明は電極を有する半導体素子と、これと相対する配
線電極を有する基板および前記半導体素子の外寸と合致
する孔を有した枠体から構成され、先ず、前記基板上に
枠体を搭載し前記枠体の孔に前記半導体素子を挿入し、
加熱もしくは光照射する事により、前記半導体素子の電
極と基板の配線電極とを一度に接合するものである。Structure of the Invention The present invention comprises a semiconductor element having an electrode, a substrate having a wiring electrode facing the electrode, and a frame having holes matching the outer dimensions of the semiconductor element. First, a frame is provided on the substrate. And insert the semiconductor element into the hole of the frame,
By heating or irradiating light, the electrodes of the semiconductor element and the wiring electrodes of the substrate are joined at once.
前記半導体素子の電極と基板の配線電極を接合させる場
合の圧力は、半導体素子自体の自重もしくは電極に設け
た低融点金属の融解時の表面張力あるいは可撓性フィル
ムを前記半導体素子裏面に設け前記枠体の孔を減圧せし
める事によって得られる構成である。The pressure when joining the electrode of the semiconductor element and the wiring electrode of the substrate is the self-weight of the semiconductor element itself or the surface tension when the low melting point metal provided on the electrode is melted or a flexible film is provided on the back surface of the semiconductor element. This is a configuration obtained by decompressing the holes in the frame.
実施例の説明 第１の実施例を第１図で説明する。電極２を有する半導
体素子１と、これと対向した配線電極３を有する基板４
および前記半導体素子１の外寸と合致した複数の孔５を
有する枠体６から構成されている。Description of Embodiments A first embodiment will be described with reference to FIG. A semiconductor element 1 having an electrode 2 and a substrate 4 having a wiring electrode 3 facing the semiconductor element 1.
And a frame body 6 having a plurality of holes 5 matching the outer dimensions of the semiconductor element 1.
半導体素子１の電極２上には低融点金属が設けられ、前
記低融金属は対向する基板４上の配線電極３の材質とな
じみの良い材質、Pb−Sn合金,InGa合金,Ag等からなる。
また低融点金属は基板４上の配線電極３上に形成しても
良い。A low melting point metal is provided on the electrode 2 of the semiconductor element 1, and the low melting point metal is made of a material that is well compatible with the material of the wiring electrode 3 on the opposing substrate 4, Pb-Sn alloy, InGa alloy, Ag, or the like. .
The low melting point metal may be formed on the wiring electrode 3 on the substrate 4.
先ず、複数の孔５を有する枠体６を基板４上の配線電極
３上に置き、固定する（第１図ｂ）。この時、枠体６
は、孔５に半導体素子１を挿入した時に、半導体素子１
の電極２と基板４上の配線電極３とが一致する様に基板
４上に配線されるものである。First, the frame 6 having the plurality of holes 5 is placed on the wiring electrode 3 on the substrate 4 and fixed (FIG. 1b). At this time, the frame body 6
When the semiconductor element 1 is inserted into the hole 5,
The electrode 2 and the wiring electrode 3 on the substrate 4 are wired on the substrate 4 so that they coincide with each other.
次に、半導体素子１の電極２面を下側にして前記枠体６
の孔５に挿入する。この挿入によって、半導体素子１の
電極２と基板４の配線電極とは自動的に位置合せが行な
われるものである。しかるのち、基板４を全域加熱する
かもしくは半導体素子１の裏面から赤外加熱７を行う。
この加熱７によって、半導体素子１の低融点金属は少な
くとも溶融し、対向する配線電極と接合されるものであ
る（第１図ｃ）。ここで加熱の際に、半導体素子１に多
少の圧力を加えることにより、より確実な接合を得るこ
ともできる。また前記枠体は、絶縁体で一体成型された
構造であっても良いし、アルミニウムの如く金属であっ
て、表面にAl2O3の如く絶縁性の配化膜を設けた構造で
も良い。Next, with the electrode 2 surface of the semiconductor element 1 facing downward, the frame 6
Insert into the hole 5 of By this insertion, the electrode 2 of the semiconductor element 1 and the wiring electrode of the substrate 4 are automatically aligned. After that, the entire area of the substrate 4 is heated, or infrared heating 7 is performed from the back surface of the semiconductor element 1.
By this heating 7, at least the low melting point metal of the semiconductor element 1 is melted and joined to the opposing wiring electrodes (FIG. 1c). Here, by applying some pressure to the semiconductor element 1 during heating, it is possible to obtain more reliable bonding. Further, the frame body may have a structure integrally molded with an insulator, or may have a structure made of metal such as aluminum and having an insulating distribution film such as Al 2 O 3 provided on the surface thereof.
次に第２の実施例を第２図で説明する。半導体素子１、
枠体６、基板４の構成および前記枠体６を基板４の配線
電極３上に載置・固定することは第２図（ａ），（ｂ）
に示した如く、第１の実施例と同一である。前記枠体６
の孔に半導体素子１を挿入した後、ポリイミドフィル
ム，エポキシフィルム，テフロンフィルムの如く耐熱性
の可撓性フィルム８で前記枠体６を含めて半導体素子１
の裏面を覆わせる。ついで、基板もしくは枠体に設けた
真空孔（図示していない）により枠体の孔の半導体素子
１の挿入されている領域の空間すなわち基板４と可撓性
フィルム８で囲まれた空間を減圧する（第２図ｃ）。こ
の減圧により、半導体素子１は、基板４の配線電極３に
押圧されるから、この状態で基板４を加熱するかもしく
は半導体素子１を加熱せしめ、例えば低融点金属により
相互の電極同士を接合せしめる。この実施例の如く、可
撓性フィルムを用いて空間を減圧せしめ、これにより加
圧すれば半導体素子の電極に加わる加重が均等にしかも
平均に加わるから、全ての電極に対し確実な接合を得る
ことができる。Next, a second embodiment will be described with reference to FIG. Semiconductor element 1,
The configurations of the frame body 6 and the substrate 4 and the mounting and fixing of the frame body 6 on the wiring electrodes 3 of the substrate 4 are shown in FIGS.
The same as the first embodiment, as shown in FIG. The frame 6
After inserting the semiconductor element 1 into the hole of the semiconductor element 1 including the frame body 6 with a heat-resistant flexible film 8 such as a polyimide film, an epoxy film, or a Teflon film.
Cover the back of the. Next, a vacuum hole (not shown) provided in the substrate or the frame body decompresses the space in the area of the frame body in which the semiconductor element 1 is inserted, that is, the space surrounded by the substrate 4 and the flexible film 8. (Fig. 2c). The semiconductor element 1 is pressed against the wiring electrode 3 of the substrate 4 by this decompression, so that the substrate 4 is heated in this state or the semiconductor element 1 is heated, for example, the mutual electrodes are joined by a low melting point metal. . As in this embodiment, the flexible film is used to reduce the pressure in the space, and if the pressure is applied, the load applied to the electrodes of the semiconductor element is evenly and evenly applied, so that reliable bonding is obtained for all the electrodes. be able to.
次に第３の実施例を第３図で説明する。Next, a third embodiment will be described with reference to FIG.
基板４上に枠体６を載置した後、枠体６の孔５に光また
は熱硬化型樹脂10を塗布し（第３図ｂ）、ついで、半導
体素子１を孔５に挿入し、圧接しながら熱又は光７を加
える（第３図ｃ）。この工程により、樹脂10は押し拡げ
られ、半導体素子１の電極２と基板４上の配線電極３と
は圧接され、かつこの状態で樹脂は硬化10′されるか
ら、半導体素子１も基板４に固定されることになる。こ
の実施例において、電極同志の接合をより高めるため
に、半導体素子の電極もしくは基板の配線電極上に金属
突起を形成させた構成であっても良い。After placing the frame 6 on the substrate 4, the light or thermosetting resin 10 is applied to the hole 5 of the frame 6 (FIG. 3b), and then the semiconductor element 1 is inserted into the hole 5 and pressure-bonded. While applying heat or light 7 (Fig. 3c). By this step, the resin 10 is spread out, the electrode 2 of the semiconductor element 1 and the wiring electrode 3 on the substrate 4 are pressure contacted, and the resin is cured 10 'in this state, so that the semiconductor element 1 is also attached to the substrate 4. It will be fixed. In this embodiment, a metal protrusion may be formed on the electrode of the semiconductor element or the wiring electrode of the substrate in order to enhance the bonding between the electrodes.
第４図の実施例は、第３図の実施例を改良したものであ
る。すなわち、枠体６の孔５に光または熱硬化型樹脂10
を塗布（第４図ｂ）し、半導体素子１を導入した後、可
撓性フィルム８で前記枠体を含めて、半導体素子１の裏
面を覆い、枠体もしくは基板に設けて真空孔（図示せ
ず）により、孔内部を減圧状態にせしめた後、樹脂を硬
化して硬化樹脂10とする（第４図ｃ）。The embodiment of FIG. 4 is an improvement of the embodiment of FIG. That is, the light or thermosetting resin 10 is placed in the hole 5 of the frame body 6.
Is applied (FIG. 4b), the semiconductor element 1 is introduced, the back surface of the semiconductor element 1 is covered with the flexible film 8 including the frame body, and the frame body or the substrate is provided with a vacuum hole (see FIG. After depressurizing the inside of the hole by (not shown), the resin is cured to obtain a cured resin 10 (Fig. 4c).
この減圧状態により、樹脂10は半導体素子１の表面と基
板４面とのわずかな隙間にも浸入する事になるから強い
接合が得られ、かつ、半導体素子１の表面の確実な保護
樹脂としても効果がある。Due to this reduced pressure state, the resin 10 will also penetrate into a slight gap between the surface of the semiconductor element 1 and the surface of the substrate 4, so that a strong bond can be obtained and also as a reliable protective resin for the surface of the semiconductor element 1. effective.
発明の効果 本発明では、基板上に載置する枠体によって複数の半
導体素子の電極と基板の配線電極との位置合せを一括し
て実施する構成である。すなわち、基板上に枠体を載置
・固定するのみで、基板上に搭載する全ての半導体素子
の位置合せを不要とし、一括して処理できるものであ
る。したがって、従来半導体素子をひとつづつ位置合せ
した時間が必要でなく製造に要する時間を著じるしく短
縮できるものである。EFFECTS OF THE INVENTION The present invention has a structure in which the electrodes of a plurality of semiconductor elements and the wiring electrodes of the substrate are collectively positioned by the frame body mounted on the substrate. That is, only by mounting and fixing the frame on the substrate, it is not necessary to align all the semiconductor elements mounted on the substrate, and the processing can be performed collectively. Therefore, the time required for aligning the semiconductor elements one by one in the related art is not required, and the time required for manufacturing can be remarkably shortened.
また枠体の孔に半導体素子を挿入した後、お互いの電
極同志の接合も、基板全体あるいは半導体素子を加熱す
るのみで全ての半導体素子の接合を一括・同時に実施で
きる。したがって、製造コストが著じるしく低減できる
効果がある。Further, after the semiconductor element is inserted into the hole of the frame body, the electrodes can be bonded to each other at once by heating the entire substrate or the semiconductor elements at once. Therefore, there is an effect that the manufacturing cost can be remarkably reduced.
枠体に半導体素子を挿入し、可撓性フィルムで覆い、
枠体内の孔を減圧にすることにより、電極面および電極
面と均一で、平均した加重を加えることができるから、
確実で信頼性の高い接合を得る事ができる。Insert the semiconductor element into the frame, cover with a flexible film,
By reducing the pressure in the holes in the frame, it is possible to apply a uniform and averaged weight to the electrode surface and the electrode surface.
It is possible to obtain a reliable and reliable joint.
第１図（ａ）〜（ｃ）は本発明の第１の実施例を示す工
程図、第２図（ａ）〜（ｃ）は可撓性フィルムを用いた
第２の実施例を示す工程図、第３図（ａ）〜（ｃ）は接
合に樹脂を用いた第３の実施例を示す工程図、第４図
（ａ）〜（ｃ）は第３の実施例において可撓性フィルム
を用いた第４の実施例の工程図である。 １……半導体素子、２……電極、３……配線電極、４…
…基板、６……枠体、８……可撓性フィルム、10……光
または熱硬化性樹脂。1A to 1C are process drawings showing a first embodiment of the present invention, and FIGS. 2A to 2C are processes showing a second embodiment using a flexible film. 3A to 3C are process drawings showing a third embodiment using a resin for joining, and FIGS. 4A to 4C are flexible films in the third embodiment. It is a process drawing of the 4th example using. 1 ... Semiconductor element, 2 ... Electrode, 3 ... Wiring electrode, 4 ...
... Substrate, 6 ... Frame, 8 ... Flexible film, 10 ... Light or thermosetting resin.
Claims (4)
半導体素子と、前記半導体素子の外寸と合致し、前記半
導体素子を挿入するための複数の孔を有する枠体、前記
枠体を載置し、前記半導体素子の電極と対向した位置に
配線電極を有する基板を用い、前記基板に前記枠体を載
置し、ついで前記枠体の複数の孔に前記半導体素子を挿
入した後、前記基板もしくは半導体素子を加熱すること
を特徴とする実装体の製造方法。1. A semiconductor element in which at least a low melting point metal is formed on an electrode, a frame body having a plurality of holes for inserting the semiconductor element, the frame body being fitted with the outer dimensions of the semiconductor element, and the frame body being mounted thereon. Placed, using a substrate having a wiring electrode at a position facing the electrode of the semiconductor element, the frame is placed on the substrate, then after inserting the semiconductor element into a plurality of holes of the frame, the A method for manufacturing a mounting body, which comprises heating a substrate or a semiconductor element.
記枠体上面および半導体素子の裏面を可撓性フィルムで
覆い、前記枠体の孔の空間を減圧せしめ、前記半導体素
子もしくは基板を加熱することを特徴とする特許請求の
範囲第１項記載の実装体の製造方法。2. A semiconductor element is inserted into a plurality of holes of a frame body, the upper surface of the frame body and the back surface of the semiconductor element are covered with a flexible film, and the space of the hole of the frame body is decompressed. The method for manufacturing a mounting body according to claim 1, wherein the substrate is heated.
子の外寸と合致し前記半導体素子を挿入するための複数
の孔を有する枠体、前記枠体を載置し、前記半導体素子
の電極と対向した位置に配線電極を有する基板を用い、
前記基板に前記枠体を載置し、前記枠体の複数の孔もし
くは前記半導体素子の電極側に光または熱硬化性樹脂を
塗布せしめた後、前記枠体の複数の孔に前記半導体素子
を挿入し、前記樹脂を光または熱によって硬化せしめる
ことを特徴とする実装体の製造方法。3. A semiconductor element having an electrode, a frame body having a plurality of holes for matching the outer dimensions of the semiconductor element and for inserting the semiconductor element, the frame body is mounted, and the electrode of the semiconductor element is mounted. Using a substrate having a wiring electrode at a position facing
The frame is placed on the substrate, and light or thermosetting resin is applied to the plurality of holes of the frame or the electrode side of the semiconductor element, and then the semiconductor element is provided in the plurality of holes of the frame. A method of manufacturing a mounting body, which comprises inserting and curing the resin by light or heat.
後、前記枠体上面および半導体素子の裏面を可撓性フィ
ルムで覆い、前記枠体の孔の空間を減圧せしめ、前記樹
脂を光または熱によって硬化せしめることを特徴とする
特許請求の範囲第３項記載の実装体の製造方法。4. A semiconductor element is inserted into a plurality of holes of a frame body, and then the upper surface of the frame body and the back surface of the semiconductor element are covered with a flexible film to reduce the pressure in the space of the hole of the frame body, and the resin is removed. The mounting body manufacturing method according to claim 3, wherein the mounting body is cured by light or heat.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12705584A JPH0727924B2 (en) | 1984-06-20 | 1984-06-20 | Manufacturing method of mounting body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12705584A JPH0727924B2 (en) | 1984-06-20 | 1984-06-20 | Manufacturing method of mounting body |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS616833A JPS616833A (en) | 1986-01-13 |
| JPH0727924B2 true JPH0727924B2 (en) | 1995-03-29 |
Family
ID=14950479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12705584A Expired - Lifetime JPH0727924B2 (en) | 1984-06-20 | 1984-06-20 | Manufacturing method of mounting body |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0727924B2 (en) |
Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0248566A3 (en) * | 1986-05-30 | 1990-01-31 | AT&T Corp. | Process for controlling solder joint geometry when surface mounting a leadless integrated circuit package on a substrate |
| JPH0797595B2 (en) * | 1988-03-16 | 1995-10-18 | 富士通株式会社 | Semiconductor component mounting method |
| JPH02256252A (en) * | 1989-03-29 | 1990-10-17 | Omron Tateisi Electron Co | Method of packaging electronic part |
| JPH04369847A (en) * | 1990-08-30 | 1992-12-22 | Micron Technol Inc | Semiconductor assembly |
| JP5715412B2 (en) * | 2010-12-28 | 2015-05-07 | アルプス電気株式会社 | Manufacturing method of load sensor |
| EP2980870B1 (en) | 2013-03-28 | 2018-01-17 | Toshiba Hokuto Electronics Corporation | Light-emitting device, production method therefor, and device using light-emitting device |
| CN107768362B (en) | 2013-03-28 | 2020-09-08 | 东芝北斗电子株式会社 | Light emitting device and method for manufacturing the same |
| EP3079175A4 (en) | 2013-12-02 | 2018-04-11 | Toshiba Hokuto Electronics Corporation | Light-emission device |
| WO2015083365A1 (en) | 2013-12-02 | 2015-06-11 | 東芝ホクト電子株式会社 | Light-emission device, and production method therefor |
| CN105518886A (en) | 2013-12-02 | 2016-04-20 | 东芝北斗电子株式会社 | Light-emission unit, light-emission device, and light-emission-unit production method |
| JPWO2015146115A1 (en) | 2014-03-25 | 2017-04-13 | 東芝ホクト電子株式会社 | Light emitting device |
| WO2016047132A1 (en) | 2014-09-26 | 2016-03-31 | 東芝ホクト電子株式会社 | Light-emission module |
| JP6913460B2 (en) | 2014-09-26 | 2021-08-04 | 東芝ホクト電子株式会社 | Luminous module |
-
1984
- 1984-06-20 JP JP12705584A patent/JPH0727924B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS616833A (en) | 1986-01-13 |
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