JPH07273282A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device in which an arrangement is not limited, whose cost can be lowered and whose reliability is high. CONSTITUTION:Heat-generating semiconductor elements (a first PNP transistor 20 and a second PNP transistor 30) which generate heat in their operation and control parts (a resistor 40 and an NPN transistor 50) which control them are formed inside a substrate 1. After that, a heat isolation groove 60 is formed between the first PNP transistor 20 and the resistor 40 by a laser cutter. A substance whose heat conductivity is low is filled into the heat isolation groove 60 which has been formed. Thereby, heat which is generated from the first PNP transistor 20 is not conducted to the resistor 40, and a change in a control characteristic due to heat is not generated between the resistor 40 and the NPN transistor 50. The heat-generating semiconductor elements and the control parts are isolated thermally from each other, it is not required to arrange the heat-generating semiconductor elements and the control parts by taking their positions into consideration, and it is not required to install the heat-generating semiconductor elements and the control parts on separate substrates.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improving reliability and reducing cost.

[0002]

2. Description of the Related Art Generally, there are various kinds of so-called one-chip integrated circuits in which various circuits are formed on one substrate. In some of these, a power transistor and a control transistor for controlling the power transistor are formed on the same substrate.

An example of such a one-chip integrated circuit 100 is shown in FIG. In the one-chip integrated circuit 100, the power transistor 90, the first control transistor 80, and the second control transistor 85 are provided in the substrate 1. First
Control transistor 80 and second control transistor 85
Perform normal control by maintaining operating temperatures substantially equal to each other. The power transistor 90 is used as a power source and generates a large amount of heat during operation.

[0004]

However, the conventional one-chip integrated circuit 100 has the following problems.

When the first control transistor 80 and the second control transistor 85 are arranged as shown in FIG. 7, there is a difference in the distance from the power transistor 90 to each control transistor. Due to this distance difference, the power transistor 9
Most of the heat generated from 0 is generated by the second control transistor 8
5 and a little to the first control transistor 80.

As described above, if there is a difference in the amount of heat transferred between the first control transistor 80 and the second control transistor 85, the control characteristics of both control transistors will be distorted. If the control characteristics of both control transistors are incorrect, the power transistor 90 cannot be accurately controlled, and there is a problem of lack of reliability.

In order to solve the above problems, the following measures have been conventionally taken. As one of them, in the design stage of the one-chip integrated circuit 100, the positions of the first control transistor 80 and the second control transistor 85 are arranged so that the heat from the power transistor 90 is transferred almost equally. As the second, the first control transistor 80 and the second control transistor 85 are provided on a substrate different from the substrate on which the power transistor 90 is provided.

However, the first countermeasure has a problem that the layout of the control transistor with respect to the power transistor 90 is limited when designing the one-chip integrated circuit. In particular, when there are a plurality of power transistors, there is a problem that the arrangement of control transistors is extremely limited. In the second measure, the control transistor is provided on a substrate different from the substrate on which the power transistor is provided, which causes a problem of high cost.

Therefore, the present invention is not limited to the arrangement,
An object of the present invention is to provide a highly reliable semiconductor device which can be manufactured at low cost.

[0010]

According to another aspect of the present invention, there is provided a semiconductor device, wherein a substrate, a heat generating semiconductor element that is provided in the substrate and generates heat during operation, and provided in the substrate at a predetermined interval from the heat generating semiconductor element. In a semiconductor device including a control unit that controls the heat generating semiconductor element, a heat separating unit is provided on a substrate between the control unit and the heat generating semiconductor element.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a thermal separation groove is formed in the substrate as the thermal separation means, and a substance having a low thermal conductivity is put in the thermal separation groove. Is characterized by.

According to another aspect of the semiconductor device of the present invention, a substrate, a heat generating semiconductor element which is provided in the substrate and generates heat during operation, and a heat generating semiconductor element which is provided in the substrate at a predetermined interval from the heat generating semiconductor element. In a semiconductor device having a control section for controlling the control section, a control section provided in the substrate and a separation area for separating each of the heat generating semiconductor elements at a predetermined interval, It is characterized by being formed of a low substance.

A semiconductor device according to a fourth aspect of the present invention is a substrate, a heat generating semiconductor element that is provided in the substrate and generates heat during operation, and is provided in the substrate at a predetermined interval from the heat generating semiconductor element. A control unit that controls the elements,
In a semiconductor device comprising: a heat radiation column connected to the bottom of the substrate to radiate heat from the heat generation semiconductor element to the bottom surface, and the heat radiation column is provided between the control section and the heat generation semiconductor element. And a heat dissipation plate that is connected to the heat dissipation column and covers the surface of the substrate to evenly dissipate the heat from the heat dissipation column to the entire surface of the substrate.

[0014]

In the semiconductor device according to any one of claims 1 to 3, the heat separating means is provided by putting a substance having a low thermal conductivity into the substrate between the control section and the heat generating semiconductor element, and the separating area is provided. Is formed of a material having a low heat transfer coefficient and separates the heat generating semiconductor element and the control unit at predetermined intervals. Therefore, the heat generated by the heat generating semiconductor element is not transmitted to the control unit, and the control characteristic does not change due to the heat in the control unit. Further, since the heat generating semiconductor element and the control unit are thermally separated from each other, it is not necessary to arrange them in consideration of the positions of the heat generating semiconductor element and the control unit. No need to provide.

According to another aspect of the semiconductor device of the present invention, the heat radiating pillar radiates the heat from the heat generating semiconductor element to the bottom surface of the heat radiating substrate, and the heat radiating plate radiates the heat from the heat radiating pillar evenly over the entire surface of the substrate. To do. Therefore, heat is not accumulated in the substrate and the temperature of the substrate becomes substantially uniform.

[0016]

EXAMPLE An example of a semiconductor device (one-chip integrated circuit) according to the present invention will be described below. FIG. 1A shows a cross-sectional view of the one-chip integrated circuit 200 of this embodiment. The 1-chip integrated circuit 200 includes a first PN, which is a heat generating portion, in the substrate 1.
P-type transistor 20 and second PNP-type transistor 3
0, a resistor 40 as a control unit, and an NPN transistor 50 are formed. Further, each semiconductor element is electrically isolated by an isolation 80 which is an isolation region. Further, a heat separation groove 60, which is a heat separation means, is formed between the first PNP transistor 20 and the resistor 40.

A substance having a low thermal conductivity, such as carbon, is embedded in the heat separation groove 60. Further, a passivation film 65 is provided on the surface of the substrate 1 on which each semiconductor element is formed, and a plastic mold 73 is formed on the passivation film 65.

An equivalent circuit of this one-chip integrated circuit 200 is shown in FIG. 1B. As shown in the equivalent circuit of FIG. 1B, in the one-chip integrated circuit 200, the collector voltage Vcc is applied to the first PNP transistor 20 and the second PNP transistor 30, and the base current I of the first PNP transistor 20 is applied.
This is a circuit that limits B. It is the first PNP transistor 20 and the second PNP transistor 30 that generate heat in the one-chip integrated circuit 200.

Next, the formation of the heat separation groove 60 and the embedding of a substance having a low thermal conductivity in the substrate 1 will be described. A cross-sectional view of the one-chip integrated circuit 200 before the formation of the heat separation groove 60 is shown in FIG. 2A. Note that the passivation film 65 is not formed in the step shown in FIG. 2A.

The first PNP of this one-chip integrated circuit 200
A thermal isolation groove 60 is formed between the mold transistor 20 and the resistor 40 by a laser cutter (FIG. 2B). After forming the thermal separation groove 60, a material having a low thermal conductivity, for example, carbon is deposited in the thermal separation groove 60. After carbon deposition,
A passivation film 65 is formed on the surface of the substrate 1. After forming the passivation film 65, the passivation film 65
A plastic mold is formed on the entire upper surface. In this way, the one-chip integrated circuit 200 shown in FIG. 1A is formed.

In the following embodiments of the present invention, the heat generated from the first PNP transistor 20 or the second PNP transistor 30 is evenly distributed in the first PNP transistor 20 and the resistor 40. Suppose that

Next, generation and transfer of heat in the one-chip integrated circuit 200 will be described. When the formed 1-chip integrated circuit 200 operates, the first PNP transistor 20 or the second PNP transistor 30 to which the collector voltage Vcc is applied generates the most heat (see FIG. 1B). The heat generated in the first PNP-type transistor 20 passes through the substrate 1 and the resistors 40 and N.
It tries to transmit to the PN type transistor 50 (see FIG. 1A).

However, this heat transfer is hindered by the heat separation groove 60 in which a substance having a low heat conductivity is embedded. As a result, the heat from the first PNP transistor 20 does not reach the resistor 40 and the NPN transistor 50, and the resistor 40 and the NPN transistor 5
The operating temperature between 0 is uniform.

That is, the control characteristic between the resistor 40 or the NPN type transistor 50 is not changed by the heat from the first PNP type transistor 20. Therefore, the resistor 40 and the NPN transistor 50 can perform appropriate control with respect to each other, and the one-chip integrated circuit 20.
It is possible to perform normal operation as a whole, and reliability is improved.

Further, since the control characteristic between the resistor 40 and the NPN transistor 50 is not changed by blocking the heat transfer of the heat separation groove 60, both semiconductor elements are connected to the first PNP.
-Type transistor 20 and second PNP-type transistor 30
Since it is not necessary to form it on a substrate different from that described above, the cost can be reduced.

Further, the first PNP is formed by the heat separation groove 60.
Since heat transfer from the N-type transistor 20 is blocked, the resistor 40 or the NPN-type transistor 50 is placed at the first P position.
It is not necessary to arrange so that the heat from the NP-type transistor 20 is equally transferred. Therefore, the placement of the resistor 40 or the NPN transistor 50 in the one-chip integrated circuit 200 is not limited.

A part of the heat generated from the first PNP type transistor 20 tries to be transferred to the resistor 40 through the plastic mold 75. However, since the upper surface of the plastic mold 75 is in direct contact with the atmosphere, this heat is released into the atmosphere. Therefore, the first P
The heat from the NP-type transistor 20 is generated by the resistor 40 and the N
It does not reach the PN transistor 50.

By the way, in the above embodiment, the heat separation groove 60 was formed in the substrate 1 by a laser cutter. However, another method may be used as long as the heat separation groove 60 can be reliably formed, for example, etching may be used. Further, in the above-described embodiment, carbon is embedded in the thermal separation groove 60, but the thermal conductivity is low, and the first PNP transistor 20 and the resistor 40 are provided.
Other substances may be used as long as they can separate the spaces. For example, plastic may be used as the dielectric substance, and ceramic or rubber may be used as the insulating substance.

Another embodiment of the one-chip integrated circuit according to the present invention will be described below. FIG. 3A shows a cross-sectional view of the one-chip integrated circuit 300 of this embodiment. 1-chip integrated circuit 30
The structure of 0 is almost the same as the one-chip integrated circuit 200 shown in FIG. 2A. However, the one-chip integrated circuit 3 of this embodiment is
2A is different from the one-chip integrated circuit 200 of FIG. 2A in that the isolation groove 60 is not formed and the isolation 80 formed between the semiconductor elements is a substance having a low thermal conductivity.

Next, the case where the isolation 80 is made of a material having a low thermal conductivity will be described. The formation of each isolation 80 on the substrate 1 is performed simultaneously,
For convenience of description, the first PNP transistor 20 and the second PNP transistor 20
The formation of isolation between the NP-type transistors 30 will be described (see FIG. 3A).

First, after the substrate 1 is epitaxially grown, a photoresist film 15 is formed on the surface of the substrate (FIG. 3).
B). The substrate 1 is etched using the formed photoresist film 15 as a mask. As a result, the isolation recess 82 is formed in the etched portion (FIG. 3C).

The substrate 1 on which the isolation recesses 82 have been formed is polished (mechanical grinding) from the lower surface of the substrate until the thickness level L1 is reached. After removal by mechanical grinding, a material with low thermal conductivity (eg carbon) is deposited in the isolation recess 82 (FIG. 3D). Through the above procedure, each isolation 80 in the substrate 1 is formed at the same time.

After vapor deposition of carbon, the photoresist film 15 is removed, and thereafter, a semiconductor is formed by an ordinary procedure to complete the one-chip integrated circuit 300 (see FIG. 3A).

Next, generation and transfer of heat in the one-chip integrated circuit 300 will be described. Even in this case, the most heat is generated when the one-chip integrated circuit 300 operates.
The first PNP transistor 20 or the second PNP transistor 30 (see FIG. 1B). The heat generated in the first PNP transistor 20 tries to transfer to the resistor 40 through the substrate 1 (see FIG. 3A).

However, heat transfer is blocked by the isolation 80 formed between the first PNP transistor 20 and the resistor 40 and having a substance having a low thermal conductivity embedded therein. As a result, the first PNP transistor 2
The heat from zero does not reach the resistor 40. Further, an isolation 80 similar to the above is formed between the resistor 40 and the NPN transistor 50. Therefore, the resistor 40 and the NPN transistor 50 are thermally isolated from each other, and the operating temperatures of both semiconductor elements are substantially equal.

That is, the control characteristic of the resistor 40 or the NPN type transistor 50 is the same as the first PNP type transistor 2
It does not change due to heat from 0. Therefore,
The resistor 40 and the NPN transistor 50 can appropriately control each other, and can operate normally as a whole of the one-chip integrated circuit 300, which is highly reliable.

In addition, the control characteristics of the resistor 40 and the NPN type transistor 50 do not change due to the prevention of heat transfer by the isolation 80, and both semiconductor elements are connected to the first PNP type transistor 20 and the second PNP type transistor 30. Since it is not necessary to form it on another substrate, the cost can be reduced.

Further, since the heat transfer from the first PNP transistor 20 is blocked by the isolation 80, the heat from the first PNP transistor 20 is equally transferred to the position of the resistor 40 or the NPN transistor 50. No need to place. Therefore, the placement of the resistor 40 or the NPN transistor 50 in the one-chip integrated circuit 300 is not limited.

Also in this embodiment, a part of the heat from the first PNP transistor 20 tries to be transferred to the resistor 40 through the plastic mold 75.
However, since the upper surface of the plastic mold 75 is in direct contact with the atmosphere, this heat is released into the atmosphere. Therefore, the heat from the first PNP type transistor 20 does not reach the resistor 40 and the NPN type transistor 50.

By the way, in the above embodiment, the substrate 1
The isolation hole 82 is formed by etching. However, surely the isolation hole 82
Other methods may be used as long as they can be formed by, for example, a laser cutter.

In the above embodiment, carbon is embedded in the isolation hole 82, but any other substance may be used as long as it has a low thermal conductivity and can electrically insulate adjacent circuits. For example, rubber may be used.

Another embodiment of the one-chip integrated circuit according to the present invention will be described below. FIG. 4A shows a cross-sectional view of the one-chip integrated circuit 500 of this embodiment. The structure of the 1-chip integrated circuit 500 is the same as that of the 1-chip integrated circuit 20 of the above embodiment.
It is similar to 0 and 1 chip integrated circuits 300.

However, the one-chip integrated circuit 50 of this embodiment is
0 is connected to the base substrate 10 as a heat dissipation substrate having heat dissipation fins 70 that are heat dissipation columns on the bottom of the substrate 1.
It differs from other one-chip integrated circuits in that a plastic mold 75, which is a heat dissipation plate, is connected to the heat dissipation fin 70.

The radiating fin 70 is made of a material having a high heat transfer coefficient (for example, copper), is connected to the bottom of the base substrate 10, and is provided between the first PNP transistor 20 and the resistor 40. On the other hand, the plastic mold 75 is formed on the surface of the substrate 1 so as to cover the entire surface thereof, and is connected to the heat radiation fins 70.

Next, the case where the ground substrate 10 having the radiation fins 70 is connected to the substrate 1 will be described. First, each semiconductor element is formed on the substrate 1 according to a normal procedure (see FIG. 4A). Here, before forming the passivation film 65 on the substrate 1, a radiation fin hole 73 is formed by a laser cutter on the substrate surface between the first PNP transistor 20 and the resistor 40 (FIG. 4B).

A passivation film 65 is formed on the surface of the substrate after the radiation fin holes 73 are formed. The radiation fin 7 is shown in FIG. 4C.
FIG. 4D shows a plan view of the ground substrate 10 having 0, and FIG. 4D shows a side view of the ground substrate 10.

Next, the ground substrate 10 is connected to the bottom surface of the substrate 1 shown in FIG. 4B by die bonding. FIG. 5A is a plan view showing the state of the ground substrate 10 and the substrate 1 after connection.
And a side view is shown in FIG. 5B. After connecting the ground substrate 10 and the substrate 1, the pads of each semiconductor element are wired by wires (not shown). After wiring, the plastic mold 75 is formed on the surface of the substrate 1 and the base substrate 1.
It is provided so as to cover 0 and is connected to the radiation fin 70. FIG. 6A shows a plan view showing the surface of the substrate 1 covered with the plastic mold 75 and the base substrate 10, and a side view of the substrate 1 and the base substrate 10 is shown in FIG. 6B.

Next, generation and transfer of heat in the one-chip integrated circuit 500 will be described. 1-chip integrated circuit 5
00, the first PNP transistor 2
0, the second PNP transistor 30 generates heat (see FIG. 1B). Here again, the first PNP transistor 20
The heat generated in 1 tends to transfer to the resistor 40 through the substrate 1 (see FIG. 4A).

However, this heat is transferred to the base substrate 10 and radiated by the radiation fins 70 provided between the first PNP type transistor 20 and the resistor 40. Therefore, heat is not accumulated in the substrate 1 and reliable and quick heat dissipation can be performed. Further, the heat transferred to the heat radiation fin 70 is transferred to the plastic mold 75 connected thereto at the same time as the heat radiation to the base substrate 10.

Here again, since the upper surface of the plastic mold 75 is in direct contact with the atmosphere, part of the heat is released into the atmosphere. However, unlike the above embodiment, the amount of heat transferred from the radiation fin 70 to the plastic mold 75 is large, so that the heat is transferred to the resistor 40 and the NPN transistor 50 through the plastic mold 75.

That is, a part of the heat transferred to the radiation fin 70 is released into the atmosphere, but most of the heat is transferred through the plastic mold 75 covering the entire surface of the substrate 1 to the entire surface of the substrate 1. It Therefore, the temperature of the substrate becomes substantially uniform.

That is, in the present embodiment, unlike the above embodiment, the heat from the first PNP type transistor 20 is not cut off, but is evenly distributed over the entire substrate. Therefore, the operating temperature of the resistor 40 or the NPN type transistor 50 becomes equal. As a result, the control characteristics between the two semiconductor elements do not change due to the heat from the first PNP transistor 20.

In other words, the resistor 40 and the NPN type transistor 50 can mutually perform appropriate control,
The 1-chip integrated circuit 500 as a whole can operate normally and is highly reliable.

Further, since the operating temperatures of the resistor 40 and the NPN type transistor 50 are equalized, it is not necessary to form both semiconductor elements on the substrate different from the first PNP type transistor 20 and the second PNP type transistor 30, and the cost is reduced. Can be achieved.

Furthermore, the uniform heat transfer to the entire substrate by the plastic mold 75 allows the resistor 40 or NP
The position of the N-type transistor 50 does not need to be arranged at a position where the heat from the first PNP-type transistor 20 is equally transferred. Therefore, the placement of the resistor 40 or the NPN transistor 50 in the one-chip integrated circuit 500 is not limited.

In the above embodiment, the radiation fin holes 73 are formed in the substrate 1 by the laser cutter. However, other methods may be used as long as the radiation fin holes can be formed reliably, for example, etching may be used.

Further, in the above embodiment, the radiation fin 70 is made of copper, but it may be made of other material as long as it has a high heat transfer coefficient, for example, iron, gold, silver or aluminum. Good. Further, in the above-described embodiment, the height of the protruding portion of the radiation fin 70 on the substrate surface is determined by the plastic mold 7
It was almost the same as 5. However, if reliable and quick heat dissipation is possible, as shown in FIG.
0 may be provided so as to penetrate the plastic mold 75.

[0058]

In the semiconductor device according to any one of claims 1 to 3, the heat separating means is provided by putting a substance having a low thermal conductivity into the substrate between the control section and the heat generating semiconductor element. The isolation region is formed of a material having a low heat transfer coefficient and separates the heat generating semiconductor element and the control unit at a predetermined interval. Therefore, the heat generated by the heat generating semiconductor element is not transmitted to the control unit, and the control characteristic does not change due to the heat in the control unit. Further, since the heat generating semiconductor device and the control unit are thermally separated from each other,
It is not necessary to dispose the heat generating semiconductor element and the control unit in consideration of their positions, and it is not necessary to provide the heat generating semiconductor element and the control unit on different substrates. Therefore, the arrangement is not limited, the cost can be reduced, and the reliability is high.

In the semiconductor device according to the fourth aspect, the heat dissipation pillar radiates heat from the heat generating semiconductor element to the bottom surface of the heat dissipation board, and the heat dissipation plate uniformly dissipates heat from the heat dissipation pillar to the entire surface of the board. To do. That is, heat is not accumulated in the substrate, and the temperature of the substrate becomes substantially uniform. Therefore, it becomes possible to radiate heat reliably and promptly.

[Brief description of drawings]

FIG. 1 is a diagram showing a cross section and an equivalent circuit of one embodiment of a one-chip integrated circuit according to the present invention.

FIG. 2 is a cross-sectional view showing a process for forming the one-chip integrated circuit shown in FIG.

3A and 3B are cross-sectional views showing a forming process of another embodiment of the one-chip integrated circuit according to the present invention and a cross-section of the one-chip integrated circuit.

FIG. 4 is a diagram showing a cross section of another embodiment of a one-chip integrated circuit according to the present invention and a plane of a substrate and a base substrate.

FIG. 5 is a side view showing a base substrate and a plan view and a side face of the substrate after the base substrate is attached.

6A and 6B are a plan view and a side view when a plastic mold is provided on the substrate after the base substrate shown in FIG. 5 is attached.

FIG. 7 is a plan view showing an example of arrangement of power transistors and transistors in a conventional one-chip integrated circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Substrate 20 ... First PNP-type transistor 30 ... Second PNP-type transistor 40 ... Resistor 50 ... NPN-type transistor 60 ... Thermal separation groove

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koichi Yamazaki, 21, Saiin Mizozaki-cho, Ukyo-ku, Kyoto City, Kyoto Prefecture Rome (72) Inventor, Keisuke Naganuma 21, Saiin-Mizozaki-cho, Kyoto City, Kyoto Prefecture Rome Within the corporation

Claims (4)

[Claims] 1. A substrate, a heat generating semiconductor element that is provided in the substrate and generates heat during operation, and a control unit that is provided in the substrate at a predetermined interval from the heat generating semiconductor element and controls the heat generating semiconductor element. A semiconductor device comprising: a semiconductor device, wherein a heat separating unit is provided on a substrate between the control unit and the heat generating semiconductor element. 2. The semiconductor device according to claim 1, wherein a thermal isolation groove is formed in the substrate as the thermal isolation means, and a substance having a low thermal conductivity is put in the thermal isolation groove. apparatus. 3. A substrate, a heat generating semiconductor element which is provided in the substrate and generates heat during operation, and a control unit which is provided in the substrate at a predetermined interval from the heat generating semiconductor element and controls the heat generating semiconductor element. A semiconductor device having a separation region for separating each of the control unit and the heat-generating semiconductor element provided in the substrate at a predetermined interval, wherein the separation region is formed of a substance having a low heat transfer coefficient. A semiconductor device characterized by: 4. A substrate, a heat generating semiconductor element which is provided in the substrate and generates heat during operation, and a control which is provided in the substrate at a predetermined interval from the heat generating semiconductor element and controls the heat generating semiconductor element. And a heat dissipation column connected to the bottom of the substrate for radiating heat from the heat generating semiconductor element to the bottom surface, the heat dissipation column being provided between the control section and the heat generating semiconductor element. And a heat dissipation plate connected to the heat dissipation column and covering the surface of the substrate to evenly dissipate heat from the heat dissipation column to the entire surface of the substrate.