JPH07263577A - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] A semiconductor device provided with a flip-flop circuit formed by cross-connecting complementary inverters, for example,
Regarding an SRAM provided with a CMOS type memory cell,
To enhance the α-ray soft error resistance of the memory cell, expand the formation region of the power supply line, and reduce the area of the memory cell. A contact hole is required to connect the drain of the pMOS transistor 7 (P type diffusion layer 68), the drain of the nMOS transistor 9 (N type diffusion layer 71) and the polysilicon layer 77 to other layers. And the drain (P-type diffusion layer 70) of the pMOS transistor 8 and the nMOS transistor 1 are connected.
0 drain (N-type diffusion layer 73) and polysilicon layer 7
6 with a tungsten layer 81 that does not require contact holes to connect to other layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a flip-flop circuit formed by cross-connecting complementary inverters.

[0002]

2. Description of the Related Art Conventionally, a CM has been used as a semiconductor device of this type.
OS (complementory MOS [metal oxide semiconduct
or]) type memory cells are provided in SRAM (static r
andomaccess memory) is known, and FIG. 9 shows this C
It shows a MOS type memory cell.

In the figure, 1 is a word line for selecting a row, 2,
3 is a bit line forming a data transfer path, 4 is a VDD power supply line for supplying a high-voltage side power supply voltage VDD, and 5 is a VSS power supply line for supplying a low-voltage side power supply voltage VSS.

Further, 6 is a flip-flop circuit,
Reference numerals 7 and 8 are enhancement type pMOS transistors which form load transistors, and 9 and 10 are enhancement type nMOS transistors which form drive transistors.

Further, 11 and 12 are enhancement type nMOSs which form transfer gates whose conduction and non-conduction are controlled by a word line selection signal supplied via the word line 1.
It is a transistor.

FIG. 10 is a schematic plan view showing a conventional configuration example of this CMOS type memory cell.
16 is a P-type diffusion layer, 17-21 is an N-type diffusion layer, 22-2.
Reference numeral 5 is a polysilicon layer, and 26 and 27 are aluminum layers.

28 is a contact portion between the P-type diffusion layer 15 and the VDD power supply line 4 made of aluminum, and 29 is a VSS power supply line 5 made of the N-type diffusion layer 18 and aluminum.
It is a contact part with.

Further, 30 is a contact portion between the P type diffusion layer 14 and the aluminum layer 26, 31 is a contact portion between the P type diffusion layer 16 and the aluminum layer 27, and 32 is a contact portion between the N type diffusion layer 17 and the aluminum layer 26. Contact part, 33 is N
It is a contact portion between the mold diffusion layer 19 and the aluminum layer 27.

Further, 34 is the N-type diffusion layer 20 and the bit line 2.
And a contact portion 35 with the N-type diffusion layer 21 and the bit line 3
With 36, the contact portion 36 with the aluminum layer 26 and the polysilicon 23, and 37 with the aluminum layer 2
7 is a contact portion between the polysilicon layer 22 and the polysilicon layer 22.

FIG. 11 is a schematic sectional view taken along line AA of FIG. 10, in which 40 is a silicon substrate and 4 is a substrate.
1 is a field oxide film, 42 and 43 are gate oxide films, 4
Reference numeral 4 is an insulating film, 45 to 48 are sidewall insulating films, and 49 is an insulating film (SOG [spin on grass] film).

Here, in FIG. 10, the P-type diffusion layer 1 is formed.
The P-type diffusion layer 15 is composed of the polysilicon layer 22 and the polysilicon layer 22.
Is a source, the P-type diffusion layer 14 is a drain, and the polysilicon layer 22 is a gate.

In addition, the P-type diffusion layers 15 and 16 and the polysilicon layer 23 have the P-type diffusion layer 15 as a source, the P-type diffusion layer 16 as a drain, and the polysilicon layer 23 as a gate.
The MOS transistor 8 is configured.

The N-type diffusion layers 17 and 18 and the polysilicon layer 22 have the n-type diffusion layer 17 as a drain, the N-type diffusion layer 18 as a source, and the polysilicon layer 22 as a gate.
The MOS transistor 9 is configured.

In addition, the N-type diffusion layers 18 and 19 and the polysilicon layer 23 have the n-type diffusion layer 19 as a drain, the N-type diffusion layer 18 as a source, and the polysilicon layer 23 as a gate.
The MOS transistor 10 is configured.

Reference numeral 24 is a polysilicon layer forming the word line 1. The N-type diffusion layers 17 and 20 and the polysilicon layer 24 are the N-type diffusion layer 17 as a source and the N-type diffusion layer 2 as a source.
NM with 0 as drain and polysilicon layer 24 as gate
The OS transistor 11 is configured.

The N-type diffusion layers 19 and 21 and the polysilicon layer 24 have the n-type diffusion layer 19 as a source, the N-type diffusion layer 21 as a drain, and the polysilicon layer 24 as a gate.
The MOS transistor 12 is configured.

The polysilicon layer 25 is formed by the word line 1
The word line adjacent to the (polysilicon layer 24) is formed.

In recent years, SRAMs provided with CMOS type memory cells have both high-speed performance surpassing bipolar RAMs and low power consumption. Therefore, high-performance systems such as large-scale computers, workstations, measuring instruments, etc. It is becoming more and more used.

In these high-performance systems, in order to further improve the performance, there is a demand for the SRAM to have higher integration and higher speed. Miniaturization and reduction of power consumption by reduction of information holding current have been achieved.

However, in the CMOS type memory cell, the amount of data holding charge in the nMOS transistors 9 and 10 is small due to the reduction in the capacity of the drains (storage nodes) of the nMOS transistors 9 and 10 and the reduction in power due to miniaturization. Therefore, a soft error due to α (alpha) rays is likely to occur, which is a serious problem in terms of reliability.

This α-ray is emitted by α-decay of uranium (U) and thorium (Th) contained in aluminum or the like which is a packaging material for accommodating an IC or a wiring material for forming an IC. The energy of α rays is
The center is 5 MeV, and it is distributed in 0 to 10 MeV.

When the silicon substrate is irradiated with α rays having energy of 5 MeV, for example, the α rays penetrate to a depth of 30 μm and 1.4 × 10 ⁶ electron-hole pairs are generated. To be done.

In this case, the nMOS transistors 9 and 10
In the region where n is formed, between the drains of the nMOS transistors 9 and 10 and the P well, the generated holes are collected in the P well having a low energy level, and the electrons are nMOS transistors having a high energy level. Will be collected in the drain of.

For this reason, the potential of the drain of the nMOS transistor which holds the H level among the nMOS transistors 9 and 10 which constitute the flip-flop circuit 6 drops to near the potential (VSS) of the P well.

Due to this potential change, of the nMOS transistors 9 and 10 that form the flip-flop circuit 6, the pMOS transistor on the side holding the L level becomes conductive and the nMOS transistor becomes nonconductive, and the stored information is inverted. That is, a so-called α-ray soft error occurs.

Conventionally, as a countermeasure against this α-ray shift error,
The following are being implemented: A material having a low α-ray content is used as a packaging material or wiring material. This is for the purpose of reducing the emission of α rays from the chip component and the inside.

An α-ray shielding film such as a polyimide film is deposited on the chip surface. This is to reduce the penetration of α rays emitted from the outside of the chip into other parts such as other parts.

The memory holding voltage and memory holding current of the memory cell are increased. This is an nMO to hold information.
The purpose is to increase the amount of charge accumulated in the S transistors 9 and 10.

N forming the driving transistor of the memory cell
The capacitance attached to the drains of the MOS transistors 9 and 10 is increased. This is for the purpose of increasing the amount of charges accumulated in the nMOS transistors 9 and 10 to retain information.

Here, it is necessary to completely remove the α-ray emitting substance from the package material and the wiring material which form the chip.
It is virtually impossible, and the measures of are not complete measures.

Further, the measure of depositing an α-ray shielding film such as a polyimide resin on the chip surface is effective for α-rays radiated from the outside of the chip, but is not effective for α-rays emitted from the inside of the chip. Not valid.

Increasing the memory holding voltage and memory holding current of a memory cell leads to an increase in power consumption, but the total power consumption has already reached its limit, and the memory holding is more than the present. The voltage and memory retention current cannot be increased.

As described above, some improvement can be expected in the measures 1 to 7, but it is not complete, and the only complete measure is the drains of the nMOS transistors 9 and 10 forming the drive transistor of the memory cell. This is a measure to increase the capacity.

[0034]

Here, in the conventional CMOS type memory cell shown in FIG. 10, an SOG film for flattening is provided between the aluminum layers 26 and 27 and the polysilicon layers 22 and 23. Although the SOG film 49 is formed, since the thickness of the SOG film 49 is as thick as 3000 angstrom, for example, it is not possible to increase the capacitance of the drains of the nMOS transistors 9 and 10 via the aluminum layers 26 and 27. .

Therefore, the conventional CM shown in FIG.
In the OS type memory cell, it is necessary to increase the area of the drain itself of the nMOS transistors 9 and 10 in order to increase the capacity of the nMOS transistors 9 and 10. There has been a problem that the area of the cell becomes large and high integration cannot be achieved.

In the conventional CMOS type memory cell shown in FIG. 10, the wiring connecting the drain of the pMOS transistor 7, the drain of the nMOS transistor 9 and the polysilicon layer 23, and the pMOS transistor 8 are connected. Since the wiring connecting the drain, the drain of the nMOS transistor 10 and the polysilicon layer 22 is formed by the aluminum layers 26 and 27, the wiring corresponding to that is formed.
There is a problem that the area where the VDD power supply line 4 and the VSS power supply line 5 are formed becomes small.

In the conventional CMOS type memory cell shown in FIG. 10, the aluminum layer 26 is connected to the P type diffusion layer 14, the N type diffusion layer 17 and the polysilicon layer 23, and the aluminum layer 27. And the P-type diffusion layer 1
6. Since contact holes are required for connection with the N-type diffusion layer 19 and the polysilicon layer 22, there is a problem that the area of the memory cell becomes large.

In view of the above point, the present invention is a semiconductor device provided with a flip-flop circuit formed by cross-connecting complementary inverters, which has enhanced α-ray soft error resistance and a power line formation region. It is an object of the present invention to provide a semiconductor device which can be enlarged and the area of a flip-flop circuit can be reduced.

[0039]

FIG. 1 is a diagram for explaining the principle of the present invention, showing a flip-flop circuit provided by the present invention. That is, the semiconductor device of the present invention is configured by providing the flip-flop circuit as shown in FIG.

In the figure, 51 is a VDD power supply line for supplying a high-voltage-side power supply voltage VDD, and 52 is a low-voltage-side power supply voltage VS.
VSS power supply lines for supplying S, 53 and 54 are p-channel field effect transistors forming load transistors, 55 and 5
Reference numeral 6 is an n-channel field effect transistor which is a driving transistor.

Further, 57 is a conductive layer forming the gates of the p-channel field effect transistor 53 and the n-channel field effect transistor 55, and 58 is a p-channel field effect transistor 54 and an n-channel field effect transistor 56.
Is a conductive layer that forms the gate of.

Further, 59 is connected to the drain of the p-channel field effect transistor 53, the drain of the n-channel field effect transistor 55 and the conductive layer 58, and a part 59A is arranged on the conductive layer 57 via an insulating layer. It is a conductive layer.

The conductive layer 59 is connected to the conductive layer 58 without a contact hole.

Reference numeral 60 is connected to the drain of the p-channel field effect transistor 54, the drain of the n-channel field effect transistor 56, and the conductive layer 57, and a portion 60A is disposed on the conductive layer 58 via an insulating layer. It is a conductive layer.

The conductive layer 60 is connected to the conductive layer 57 without a contact hole.

[0046]

In the present invention, since the conductive layer 59 is connected to the conductive layer 58 without passing through the contact hole, the gap between the part 59A of the conductive layer 59 and the conductive layer 57 may be narrow. Therefore, the capacitance formed between the part 59A of the conductive layer 59 and the conductive layer 57 can be increased.

Therefore, it is possible to increase the capacitance attached to the drain of the n-channel field effect transistor 55 forming the driving transistor.

Further, since the conductive layer 60 is connected to the conductive layer 57 without passing through the contact hole, the interval between the part 60A of the conductive layer 60 and the conductive layer 58 can be narrow. A portion 60A of the conductive layer 60 and the conductive layer 5
It is possible to increase the capacity formed between the capacitor 8 and.

Therefore, the capacitance attached to the drain of the n-channel field effect transistor 56 forming the driving transistor can be increased.

As described above, according to the present invention, the capacitance added to the drains of the n-channel field effect transistors 55 and 56 can be increased, so that the α-ray soft error resistance can be enhanced.

When the conductive layers 59 and 60 are opposed to the VDD power supply line 51 and the VSS power supply line 52 via the insulating layer, the conductive layers 59 and 60 and the VDD power supply line 51 are opposed to each other. Since the capacitance between the VSS power supply line 52 and the drain can be added to the drains of the n-channel field effect transistors 55 and 56, the α-ray soft error resistance can be further enhanced.

The conductive layer 59 is connected to the conductive layer 58 without a contact hole, and the conductive layer 60 is connected to the conductive layer 57 without a contact hole. 59 and 60 can be formed below the flattening film.

Therefore, the VDD power supply line 51 and VSS
Since the power supply line 52 can be formed above the conductive layers 59 and 60 via the flattening film, the VDD power supply line 51 can be formed.
The area where the VSS power supply line 52 is formed can be increased.

Similarly, the conductive layer 59 is connected to the conductive layer 58 without passing through a contact hole, and the conductive layer 60 is provided.
Is connected to the conductive layer 57 without passing through the contact hole, the area of the flip-flop circuit can be reduced.

The conductive layer 59 is connected to the drains of the p-channel field effect transistor 53 and the n-channel field effect transistor 55 without passing through the contact hole, and the conductive layer 60 is passed through the contact hole. Without the p-channel field effect transistor 54
When connecting to the drain of the flip-flop circuit and the drain of the n-channel field effect transistor 56, the area of the flip-flop circuit can be further reduced.

The flip-flop circuit provided by the present invention can be used for a complementary memory cell in, for example, an SRAM, and FIG. 2 shows a complementary memory cell using the flip-flop circuit shown in FIG. 2 shows a memory cell of a mold.

In the figure, 61 is the flip-flop circuit shown in FIG. 1, 62 is a word line for selecting a row, 63 and 64 are bit lines forming a data transfer path, and 65 and 66 are word lines 62.
It is an n-channel field effect transistor that forms a transfer gate whose conduction and non-conduction are controlled by a word line selection signal supplied via.

[0058]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
Embodiments to fifth embodiments will be described by taking the case where the present invention is applied to an SRAM provided with CMOS type memory cells as an example.

First Embodiment FIG. 3 and FIG. 4 FIG. 3 is a diagram showing a main part of the first embodiment of the present invention. The planar structure of a CMOS type memory cell provided in the first embodiment of the present invention. Is schematically shown, and the circuit is configured as shown in FIG.

In the figure, 68 to 70 are P type diffusion layers, 71 to 7
5 is an N type diffusion layer, 76 to 79 are polysilicon layers, 80,
Reference numeral 81 is a tungsten (W) layer forming a local wiring which does not require a contact hole for connection with another layer.

Reference numeral 82 is a contact portion between the P type diffusion layer 69 and the VDD power supply line 4 made of an aluminum layer, and 83.
Is a contact portion between the N-type diffusion layer 72 and the VSS power supply line 5 made of aluminum.

Further, 84 is the N-type diffusion layer 74 and the bit line 2.
And a contact portion 85 with the N-type diffusion layer 75 and the bit line 3
It is a contact part with.

Reference numeral 86 denotes a contact portion between the P-type diffusion layer 68 and the tungsten layer 80, which is the tungsten layer 80.
Are directly connected to the P-type diffusion layer 68 without via a contact hole.

Reference numeral 87 denotes a contact portion between the P type diffusion layer 70 and the tungsten layer 81, and the tungsten layer 81
Are directly connected to the P-type diffusion layer 70 without via contact holes.

Numeral 88 is a contact portion between the N type diffusion layer 71 and the tungsten layer 80, and the tungsten layer 80
Are directly connected to the N-type diffusion layer 71 without via a contact hole.

Reference numeral 89 denotes a contact portion between the N-type diffusion layer 73 and the tungsten layer 81, which is the tungsten layer 81.
Are directly connected to the N-type diffusion layer 73 without via contact holes.

Reference numeral 90 denotes a contact portion between the tungsten layer 80 and the polysilicon layer 77, and the tungsten layer 80 is connected to the polysilicon layer 77 via a silicide layer without a contact hole.

Further, reference numeral 91 is a contact portion between the tungsten layer 81 and the polysilicon layer 76, and the tungsten layer 81 is connected to the polysilicon layer 76 via the silicide layer without via a contact hole.

Further, 80A is a portion of the tungsten layer 80 which faces the polysilicon layer 76 via the insulating layer, and 81A is a portion of the tungsten layer 81 which faces the polysilicon layer 77 via the insulating layer. .

FIG. 4 is a schematic sectional view taken along the line BB of FIG. 3, in which 93 is a silicon substrate, 94 is a field oxide film, 95 and 96 are gate oxide films, and 97 is an insulating film. A film, 98 to 101 are sidewall insulating films, 102 is a silicide, and 103 is an insulating film (SOG).

Here, in FIG. 3, the P-type diffusion layer 68,
69 and the polysilicon layer 76, the P-type diffusion layer 69 is the source, the P-type diffusion layer 68 is the drain, and the polysilicon layer 76.
A pMOS transistor 7 having a gate as a gate is formed.

The P-type diffusion layers 69 and 70 and the polysilicon layer 77 have the p-type diffusion layer 69 as a source, the P-type diffusion layer 70 as a drain, and the polysilicon layer 77 as a gate.
The MOS transistor 8 is configured.

Further, the N-type diffusion layers 71 and 72 and the polysilicon layer 76 have the N-type diffusion layer 71 as a drain, the N-type diffusion layer 72 as a source, and the polysilicon layer 76 as a gate.
The MOS transistor 9 is configured.

The N-type diffusion layers 72 and 73 and the polysilicon layer 77 have the n-type diffusion layer 73 as a drain, the N-type diffusion layer 72 as a source, and the polysilicon layer 77 as a gate.
The MOS transistor 10 is configured.

The polysilicon layer 78 constitutes the word line 1, and the N-type diffusion layers 71 and 74 and the polysilicon layer 78 form the N-type diffusion layer 71 as the source and the N-type diffusion layer 74 as the source. The nMOS transistor 11 having the drain and the polysilicon layer 78 as the gate is configured.

Further, the N-type diffusion layers 73 and 75 and the polysilicon layer 78 have the n-type diffusion layer 73 as a source, the N-type diffusion layer 75 as a drain, and the polysilicon layer 78 as a gate.
The MOS transistor 12 is configured.

The polysilicon layer 79 is formed in the word line 1
A word line adjacent to the (polysilicon layer 78) is formed.

Here, in this first embodiment, pM
A drain (P-type diffusion layer 68) of the OS transistor 7,
Drain of nMOS transistor 9 (N type diffusion layer 71)
And the polysilicon layer 77 are connected to each other by a tungsten layer 80 which does not require a contact hole for connection with other layers.

As a result, a part 8 of the tungsten layer 80 is formed.
Since the distance between 0A and the polysilicon layer 76 can be narrow, the capacitance formed between the portion 80A of the tungsten layer 80 and the polysilicon layer 76 is large.

Therefore, the capacity of the drain of the nMOS transistor 9 forming the driving transistor of the flip-flop circuit 6 can be increased.

The drain of the pMOS transistor 8 (P-type diffusion layer 70), the drain of the nMOS transistor 10 (N-type diffusion layer 73) and the polysilicon layer 76 are connected to other layers by contact holes. Are connected by a tungsten layer 81 that does not require

As a result, a part 8 of the tungsten layer 81 is formed.
Since the distance between 1A and the polysilicon layer 77 can be narrow, the capacitance formed between the portion 81A of the tungsten layer 81 and the polysilicon layer 77 is large.

Therefore, the capacity of the drain of the nMOS transistor 10 forming the driving transistor of the flip-flop circuit 6 can be increased.

As described above, according to the first embodiment, n
Since the capacitance added to the drains of the MOS transistors 9 and 10 becomes large, the α-ray soft error resistance can be enhanced.

Further, the tungsten layer 80 includes the drain of the pMOS transistor 7 (P type diffusion layer 68), the drain of the nMOS transistor 9 (N type diffusion layer 71), and the polysilicon layer 77 without the contact hole. The tungsten layer 81 is connected to the drain of the pMOS transistor 8 (P type diffusion layer 70) and the drain of the nMOS transistor 10 (N.
Since the type diffusion layer 73) is connected to the polysilicon layer 76, these tungsten layers 80 and 81 are
It can be formed below the G film 103.

Therefore, the VDD power supply line 4 and the VSS power supply line 5 are connected to the tungsten layer 80 through the SOG film 103,
Since it can be formed above 81, these VDD
The area where the power supply line 4 and the VSS power supply line 5 are formed can be enlarged.

The tungsten layer 80, the drain of the pMOS transistor 7 (P type diffusion layer 68), the nMOS
Connection between the drain (N-type diffusion layer 71) of the transistor 9 and the polysilicon layer 77, and the tungsten layer 81
And the drain of the pMOS transistor 8 (P-type diffusion layer 7
0), a contact hole is not required for connection with the drain (N-type diffusion layer 73) of the nMOS transistor 10 and the polysilicon layer 76, so that the area of the memory cell can be reduced.

Second Embodiment FIG. 5 FIG. 5 is a diagram showing a main part of a second embodiment of the present invention, and schematically shows a planar structure of a CMOS type memory cell provided in the second embodiment of the present invention. And the circuit is configured as shown in FIG.

The CMOS type memory cell provided in the second embodiment has polysilicon layers 76 and 77 with wide portions 76A,
77A, and the tungsten layer 80 is the polysilicon layer 7
6 is a widened portion 81A facing the polysilicon layer 77 and a portion 80A facing the polysilicon layer 77, and the other portions are similar to the CMOS type memory cell provided in the first embodiment shown in FIG. It was done.

According to the second embodiment, the capacitance formed between the portion 80A of the tungsten layer 80 and the polysilicon layer 76 and the portion 81A of the tungsten layer 81.
The capacitance formed between the polysilicon layer 77 and the
It is larger than that of the embodiment.

Therefore, according to the second embodiment, the nMO forming the driving transistor of the flip-flop circuit 6 is formed.
Since the capacitance attached to the drains of the S transistors 9 and 10 can be made larger than that in the first embodiment, the α-ray soft error resistance can be enhanced more than that in the first embodiment, and the VDD power supply line can be provided. 4 and the VSS power supply line 5 can be enlarged and the area of the memory cell can be reduced.

Third Embodiment FIG. 6 FIG. 6 is a diagram showing a main part of the third embodiment of the present invention, and schematically shows a planar structure of a CMOS type memory cell provided in the third embodiment of the present invention. And the circuit is configured as shown in FIG.

In the figure, 105 to 108 are P-type diffusion layers and 10
Reference numerals 9 to 114 are N-type diffusion layers, 115 to 118 are polysilicon layers, and 119 and 120 are tungsten layers forming local wiring.

Reference numeral 121 denotes a contact portion between the P type diffusion layer 105 and the VDD power supply line 4 made of an aluminum layer,
122 is a V formed of a P-type diffusion layer 108 and an aluminum layer.
It is a contact portion with the DD power supply line 4.

Reference numeral 123 is a contact portion between the N-type diffusion layer 109 and the VSS power supply line 5 made of aluminum.
Reference numeral 4 is a contact portion between the N-type diffusion layer 114 and the VSS power supply line 5 made of aluminum.

Further, 125 is a contact portion between the N-type diffusion layer 111 and the bit line 2, and 126 is a contact portion between the N-type diffusion layer 112 and the bit line 3.

Reference numeral 127 denotes a contact portion between the P-type diffusion layer 106 and the tungsten layer 119, and the tungsten layer 119 is directly contacted with P without passing through a contact hole.
It is connected to the mold diffusion layer 106.

Further, reference numeral 128 denotes a contact portion between the P type diffusion layer 107 and the tungsten layer 120, and the tungsten layer 128 is directly connected to the P layer without passing through a contact hole.
It is connected to the mold diffusion layer 107.

Reference numeral 129 is a contact portion between the N-type diffusion layer 110 and the tungsten layer 119, and the tungsten layer 119 is directly connected to the N layer without passing through a contact hole.
It is connected to the mold diffusion layer 110.

Reference numeral 130 denotes a contact portion between the N type diffusion layer 113 and the tungsten layer 120, and the tungsten layer 120 is directly connected to the N layer without passing through a contact hole.
It is connected to the mold diffusion layer 113.

Reference numeral 131 denotes a contact portion between the tungsten layer 119 and the polysilicon layer 116, and the tungsten layer 119 is connected to the polysilicon layer 116 via a silicide without a contact hole.

Reference numeral 132 denotes a contact portion between the tungsten layer 120 and the polysilicon layer 115, and the tungsten layer 120 is connected to the polysilicon layer 115 via a silicide without a contact hole.

Further, 115A is a wide portion of the polysilicon layer 115, 116A is a wide portion of the polysilicon layer 116, and 1A.
Reference numeral 19A denotes a portion of the tungsten layer 119 that faces the polysilicon layer 115 via the insulating layer, and 120A denotes a portion of the tungsten layer 120 that faces the polysilicon layer 116 via the insulating layer.

Here, the P-type diffusion layers 105 and 106 and the polysilicon layer 115 are used as the source of the P-type diffusion layer 105.
A pMOS transistor 7 having the P-type diffusion layer 106 as a drain and the polysilicon layer 115 as a gate is configured.

In addition, the P-type diffusion layers 107 and 108 and the polysilicon layer 116 form the P-type diffusion layer 108 as a source and P-type diffusion layer 108.
A pMOS transistor 8 having the type diffusion layer 107 as a drain and the polysilicon layer 116 as a gate is configured.

Further, the N-type diffusion layers 109 and 110 and the polysilicon layer 115 are used to drain the N-type diffusion layer 110,
An nMOS transistor 9 having the N-type diffusion layer 109 as a source and the polysilicon layer 115 as a gate is configured.

Further, the N-type diffusion layers 113 and 114 and the polysilicon layer 116 form the drain of the N-type diffusion layer 113,
The nMOS transistor 10 having the N-type diffusion layer 114 as a source and the polysilicon layer 116 as a gate is configured.

Further, the polysilicon layer 117 is the word line 1
And the N-type diffusion layers 110 and 111,
With the polysilicon layer 117, the N-type diffusion layer 110 is the source, the N-type diffusion layer 111 is the drain, and the polysilicon layer 11
An nMOS transistor 11 having a gate 7 is formed.

In addition, the N-type diffusion layers 112 and 113 and the polysilicon layer 117 form the drain of the N-type diffusion layer 112,
The nMOS transistor 12 having the N-type diffusion layer 113 as a source and the polysilicon layer 117 as a gate is configured.

The polysilicon layer 118 constitutes a word line adjacent to the word line 1 (polysilicon layer 117).

Here, in the third embodiment, pM
Drain of OS transistor 7 (P-type diffusion layer 106)
And the drain of the nMOS transistor 9 (N-type diffusion layer 1
10) and the polysilicon layer 116 are tungsten layers 1 that do not require contact holes for connection with other layers.
Connected at 19.

As a result, the interval between the portion 119A of the tungsten layer 119 and the polysilicon layer 115 can be made narrow, so that the capacitance formed between the portion 119A of the tungsten layer 119 and the polysilicon layer 115 is small. It will be big.

Therefore, the capacitance attached to the drain (N-type diffusion layer 110) of the nMOS transistor 9 forming the driving transistor of the flip-flop circuit 6 can be increased.

The drain of the pMOS transistor 8 (P-type diffusion layer 107), the drain of the nMOS transistor 10 (N-type diffusion layer 113), and the polysilicon layer 11 are also included.
5 is connected by a tungsten layer 120 which does not require a contact hole for connection with other layers.

As a result, the interval between the portion 120A of the tungsten layer 120 and the polysilicon layer 116 can be made narrow, so that the capacitance formed between the portion 120A of the tungsten layer 120 and the polysilicon layer 116 is small. It will be big.

Therefore, it is possible to increase the capacity of the drain (N-type diffusion layer 113) of the nMOS transistor 10 which forms the driving transistor of the flip-flop circuit 6.

As described above, according to the third embodiment, n
Drains of the MOS transistors 9 and 10 (N type diffusion layer 1
Since the capacity added to 10, 113) becomes large, α
Line soft error resistance can be enhanced.

Moreover, according to the third embodiment, since the wide portions 115A and 116A are provided in the polysilicon layers 115 and 116, the drains (N-type diffusion layers 110 and 113) of the nMOS transistors 9 and 10 are formed. The capacity to be added can be made larger than that in the first embodiment, and the α-ray soft error resistance can be strengthened to that extent as compared with the case in the first embodiment.

Further, the tungsten layer 119 does not go through a contact hole, and the drain of the pMOS transistor 7 (P type diffusion layer 106), the drain of the nMOS transistor 9 (N type diffusion layer 110) and the polysilicon layer 11 are formed.
6, the tungsten layer 120 does not go through a contact hole, and the drain of the pMOS transistor 8 (P type diffusion layer 107), the drain of the nMOS transistor 10 (N type diffusion layer 113), and the polysilicon layer 11 are connected.
5, the tungsten layers 119 and 120 can be formed below the flattening film.

Therefore, the VDD power supply line 4 and the VSS power supply line 5 are connected to the tungsten layers 119 and 12 through the flattening film.
Since it can be formed above 0, the region where these VDD power supply line 4 and VSS power supply line 5 are formed can be enlarged.

In addition, the tungsten layer 119 and the pMOS
Drain of transistor 7 (P-type diffusion layer 106), nM
Connection between the drain of the OS transistor 9 (N-type diffusion layer 110) and the polysilicon layer 116, the tungsten layer 120, the drain of the pMOS transistor 8 (P-type diffusion layer 107), and the drain of the nMOS transistor 10 (N-type diffusion). Since contact holes are not required for the connection with the layer 113) and the polysilicon layer 115, the area of the memory cell can be reduced.

Fourth Embodiment FIG. 7 FIG. 7 is a diagram showing an essential part of the fourth embodiment of the present invention, and schematically shows a planar structure of a CMOS type memory cell provided in the fourth embodiment of the present invention. And the circuit is configured as shown in FIG.

In this CMOS type memory cell, a hole 76B is provided in the wide portion 76A of the polysilicon layer 76 so that the tungsten layer 80 faces the side wall of the polysilicon layer 76 and the width of the polysilicon layer 77 is wide. Part 77A
A hole portion 77B is provided in the same so that the tungsten layer 81 faces the side wall of the polysilicon layer 77, and the other portions are the same as those of the CMOS type memory cell provided in the second embodiment shown in FIG. .

Also according to the fourth embodiment, the capacitances attached to the drains of the nMOS transistors 9 and 10 forming the driving transistors of the flip-flop circuit 6 can be made larger than in the case of the first embodiment. The resistance can be enhanced as compared with the case of the first embodiment, and the region where the VDD power supply line 4 and the VSS power supply line 5 are formed can be enlarged and the area of the memory cell can be reduced.

Instead of the holes 76B and 77B, a gap may be provided, or the holes 76B and 7B.
A gap may be provided together with 7B.

Fifth Embodiment FIG. 8 FIG. 8 is a diagram showing a main part of the fifth embodiment of the present invention, and schematically shows a planar structure of a CMOS type memory cell provided in the fifth embodiment of the present invention. And the circuit is configured as shown in FIG.

In this CMOS type memory cell, holes 115B and 115 are formed in the wide portion 115A of the polysilicon layer 115.
C is provided, and the tungsten layer 119 is the polysilicon layer 11
5, the wide portion 116A of the polysilicon layer 116 is provided with holes 116B and 116C so that the tungsten layer 120 also faces the side wall of the polysilicon layer 116. The third embodiment has the same structure as the CMOS type memory cell provided in the third embodiment.

Also in the fifth embodiment, the capacitances attached to the drains of the nMOS transistors 9 and 10 forming the driving transistors of the flip-flop circuit 6 can be made larger than in the first embodiment, so that the α ray soft error occurs. Of the power supply line 4 and the VSS power supply line 5 and the area of the memory cell can be reduced.

A gap may be provided instead of the holes 115B and 116B, and the holes 11 may be formed.
A gap may be provided together with 5B and 116B.

[0130]

According to the present invention, the conductivity connecting the drain of the p-channel field effect transistor forming one load transistor and the drain of the n-channel field effect transistor forming one driving transistor, which constitutes the flip-flop circuit. As the layer, a conductive layer which does not require a contact hole for connection with the conductive layer forming the gate of the other p-channel field effect transistor and the other n-channel field effect transistor is used, and the p-channel forming the other load transistor As a conductive layer that connects the drain of the field-effect transistor and the drain of the n-channel field-effect transistor that forms the other driving transistor, a conductive layer that forms the gate of one p-channel field-effect transistor and one n-channel field-effect transistor To connect By using a conductive layer that does not require a hole and a hole, the capacitance added to the drains (storage nodes) of one and the other n-channel field effect transistors can be increased, so that the α-ray soft error resistance can be improved. In addition to the enhancement, it is possible to increase the area for forming the power supply line and reduce the area of the flip-flop circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention (a diagram showing a flip-flop circuit provided by the present invention).

FIG. 2 is a diagram showing a complementary memory cell using the flip-flop circuit shown in FIG.

FIG. 3 is a diagram showing a main part of the first embodiment of the present invention (planar structure of a CMOS type memory cell provided in the first embodiment of the present invention).

FIG. 4 is a schematic cross-sectional view taken along the line BB of FIG.

FIG. 5 is a diagram showing a main part of a second embodiment of the present invention (planar structure of a CMOS type memory cell provided in the second embodiment of the present invention).

FIG. 6 is a diagram showing a main part of a third embodiment of the present invention (planar structure of a CMOS type memory cell provided in the third embodiment of the present invention).

FIG. 7 is a diagram showing a main part of a fourth embodiment of the present invention (planar structure of a CMOS type memory cell provided in the fourth embodiment of the present invention).

FIG. 8 is a diagram showing a main part of a fifth embodiment of the present invention (planar structure of a CMOS type memory cell provided in the fifth embodiment of the present invention).

FIG. 9 is a circuit diagram showing a CMOS type memory cell.

FIG. 10 is a schematic plan view showing a conventional configuration example of a CMOS type memory cell.

11 is a schematic cross-sectional view taken along the line AA of FIG.

[Explanation of symbols]

 (FIG. 1) 51 VDD power supply line 52 VSS power supply line 53, 54 p-channel field effect transistor 55, 56 n-channel field effect transistor 57-60 conductive layer (FIG. 2) 61 flip-flop circuit 62 shown in FIG. 1 word line 63, 64-bit line 65, 66 n-channel field effect transistor

Claims (9)

[Claims] 1. A first p-channel field effect having a source connected to a first power supply line (51) supplied with a first power supply voltage (VDD) and having a first conductive layer (57) as a gate. A transistor (53) and a source are connected to a second power supply line (52) to which a second power supply voltage (VSS) is supplied, and the first conductive layer (57).
A first n-channel field effect transistor (55) having a gate as a gate, and a second p-channel electric field having a source connected to the first power supply line (51) and a second conductive layer (58) as a gate. An effect transistor (54), a second n-channel field effect transistor (56) having a source connected to the second power supply line (52) and having the second conductive layer (58) as a gate, Has its end connected to the drain of the first p-channel field effect transistor (53) and has a second end connected to the drain of the first n-channel field effect transistor (55) and a third end. Part is connected to the second conductive layer (58) without passing through a contact hole, and a part (5
9A) has a third conductive layer (59) disposed on the first conductive layer (57) via an insulating layer, and a first end portion of the second p-channel field effect transistor (54). Of the first n-channel field effect transistor (56) with a second end connected to the drain of the first n-channel field effect transistor (56) and a third end connected to the first conductive layer (without a contact hole). 57) and a part (6
0A) is provided with a fourth conductive layer (60) arranged on the second conductive layer (58) via an insulating layer. 2. The third conductive layer (59) has its first end connected to the drain of the first p-channel field effect transistor (53) without passing through a contact hole, Has an end connected to the drain of the first n-channel field effect transistor (55) without a contact hole, and the fourth conductive layer (60) has a first end connected to the contact hole. Connected to the drain of the second p-channel field effect transistor (54) without intervention, and the second end connected to the drain of the second n-channel field effect transistor (56) without intervention of a contact hole. The semiconductor device according to claim 1, wherein the semiconductor device is provided. 3. The third and fourth conductive layers (59, 60)
3. The semiconductor device according to claim 1, wherein the first power line and the second power line are opposed to each other via an insulating layer. 4. A portion of the first conductive layer (57) facing the third conductive layer (59) is widened, and the second conductive layer (58) is formed of the wide portion. The semiconductor device according to claim 1, 2 or 3, wherein a portion facing the fourth conductive layer (60) is a wide portion. 5. The first conductive layer (57) is provided with a hole portion in the wide portion, and is configured to face the third conductive layer (59) through the hole portion. At the same time, the second conductive layer (58) is configured such that a hole is provided in the wide portion and the second conductive layer (58) faces the fourth conductive layer (60) also through the hole. The semiconductor device according to claim 4. 6. The first conductive layer (57) is configured such that a gap is provided in the wide portion, and the first conductive layer (57) faces the third conductive layer (59) through this gap as well. The second conductive layer (58) is configured such that a gap is provided in the wide portion and the second conductive layer (58) faces the fourth conductive layer (60) even with the gap. 4 or 5
The semiconductor device described. 7. The first and second conductive layers (57, 58)
Is formed on the plane inside the third and fourth conductive layers (59, 60).
The semiconductor device according to 3, 4, 5 or 6. 8. The first and second conductive layers (57, 58)
Is formed on the outer side of the third and fourth conductive layers (59, 60) in a plane.
The semiconductor device according to 3, 4, 5 or 6. 9. The drain is connected to the first bit line (63), the source is connected to the drain of the first n-channel field effect transistor (55), and the gate is connected to the word line (62). A third n-channel field effect transistor (65), a drain connected to the second bit line (64) and a source connected to the second n-channel field effect transistor (56)
Connected to the drain of the gate and the gate of the word line (62)
And a fourth n-channel field effect transistor (66) connected to the.
The semiconductor device according to 2, 3, 4, 5, 6, 7 or 8.