JPH07262257A - Layout verification device - Google Patents

Abstract

PURPOSE:To provide a layout verification device which takes out only necessary parasitic capacity and executes simulation in a short time. CONSTITUTION:The device is provided with a discrimination means 12 executing circuit simulation by using respective net lists which do not include parasitic capacity extracted from layout pattern data 7 of a semiconductor integrated circuit and discriminating respective wirings on layout pattern data 7 into those where AC signals flow and those where DC signals flow, a retrieval means 16 retrieving the respective coordinates of the intersection points of the respective wirings and parts where the wirings are arranged in parallel by using layout pattern data 7 and the respective discriminated DC and AC wirings, a parasitic capacity extraction means 18 extracting respective parasitic capacities from the respective coordinates of the intersection points of the respective wirings and the parts where the wirings are arranged in parallel and a circuit simulator 20 executing circuit simulation by including the respective parasitic capacities extracted on the respective net lists.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout verification device for verifying characteristics of a semiconductor integrated circuit by circuit simulation.

[0002]

2. Description of the Related Art FIG. 26 is a block diagram showing the structure of a conventional layout verification apparatus. Reference numeral 1 is circuit diagram data of a semiconductor integrated circuit, 2 is layout pattern data of the semiconductor integrated circuit, 3 is a net list extracting means for extracting each net list from the circuit diagram data 1 or the layout pattern data 2, and 4 is this net list extracting means. Circuit simulators 5 and 6 for performing circuit simulation of the respective netlists extracted by 3 are result display means (for example, a display) for displaying respective verification results of this circuit simulation and a result list.

Next, the operation of the conventional layout verifying apparatus configured as described above will be described. First, the circuit diagram data 1 and the layout pattern data 2 are input from the semiconductor integrated circuit, and the netlist extracting means 3 extracts each element from the circuit diagram data 1 to create each netlist, or the layout pattern data. Each element and all the parasitic elements (resistance, capacitance) are extracted from 2 (a netlist that does not include a parasitic element is also possible, and the one that does not include a parasitic element is a netlist extracted from the circuit diagram data 1). It will be the same.), And create each netlist based on it. Next, each netlist is subjected to circuit simulation by the circuit simulator 4, and each result is output to the result display means 5 and the result list 6.

[0004]

The conventional layout verification apparatus is constructed as described above, and when a simulation is performed by creating a netlist containing no parasitic elements from the circuit diagram data 1, the simulation result is different from the actual value. In order to bring the result of the simulation close to the actual value, it is necessary to perform the simulation including each element and all the parasitic elements from the layout pattern data 2, which results in the simulation of an enormous number of elements. Therefore, there is a problem that the simulation takes a long time.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a layout verification apparatus for performing a simulation of extracting only necessary parasitic elements and performing the simulation in a short time. .

[0006]

A layout verifying apparatus according to claim 1 of the present invention comprises netlist extracting means for extracting each netlist containing no parasitic element from layout pattern data or circuit diagram data of a semiconductor integrated circuit, A circuit for simulating the extracted netlists to distinguish each wiring on the layout pattern data into one in which an AC signal flows and one in which a DC signal flows, and the layout pattern data and the distinguished DC and AC. Search means for searching each coordinate of each wiring intersection point and parallel portion using each wiring, and parasitic element extraction means for extracting each parasitic element from each coordinate of the searched wiring intersection point and parallel portion, Circuit simulation is performed by including each parasitic element extracted in the above in each netlist. It is obtained by a verification means for verifying.

A layout verifying apparatus according to a second aspect of the present invention is the layout verifying apparatus according to the first aspect, wherein the selecting means and the distinguishing means select each wiring having a parasitic element that needs to be extracted from each wiring of the semiconductor integrated circuit. The extraction means is provided for extracting only the wiring selected by the selection means from the wirings distinguished by.

A layout verification apparatus according to a third aspect of the present invention is the layout verification apparatus according to the first aspect, further comprising first net number extraction means for extracting a net number of a desired output point from each net list that does not include a parasitic element, Second net number extraction means for extracting a net number of a desired output point from each netlist including each parasitic element, and a first net number in the result of the circuit simulation of each netlist including no parasitic element Comparing means for comparing the result of the net number extracted by the extracting means with the result of the net number extracted by the second net number extracting means of the circuit simulation results of the netlists including the parasitic elements; It is equipped with.

[0009]

The parasitic element extracting means of the layout verifying device according to the first aspect of the present invention extracts each parasitic element from the intersection of each wiring and each coordinate of the parallel portion.

Further, the layout verifying apparatus according to the second aspect of the present invention selects each wiring having a parasitic element that needs to be extracted from each wiring of the semiconductor integrated circuit, and selects the wiring among the wirings distinguished by the distinguishing means. Only the wiring selected by is extracted.

Further, the comparison means of the layout verification apparatus according to the third aspect of the present invention obtains the result of the circuit simulation of the netlist not including each parasitic element and the result of the circuit simulation of each netlist including each parasitic element. Compare.

[0012]

【Example】

Example 1. Hereinafter, a method of mainly extracting the parasitic capacitance among the parasitic elements according to the embodiments of the present invention will be described with reference to the drawings. 1 is a block diagram showing the configuration of a layout verification apparatus according to a first embodiment of the present invention. In the figure, 7 is a layout pattern data of a semiconductor integrated circuit, 8 is a netlist extraction means for extracting each netlist from the layout pattern data 7 in which parasitic capacitance is not taken into consideration to create a netlist file 9, 10 is a netlist file 9 It is a circuit simulator that performs a circuit simulation by using each netlist that does not include the parasitic capacitance of (1) and creates a simulation result file 11 (hereinafter abbreviated as result file 11).

Reference numeral 12 is an alternating current (hereinafter referred to as AC) / direct current (hereinafter D) using the simulation result of the result file 11.
AC for distinguishing signals (referred to as C) and creating an AC / DC signal distinction file 13 (hereinafter abbreviated as distinction file 13)
.DC signal distinguishing means (hereinafter abbreviated as distinguishing means), 14
Extracts the fluctuation range of the amplitude of each AC signal by using the simulation result of the result file 11 and each AC signal of the discrimination file 13 to obtain the AC / DC signal and the maximum value of the AC signal.
It is a fluctuation range extraction means (hereinafter referred to as fluctuation range extraction means 14) of the AC signal for creating a minimum value distinction file 15 (hereinafter referred to as distinction file 15).

Reference numeral 16 uses the distinction file 15 and the layout pattern data 7 to search for each intersecting point (hereinafter referred to as a cross) between the AC signal wiring and the DC signal wiring and the coordinates of each parallel portion. Cross / parallel coordinate data 1
Cross that creates 7 (hereinafter abbreviated as coordinate data 17)
Parallel coordinate search means (hereinafter abbreviated as search means 16). By performing the search means 16 in this manner, not all parasitic capacitance is taken out, but the crossed / parallel portions of the wirings that are considered to affect the simulation. It is possible to limit the existing parasitic capacitances, and here, of these parasitic capacitances, the DC that has the greatest effect on the simulation.
DC wiring and A that have parasitic capacitance that affects wiring
Only cross and parallel with C wiring are searched. Reference numeral 18 is a parasitic capacitance extracting means for extracting each parasitic capacitance using the coordinate data 17 and the distinction file 15 and adding each parasitic capacitance to the netlist file 9 to create a parasitic capacitance addition netlist file 19. To parasitic capacitance extraction means 1
8 is performed, so that between the DC wiring and the DC wiring and the AC
It does not include the parasitic capacitance generated in the cross-parallel portion between the wiring and the AC wiring. A circuit simulator 20 performs a circuit simulation using the parasitic capacitance addition netlist of the parasitic capacitance addition netlist file 19 and shows the verification result in the result display means 21 and the result list 22 (this is the same as the circuit simulator 10). Is.

Next, the operation of the layout verifying apparatus of the first embodiment constructed as described above will be described with reference to the flowcharts of FIGS. First, the layout pattern data 7 is input from the semiconductor integrated circuit,
The netlist extracting means 8 extracts each element that does not include parasitic capacitance from the layout pattern data 7, and performs TRAN analysis (transient analysis) on the basis of the extracted elements to extract each netlist. For example, a net as shown in FIG. The list file 9 is created. Although the example of extracting the netlist not including the parasitic capacitance from the layout pattern data 7 is shown here, the netlist may be extracted from the circuit diagram data. Next, circuit simulation is performed by the circuit simulator 10 using each netlist that does not include this parasitic capacitance, and a result file 11 is created, for example, as shown in FIG.

Next, the operation of the discriminating means using the simulation result will be described with reference to the flowchart of FIG. 2 by taking the result file 11 of FIG. 9 as an example. First, data for each net (signal line) is extracted from the simulation result (step S1). This is data for each of the nets V (1), V (2), V (3) ... Shown in FIG. Next, the data for each time is extracted from the data of one net (step S2). Then, the amount of change is obtained by comparing with the data at the immediately preceding time (step S3). This is, for example, time 2.000E- of the net V (1) in FIG.
The value of 0.7 is 5.000 and the previous time is 1.000E-
The value of 0.7 is compared with 5.000 to obtain the amount of change.

As a result, for example, when the amount of change is less than 1%, 1 is added to the DC flag (step S
4) Also, if the amount of change is 1% or more, the AC flag is set to 1
Is added (step S5). Then, this is repeated until the end of the analysis time of the net (step S
6). When the analysis time ends, the numbers of the AC flag and the DC flag are compared (step S
7). As a result, if the number of DC flags is larger than the number of AC flags, it is determined to be a DC signal, and it is entered in the discrimination file 13 as a DC signal (step S8). If the number of AC flags is larger than the number, it is determined to be an AC signal, and it is entered in the discrimination file 13 as an AC signal (step S9).

Then, the above operation is repeated for each net to judge all the nets and to create the discrimination file 13 as shown in FIG. 10, for example. As shown in FIG. 10, the nets V (1) and V (4) in FIG. 9 have a small change, and therefore the DC signals are distinguished from the nets V (2) and V (3), and thus the AC signals are distinguished from each other. ing.

Next, the operation of the fluctuation range extracting means 14 using the discrimination file 13 and the result file 11 will be described with reference to FIG.
A description will be given based on the flowchart. First, each net of each AC signal is extracted from the discrimination file 13 (step S11). Then, each data of these extracted nets is extracted from the result file 11 (step S1).
2). Next, the maximum value / minimum value of the fluctuation range is extracted from each of the data (step S13) and additionally entered in the distinction file 13 (step S14) to create a distinction file 15 as shown in FIG. 11, for example.

Next, the operation of the search means 16 which is performed using the discrimination file 15 and the layout pattern data 7 will be described with reference to the flowcharts of FIGS. 4, 5 and 6. First, each DC signal and each AC from the distinction file 15
Input the signal that includes the maximum and minimum values to each AC
The signals are input again in the order of those having the largest difference between the maximum value and the minimum value (step S15). As described above, arranging the AC signals in descending order of the maximum value / minimum value difference means arranging them in the order of the signals that affect other AC signals. Therefore, determine the range of impact that the user needs to investigate,
You can retrieve only that signal and proceed to the next step. Then, from the layout pattern data 7, for example, the wiring coordinates and net numbers are extracted for each of the wiring layers AL1, AL2 ... As shown in FIG. 12 (step S1).
6).

Then, the wiring having the DC signal is searched for under the condition that the net numbers of the DC wirings match (step S17). For example, since the net numbers in FIG. 12 that match the net number of the DC signal in FIG. 11 are 4 and 11, these coordinates are searched for as the DC wiring. Next, a wire having an AC signal, that is, an AC wire is searched for under the condition that the net numbers match (step S18). For example, since the net numbers in FIG. 12 that match the net numbers of the AC signal in FIG. 11 are 2, 3, 8, and 10, these coordinates are A.
It is searched for the C wiring. Next, the coordinates of the DC wiring are extracted (step S19), and it is determined which coordinate of the cross / parallel portion existing between the DC wiring and the AC wiring is to be checked (step S20).

First, in the case of checking the coordinates of the cross existing between the DC wiring and the AC wiring, the coordinates of the extracted AC wiring are extracted from the coordinate file of FIG. 12 (step S21), then Among the coordinates of the DC wiring, the one having the smallest coordinate width is obtained, and all the coordinates of the DC wiring and the AC wiring are divided at intervals of the minimum width. Then, it is judged whether or not the coordinates of the AC wirings are the same as the coordinates of the DC wirings or within the range of the division where the coordinates of the DC wirings exist (step S22). The coordinates of the wiring are input to the file as the cross coordinates (step S23). Then, the above operation is repeated for each DC wiring to extract all the cross coordinates.

Next, when the coordinates of the parallel portion existing between the DC wiring and the AC wiring are examined, the coordinates of the DC wiring are searched for each bend (step S24). FIG. 13 shows, for example, the coordinates of the net number 4 of the DC wiring shown in FIG. 12, which shows the data A, B, C, and D of each rectangle divided for each coordinate. Then, it is determined whether or not the AC wiring is present within several μm (the value can be specified by the user) on the long side of the length of the XY coordinates of the retrieved DC wiring (step S25). , For example, AL1 ((40.5 9.0) (4 of the rectangular data D of the DC wiring as shown in FIG.
8.5 31.5) When searching for AC wiring that is in parallel with 4), first determine which of the X coordinate and Y coordinate of this coordinate is wider, and in this coordinate, the Y coordinate has a larger distance. Since it is wide, it can be seen that this DC wiring exists long in the vertical direction.

From this, it is searched whether or not there is an AC wiring within a few μm from the X coordinate value (within a range set by the user at a width equal to or larger than the minimum spacing between wirings), and whether or not it is parallel. To judge. For example, a search is performed from FIG. 12 based on the net number of the AC wiring, and as shown in FIG. 13, the coordinate EAL2 ((53.0 5.0) (61.0 25.
It is confirmed that 0) and 8) are arranged in parallel. The data thus obtained is input to the file as parallel coordinates (step S26), and, for example, coordinate data 17 as shown in FIG. 14 is created.

Next, the operation of the parasitic capacitance extracting means 18 using the coordinate data 17 and the netlist file 9 will be described with reference to the flowchart of FIG. First, the coordinates of the crossed / parallel portion are input from the coordinate data 17 (step S27), and the area of the cross and the length of the parallel portion are obtained (step S28). The cross area referred to here is, for example, in the first data of #cross of FIG. 14, the wiring widths of AL1 and AL2 are AL3 and AL3 is | 3.
1.5-39.5 | = 8, AL2 is | 30.0-38.
0 | = 8, and the product 64 of these is obtained as the area of the cross, and the length of the parallel portion is, for example, #pa in FIG.
In the first data of the rallell, the width of the X coordinate of the coordinate of the net number 4 of the DC signal is | 40.5-48.5 | = 8,
The width of the Y coordinate is | 9.0-31.5 | = 22.5, so Y
It is considered that the width of the coordinate becomes longer and the coordinate becomes parallel on the Y coordinate side. When the overlapping portion of the Y coordinate of AL1 and AL2 is taken, it becomes 9.0 to 25.0, and the length is | 9.0- 25.
0 | = 16.0, and the distance between these wirings is | 48.5-53.0 | = 4.5. Then, the parasitic capacitance value is obtained from the respective data and the empirical value as shown in FIG.

Next, the obtained parasitic capacitance values are added to the netlist of the netlist file 9 (step S29), and the parasitic capacitance addition netlist file 19 as shown in FIG. 16 is formed, for example. Next, the parasitic capacitance added netlist file 19 is subjected to circuit simulation again by the circuit simulator 20, and the result is output to the result display means 21 and the result list 22.

As described above, according to the first embodiment, the simulation for extracting only the necessary parasitic capacitance, that is, the parasitic capacitance that affects the DC wiring is performed. Therefore, a highly accurate simulation can be performed in a short time. It is possible to confirm the influence of the signal between the wirings.

Example 2. In the first embodiment, as the parasitic capacitance to be particularly considered in the simulation, an example of extracting only the parasitic capacitance of the cross-parallel portion between the DC wiring and the AC wiring and performing the simulation is shown, but the present invention is not limited to this. As the parasitic capacitance to be considered in the simulation, the parasitic capacitances in the cross / parallel portions between the DC wiring and the AC wiring and between the AC wiring and the AC wiring are extracted and the simulation is performed. Good. Even in this case, the parasitic capacitance existing in other than the cross / parallel portion of each wiring that does not affect the simulation and the parasitic capacitance existing in the cross / parallel portion between the DC wiring and the DC wiring should be omitted. Therefore, the parasitic capacitance is reduced as compared with the conventional case, and the simulation can be performed in a short time.

Example 3. FIG. 17 is a diagram showing a flowchart of the layout verification apparatus according to the third embodiment of the present invention.
In the figure, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. Reference numeral 23 is a menu showing each signal line of the semiconductor integrated circuit.

Next, the operation of the layout verifying apparatus of the third embodiment will be described with reference to the first embodiment. First, each wiring having a parasitic capacitance that the user needs to verify is selected from the menu 23 (step S30). Next, the discrimination file 15 obtained in the same manner as in the first embodiment is input (step S31), and the AC signals among them are rearranged in the descending order of the difference between the maximum value and the minimum value. Then, only the data of each wiring selected in step S30 is extracted from the distinction file 15 (step S32).

Next, the layout pattern 7 obtained in the same manner as in the first embodiment is input (step S33), and the wiring coordinates and net number are extracted. Then, based on the data extracted so far, the same operation as that of the above-described first embodiment is performed, and the coordinate search of the cross / parallel portion is performed (step S34). And the coordinates of the crossed and parallel parts, A
The parasitic capacitance only between the wirings selected from the menu 23 is calculated from the fluctuation range of the C signal and the empirical value (step S3).
5) Input the netlist file 9 obtained as in the first embodiment (step S36). Then, a parasitic capacitance is added to this netlist to add the circuit simulator 2
0, circuit simulation is performed, and the result is output to the result display means 21 and the result list 22.

As described above, according to the third embodiment, only the parasitic capacitance to be extracted can be extracted and simulated.

Example 4. FIG. 18 is a diagram showing the configuration of the layout verification apparatus according to the fourth embodiment of the present invention. In the figure, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. 24 is the first to extract the net number of the output point from the net list file 9 that does not include parasitic capacitance
, A second net number extracting means 25 for extracting the net number of the same output point from the parasitic capacitance addition net list file 19, and a simulation result file of the circuit simulator 20 (hereinafter, the result file 26 is abbreviated). ), 27 are both result files 11, 2
Comparison means for comparing 6 (hereinafter abbreviated as comparison means 27)
The results are shown in the result display means 28 and the result list 29.

Next, the operation of the layout verifying apparatus of the fourth embodiment constructed as described above will be explained based on the respective embodiments and the flow charts of FIGS. 19 to 21.
First, the operation of the first net number extracting means 24 for extracting the net number of the output point, which is performed by using the net list 9 not including the parasitic capacitance obtained in the same manner as in the first embodiment, will be described with reference to the flowchart of FIG. explain. First, the net number of the PLOOT / PRINT that is the desired output point (in this case, the output point is the point for which the waveform result is to be confirmed) is extracted from the netlist file 9 (step S37).

FIG. 23 shows an example of the netlist file 9 of the circuit diagram shown in FIG. 22, for example. In this case, from FIG. 23, PLOOT / PRINT is V (1
5), V (13) numbers 15, 13 are taken out. Next, when the element name of the extracted net number is checked from the net list file 9 (step S38),
It can be seen that the element name of the net numbers 15 and 13 is the transistor Q8 in FIG. Then, when the terminal name of the element of this net number is taken out (step S39), it becomes the transistors Q8-B (base) and Q8-E (emitter), and this net number 15 is b in FIG.
The point and net number 13 are points a.

Then, the operation of the second net number extracting means 25 for extracting the net number of the same output point by using the parasitic capacitance addition netlist file 19 obtained in the same manner as in the first embodiment is shown in FIG. A description will be given based on the flowchart. First, the terminal name of the element corresponding to the output point obtained in step S39 is input (step S40). Next, the net number of the terminal name of this same element is taken out from the parasitic capacitance addition netlist file 19 (step S41). This is because the net numbers of the terminals of the same element in the netlist file 9 and the parasitic capacitance netlist file 19 may not be the same due to the addition of the parasitic capacitance.

For example, FIG. 24 shows a circuit diagram in which a parasitic capacitance is added to the circuit of FIG. 22, and the parasitic capacitance addition netlist 19 is shown as in FIG. In this case, the device terminal names Q8-B and Q8
-E has a net number of 20 and 15 and parasitic capacitance is added, so a different value is extracted.

Next, the result file 11 that does not include the parasitic capacitance obtained in the same manner as in the first embodiment and the result file 26 that includes the parasitic capacitance obtained by the circuit simulator 20.
The operation of the comparison means 27 will be described with reference to the flowchart of FIG. First, the simulation result of the net number obtained by the first net number extracting means 24 for extracting the net number of the output point is input from the result file 11 (step S42), and the net number of the same output point is extracted. The simulation result of the net number obtained by the second net number extracting means 25 is input from the result file 26 of the circuit simulator 20 (step S43).

Then, it is judged whether the input net number of the simulation result is between DC and AC or between AC and AC based on the first embodiment (step S44). Then, when it is determined that it is between AC and AC, the amplitude and cycle of the AC signal are obtained from these simulation results (step S45). Then, the difference in amplitude and cycle between the data from the result file 11 for one AC signal and the data from the result file 26 of the AC signal corresponding to the same output point is obtained (step S46).

When it is determined that the value is between the other DC and AC, the maximum value and the minimum value are obtained from the simulation result of the DC signal (step S47). Then, the results of steps S46 and S47 obtained as described above are output to the result display unit 28 and the result list 29, respectively. If, as a result, the maximum value / minimum value of the DC signal is constant or the difference between the maximum value / minimum value is within the allowable range, the presence of the parasitic capacitance affects the simulation at that location. It is judged that it does not reach.

As described above, according to the fourth embodiment, the influence of the parasitic capacitance on the simulation can be verified.

[0042]

As described above, according to claim 1 of the present invention, the net list extracting means for extracting each net list containing no parasitic element from the layout pattern data or the circuit diagram data of the semiconductor integrated circuit is extracted. A circuit for simulating each netlist is used to distinguish each wiring on the layout pattern data into one in which an AC signal flows and one in which a DC signal flows, and the layout pattern data and the distinguished DC and AC. Retrieval means for retrieving the intersections of the respective wirings and the respective coordinates of the parallel portions using the wirings, parasitic element extracting means for extracting the respective parasitic elements from the retrieved intersections of the respective wirings and the respective coordinates of the parallel portions, and the respective nets. A verification tool that verifies the characteristics of the semiconductor integrated circuit by performing a circuit simulation including each parasitic element extracted above in the list. Since so provided the door, to simulate extraction only parasitic elements required, there is an effect that it is possible to provide a layout verification apparatus in a short time simulation.

According to a second aspect of the present invention, in the first aspect, the selection means for selecting each wiring having a parasitic element that needs to be extracted among the respective wirings of the semiconductor integrated circuit, and the discrimination means. Since there is provided the extracting means for extracting only the wiring selected by the selecting means among the distinguished wirings, there is an effect that only the parasitic element desired to be extracted can be simulated.

According to claim 3 of the present invention, in claim 1, there is provided a first net number extracting means for extracting a net number of a desired output point from each net list which does not include a parasitic element, and each parasitic. Second net number extracting means for extracting a net number of a desired output point from each netlist including elements, and first net number extracting means for the result of circuit simulation of each netlist including no parasitic element. And a comparison means for comparing the result of the net number extracted by the above-mentioned result with the result of the net number extracted by the second net number extracting means out of the results of the circuit simulation of each netlist including each parasitic element. By doing so, it is possible to easily compare the result with and without the parasitic element, and verify the effect of the parasitic element on the simulation. There is an effect that it is possible to provide a layout verification device that.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a layout verification device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of an AC / DC signal distinguishing unit of the layout verifying device shown in FIG.

FIG. 3 is a flowchart showing an operation of an AC signal fluctuation width extracting means of the layout verification apparatus shown in FIG.

FIG. 4 is a flowchart showing a part of the operation of the coordinate retrieving means of the cross / parallel portions of the layout verification apparatus shown in FIG.

FIG. 5 is one flowchart following the flowchart of FIG.

6 is another flowchart following the flowchart of FIG.

7 is a flowchart showing the operation of a parasitic capacitance netlist extraction means of the layout verification device shown in FIG.

8 is a diagram showing an example of a netlist file that does not include parasitic capacitance of the layout verification device shown in FIG.

9 is a diagram showing an example of a simulation result file that does not include parasitic capacitance of the layout verification apparatus shown in FIG.

10 is an AC / DC of the layout verification device shown in FIG.
It is a figure which shows an example of the discrimination file of a signal.

11 is an AC / DC of the layout verification device shown in FIG.
It is a figure which shows an example of the distinction file of the maximum value / minimum value of a signal and an AC signal.

12 is a diagram showing an example of coordinates and net numbers of wirings extracted from the layout pattern data of the layout verification device shown in FIG.

13 is a diagram in which a part of the coordinates of the wiring shown in FIG. 12 is plotted.

14 is a diagram showing an example of coordinate data of a cross-parallel portion of the layout verification device shown in FIG.

15 is a diagram showing an example of a cross area, a length of a parallel portion, a wiring interval, a net number, and a parasitic capacitance value obtained from the cross / parallel coordinate data shown in FIG.

16 is a diagram showing an example of a parasitic capacitance addition netlist file of the layout verification device shown in FIG.

FIG. 17 is a flowchart showing the operation of the layout verification device in the third embodiment of the present invention.

FIG. 18 is a diagram showing a configuration of a layout verification device according to a fourth embodiment of the present invention.

19 is a flowchart showing the operation of the first net number extraction means for extracting the net number of the output point of the layout verification device shown in FIG.

20 is a flowchart showing the operation of the second net number extraction means for extracting the net number of the same output point of the layout verification device shown in FIG.

FIG. 21 is a flowchart showing the operation of the comparison means of both simulation result files of the layout verification device shown in FIG.

FIG. 22 is a circuit diagram showing an example of a semiconductor integrated circuit.

23 is a diagram showing an example of a netlist file including no parasitic capacitance of the layout verifying device shown in FIG. 18 of the semiconductor integrated circuit shown in FIG. 22;

24 is a circuit diagram of a semiconductor integrated circuit showing an example in which a parasitic capacitance is added to the semiconductor integrated circuit shown in FIG.

25 is a diagram showing an example of a parasitic capacitance addition netlist file of the layout verification device shown in FIG. 18 of the semiconductor integrated circuit shown in FIG. 24.

FIG. 26 is a diagram showing a configuration of a conventional layout verification device.

[Explanation of symbols]

 8 Net List Extracting Means 12 AC / DC Signal Discriminating Means 16 Cross / Parallel Coordinate Searching Means 18 Parasitic Capacitance Extracting Means 27 Comparing Means of Simulation Result Files

Claims (3)

[Claims] 1. A netlist extracting means for extracting each netlist that does not include a parasitic element from layout pattern data or circuit diagram data of a semiconductor integrated circuit, and a circuit simulation using the extracted netlists. Distinguishing means for distinguishing each wiring on the pattern data into one in which an AC signal flows and one in which a DC signal flows, and an intersection point of each wiring using the layout pattern data and each of the distinguished DC and AC wirings. Retrieval means for retrieving each coordinate of the parallel portion, parasitic element extracting means for retrieving each parasitic element from the intersection of each wiring searched and each coordinate of the parallel portion, and the above-mentioned extracted to each netlist. A verification means for verifying the characteristics of the semiconductor integrated circuit by performing a circuit simulation including the above parasitic elements is provided. A layout verification device characterized by being provided. 2. A selecting means for selecting each wiring having a parasitic element that needs to be extracted from among the wirings of the semiconductor integrated circuit, and a wiring selected by the selecting means among the wirings distinguished by the distinguishing means. The layout verification apparatus according to claim 1, further comprising: an extracting unit that extracts only the data. 3. A first net number extracting means for extracting a net number of a desired output point from each net list that does not include a parasitic element, and a net of the desired output point from each net list that includes each parasitic element. A second net number extracting means for extracting a number, a net number result extracted by the first net number extracting means among the results of the circuit simulation of each net list not including the parasitic element, and each parasitic The comparison means for comparing with the result of the net number extracted by the second net number extraction means out of the results of the circuit simulation of each netlist including the elements. Layout verification device.