JPH09260499A - Computer for delay time between designated nodes in integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically compute the delay time between optional designated nodes, by providing a computer with a delay time outputting means which outputs the delay time between the starting point node and the ending point node, based on the result of the simulation by a circuit simulator. SOLUTION: A node designating means 1 presents the relation of connection between cells to an operator, and the operator designates the starting point node and the ending point node by a mouth or a keyboard. A course retrieving means 2 retrieves the course between both nodes, based on the layout data L. A cell parasitic element abstracting means 3 abstracts parasitic resistance elements, parasitic capacitive elements, and transistor elements in individual cells on the retrieval course, and a wiring parasitic element abstracting means 4 abstracts the parasitic resistance elements and the parasitic capacitive elements of the wiring between individual cells on the retrieval course. Furthermore, a means 5 makes the not list of the parasitic circuits consisting of the abstracted parasitic elements, and a means 6 makes an input file F for simulation. A circuit simulator 7 performs the simulation based on the input file F, and a delay time output means 8 outputs the delay time between both nodes, based on the result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for calculating delay time between designated nodes in an integrated circuit, and more particularly to an apparatus for automatically calculating the delay time based on a dynamic analysis method.

[0002]

2. Description of the Related Art When designing a large scale integrated circuit,
A method is adopted in which a cell library constructed as a past design asset is used and cells in the cell library are combined to realize a desired integrated circuit. Actually, a cell library having various kinds of information on cells as digital data is prepared, and an automatic layout tool using a computer performs a circuit design work using the digital data in the cell library. In this way, when the design of the large-scale integrated circuit is completed by the combination of the cells, the circuit operation is verified, and if there is a problem, the design is changed. In verifying such circuit operation, it is particularly important to consider the delay time of each part of the circuit. If the delay time becomes an unexpected value, the logical operation as originally designed may not be performed normally.

Generally, any two in a large scale integrated circuit
The dynamic analysis method and the static analysis method are known as methods for obtaining the delay time between two nodes.
The dynamic analysis method is a method of simulating the actual signal propagation process in real time based on the physical properties of the designed circuit (width, thickness, impurity concentration, etc. of each layer), and is performed using a logic simulator such as SPICE. Be seen. On the other hand, the static analysis method is a method in which the delay time is calculated for each element existing on the path between the two nodes, and the sum of these delay times is calculated as the delay time between the two nodes. In the dynamic analysis method, the computational load on the computer is greater than in the static analysis method, but the delay time can be obtained with higher accuracy.

[0004]

When the delay time between two nodes is obtained by the above dynamic analysis method,
Conventionally, a netlist for the entire designed layout module is created, or a target route is manually extracted, a netlist for the extracted route is created, and a simulation is performed based on this netlist. Since it had to be performed, there was a problem that there was much waste and work efficiency was low.

Therefore, an object of the present invention is to provide an apparatus capable of automatically calculating a delay time between arbitrary designated nodes in an integrated circuit.

[0006]

[Means for Solving the Problems]

(1) A first aspect of the present invention is an apparatus for calculating a delay time between two designated nodes for an integrated circuit designed by combining cells in a cell library prepared in advance, Node designation that presents the operator with the connection relationship between cells based on the layout data indicating the configuration of the designed integrated circuit, and inputs the information that specifies the start point node and the end point node from the plurality of nodes existing between the cells Means, a route search means for searching a route from the start point node to the end point node based on the layout data, and by referring to the in-cell information for each cell prepared in the cell library, Refer to the layout data and the cell parasitic element extraction means for extracting the parasitic elements existing on the search path for each cell existing above Thus, the wiring parasitic element extraction means for extracting the parasitic elements existing on the individual inter-cell wiring along the search path, and the parasitic elements extracted by the cell parasitic element extraction means and the wiring parasitic element extraction means are searched for on the search path. Parasitic circuit composed by arranging
A netlist creating means for creating a netlist, process data used for actually manufacturing an integrated circuit, and a predetermined input signal waveform given to the input end of the netlist are set, and the set process data and input signal waveform are set. Input file creation means for creating a simulation input file based on the input file and the netlist, and a simulation of the propagation process of the signal waveform when the input signal waveform is given to the parasitic circuit based on the created input file. The circuit simulator to be performed and the delay time output means for outputting the delay time between the start point node and the end point node based on the result of the simulation by the circuit simulator are provided.

(2) The second aspect of the present invention is the above-mentioned first aspect.
In the delay time calculating device according to the above aspect, the node designating means presents the connection relationship between cells on the display screen to present it to the operator, and designates one point on this screen with the mouse to select the node. Selectively executes the first specifying function for specifying and the second specifying function for presenting each node name of the inter-cell node to the operator and specifying the node by inputting a specific node name from the keyboard. It is configured to be possible.

(3) A third aspect of the present invention relates to the above-mentioned first aspect.
Alternatively, in the delay time calculation device according to the second aspect, the route search means may extend from the start point node to the end point node,
It has a function of determining whether or not a path through which a signal flows in one direction is formed, and notifying the operator of an error if such a path is not formed.

(4) The fourth aspect of the present invention is the above-mentioned first aspect.
In the delay time calculating device according to the third aspect, the cell parasitic element extracting unit extracts the parasitic resistance element, the parasitic capacitance element, and the transistor element existing in the cell as the parasitic elements, and the wiring parasitic element extracting unit sets the wiring The parasitic resistance element and the parasitic capacitance element existing above are extracted as a parasitic element.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on an embodiment shown in the drawings. FIG. 1 is a conceptual diagram showing a general large-scale integrated circuit design method. Currently, a general integrated circuit is designed using an automatic layout tool 10 using a computer. A cell library C for a large number of cells has already been constructed as a design asset up to now, and a designer can design a desired integrated circuit by combining the cells in the cell library C. When such a design work is performed, the layout data L is automatically created by the automatic layout tool 10. The layout data L includes even graphic level data indicating individual layers formed on the semiconductor wafer, and a mask pattern created based on the layout data L is used to generate an actual semiconductor. The device can be manufactured.

FIG. 2 is a conceptual diagram showing an example of a large scale integrated circuit 20 designed by the automatic layout tool 10. Usually, as shown in the drawing, a large number of cells 21 are arranged adjacent to each other in a row, and a plurality of such rows are arranged at a predetermined interval. The individual cells are connected to each other by the wiring 22 formed in the space between the columns. In FIG. 2, for convenience of description, a state in which three cell rows each including five cells are arranged is shown.
In an actual large-scale integrated circuit, a very large number of cells are arranged in such a form, and a large number of wirings are also provided between the cells. However, cell 21 and wiring 2 between cells
Regarding the essential part of forming a large scale integrated circuit by 2 and 2, there is no difference between the large scale integrated circuit 20 shown in the conceptual diagram of FIG. 2 and the actual large scale integrated circuit.
In verifying the operation of such a large scale integrated circuit 20,
It becomes necessary to find the delay time between the two nodes. The present invention provides an apparatus capable of automatically calculating a delay time between designated nodes in a large scale integrated circuit 20 designed by combining cells in a cell library prepared in advance as described above. To do.

FIG. 3 is a block diagram showing the basic configuration of the delay time calculating device according to the present invention. The main constituent elements of this device are node designating means 1, route searching means 2, cell parasitic element extracting means 3, wiring parasitic element extracting means 4, netlist creating means 5, simulation input file creating means 6, circuit simulator 7, The delay time output means 8. Each of these means is actually implemented by specific computer software, and the cylindrical blocks in the figure represent the data handled by each of these means. The layout data L is data obtained by the design work by the automatic layout tool 10 as described in FIG. 1, and is the large scale integrated circuit 20 shown in FIG.
It is data showing the configuration of.

Based on the layout data L, the node designating means 1 presents the operator with a connection relationship between cells and provides information for designating a start point node and an end point node among a plurality of nodes existing between cells. Has a function to input. In this embodiment, a display as shown in FIG. 2 is displayed on the display screen, the connection relation of individual cells is presented to the operator, and the operator specifies one point on this screen by using the mouse. A first designating function for designating a node and a second designating function for designating a node by displaying the individual node name on the display screen and allowing the operator to input the node name using the keyboard. Is prepared. The operator selects one of the functions and inputs the start point node and the end point node.

Specifically, for example, the display as shown in FIG. 2 is displayed on the display screen. When the operator selects the first function, the start point node and the end point node are designated by inputting the positions of the inter-cell nodes N1 to N5 on the wiring 22 displayed on the screen with the mouse. Become. When the second function is selected, an individual node name such as "N1" is input from the keyboard to specify the start point node and the end point node.

The route search means 2 executes a process for searching a route from the start point node designated by the node designation means 1 to the end point node based on the layout data L. Here, for example, the large-scale integrated circuit 2 shown in FIG.
At 0, the case where the node N1 is designated as the start node and the node N2 is designated as the end node will be described as an example. Since the layout data L includes information such as each constituent element in each cell, their connection state, and signal transmission direction, the route searching means 2 uses the starting point node N1.
When the end point node N2 and the end point node N2 are designated, a route from the start point node N1 to the end point node N2 can be searched by referring to the layout data L. In the case of this example, node N1 → cell C22 → node N3 → cell C
32 → node N5 → cell C34 → node N4 → cell C2
A route of 5 → node N2 will be searched. Here, since each node corresponds to the wiring 22 between cells, in the end, the path thus searched is constituted by the cell or the wiring between cells.

The cell parasitic element extraction means 3 refers to the in-cell information for each cell prepared in the cell library C, and exists on the search path for each individual cell on the search path. It is a means for performing the process of extracting the parasitic element. The cell library C used for designing the large-scale integrated circuit 20 includes information indicating the configuration of each cell for each cell. Generally, in a cell of a semiconductor integrated circuit, a parasitic element that causes a delay in a signal propagation process can be classified into three types of a resistance element, a capacitance element, and a transistor element. The cell parasitic element extraction means 3 recognizes these three types of parasitic elements contained in the cell based on the in-cell information in the cell library C, and extracts the recognized parasitic element. In the case of the above example, the cell C22 on the route,
For each of C32, C34, and C25, the resistance element, the capacitance element, and the transistor element are extracted as parasitic elements. However, the parasitic elements extracted for each cell are only those existing on the search path,
Parasitic elements existing at locations unrelated to the search path are not extracted.

On the other hand, the wiring parasitic element extraction means 4 is a means for referring to the layout data L to extract the parasitic elements existing on the individual inter-cell wiring along the search path. The inter-cell wiring layer 22 shown in FIG. 2 is composed of a conductive layer arranged between cells,
The parasitic element that causes the delay can be classified into two types, that is, a resistance element and a capacitance element. The wiring parasitic element extraction means 4 recognizes these two types of parasitic elements based on the graphic data of each wiring included in the layout data L, and performs processing for extracting the recognized parasitic elements. In the above example, the nodes N3 and N on the route are
For each of the individual wirings corresponding to 5 and N4, the resistance element and the capacitance element are extracted as parasitic elements.

The netlist creating means 5 creates a netlist for a parasitic circuit formed by arranging the parasitic elements extracted by the cell parasitic element extracting means 3 and the wiring parasitic element extracting means 4 on the search path. Do the work. In the case of the above example, the parasitic element extracted for the cell C22, the parasitic element extracted for the wiring corresponding to the node N3, the parasitic element extracted for the cell C32, the parasitic element extracted for the wiring corresponding to the node N5, ..., the parasitic element extracted for the cell C25,
In this order, the extracted parasitic elements are arranged, and a netlist about the parasitic circuit configured by such arrangement is created.

The simulation input file creating means 6 is a means for creating an input file F for performing simulation on the netlist created in this way. This input file F includes a netlist, an input signal waveform, and process data.
The netlist is created by the netlist creating means 5, and the input signal waveform and the process data are set by the simulation input file creating means 6. The process data is a physical process value used for actually manufacturing an integrated circuit, and specifically, sheet resistance value of each layer, unit capacitance value, film thickness value of each layer, impurity concentration value of semiconductor layer, etc. Is the numerical value of. On the other hand, the input signal waveform is the signal waveform given to the input terminal of the circuit to be simulated, and as a result of the simulation, the output signal waveform corresponding to this input signal waveform is obtained, The delay time is determined on the basis of the deviation.

The circuit simulator 7 is a device for performing a circuit simulation based on the above-mentioned input file F, and a device generally called "SPICE" is widely used. After all, in this circuit simulator 7,
A simulation of the propagation process of the signal waveform when a given input signal waveform is given to the extracted parasitic circuit will be performed, and eventually some output signal waveform will be obtained at the output end of this parasitic circuit. become.

The delay time output means 8 outputs the delay time for the route from the start point node to the end point node based on the result of the simulation thus obtained. That is, a degree of delay of the output signal waveform obtained as a result of the simulation with respect to the input signal waveform used in the simulation is numerically expressed, and this is output as the delay time between the designated nodes.

4 and 5 are flow charts showing the procedure of the delay time calculation processing by the device shown in FIG. This procedure is composed of a node designating process (upper part in FIG. 4) in the former stage, a parasitic element extracting process in the middle part (lower part in FIG. 4), and a delay time calculating process (FIG. 5) in the latter part. First, in step S1, the operator selects a node designation method. As described above, the node designating means 1 has a node designating function on the display screen with a mouse and a node designating function with a node name input by the keyboard. If the former is selected, the node is specified using the mouse in step S2, and if the latter is selected, the node is specified using the keyboard in step S3. When the designation of the start point node and the end point node is completed in this way, a route search is performed in step S4. In this route search processing, as described above, the route from the start point node to the end point node is searched while referring to the layout data L. In the following step S5, as a result of the route search processing, it is determined whether or not the start point node and the end point node are continuous, and if they are not continuous,
In step S6, the process of notifying the operator of the error is executed, and the process returns to step S1.

The determination process in step S5 is as follows.
Not only is it determined whether or not the start point node and the end point node are electrically continuous, but it is also determined whether or not the two nodes are continuous in consideration of the signal transmission direction. For example, as shown in FIG. 6, node N11 → N1
2 → N15 signal flow and nodes N13 → N14
If the signal flow of → N15 is defined and the signal flow of node N15 → N16 is further defined, designation is made that the start point node is N11 and the end point node is N16, or the start point node is N13 and the end point node. To N16
When it is specified that the nodes are continuous, the nodes are determined to be continuous. However, when the nodes are specified as N11 for the start point node and N13 for the end point node, the signal transmission direction between the two nodes is changed. By considering it, it will be judged as discontinuous. In short, it is judged whether or not a path through which a signal flows in one direction is formed from the start point node to the end point node, and if such a path is not formed, an error notification is given to the operator in step S6. Processing will be performed.

When the preceding node designation processing is completed in this way, the intermediate parasitic element extraction processing is subsequently executed.
That is, first, in step S7, the path is sequentially traced from the start point node, and the cell or wiring to be extracted is selected. Here, when the cell is selected, the process proceeds from step S8 to step S9, and the parasitic element of the selected cell is extracted by the cell parasitic element extraction unit 3. On the other hand, if wiring is selected, step S
From step 8 to step S10, the parasitic element of the selected wiring is extracted by the wiring parasitic element extraction means 4.

Such parasitic element extraction processing is repeatedly executed through step S11, and when the end node is reached, this middle processing is completed. In the case of the specific example described above, first, the cell C22 is selected in step S7, and the parasitic element for the cell C22 is extracted in step S9. That is, the parasitic resistance element, the parasitic capacitance element, and the transistor element related to the search path in the cell C22 are extracted. Subsequently, the process returns from step S11 to step S7, the wiring corresponding to the node N3 is selected this time, and in step S10, the parasitic element for this wiring, that is, the parasitic resistance element and the parasitic capacitance element are extracted. Next, the process returns from step S11 to step S7 again, and the cell C32 is selected. After that, the same process is repeated, and when the parasitic element of the cell C25 is extracted, the whole process of this middle stage is completed.

Finally, the subsequent delay time calculation process shown in FIG. 5 is executed. That is, first, in step S12, the netlists are combined. Various parasitic elements have already been extracted along the search path, and a parasitic circuit is configured along the path from the start point node to the end point node. Therefore, the netlist creating means 5 creates a netlist for this parasitic circuit. Further, in step S13, the input file F is created by the simulation input file creating means 6, and in step S14, the input file F is created by the circuit simulator 7.
Based on the simulation result, the delay time is finally output in step S15. The delay time can be obtained by the so-called dynamic analysis method.

In the case of the above example, a parasitic circuit in which a parasitic resistance element, a parasitic capacitance element, and a parasitic transistor element are arranged is formed along the search path from the start point node N1 to the end point node N2. Then, when a predetermined input signal waveform is applied to the start point node N1 and other necessary input terminals of this parasitic circuit, what kind of output signal waveform is obtained at the end point node N2 is obtained by simulation,
The delay time between the nodes N1 and N2 can be obtained based on the time-axis shift between the input signal waveform and the output signal waveform. The circuit that is the target of this simulation is a circuit that consists only of parasitic elements related to the search path from the start point node N1 to the end point node N2. Therefore, compared with the case of performing a simulation for the entire large-scale integrated circuit 20, the calculation processing load is extremely light and the delay time can be calculated efficiently.

[0028]

As described above, according to the delay time calculation apparatus between designated nodes according to the present invention, the delay time between any designated nodes in the integrated circuit can be automatically calculated.

[Brief description of drawings]

FIG. 1 is a conceptual diagram showing a method of designing a general large-scale integrated circuit.

FIG. 2 is a conceptual diagram showing an example of a large scale integrated circuit designed by an automatic layout tool.

FIG. 3 is a block diagram showing a basic configuration of a delay time calculation device according to the present invention.

FIG. 4 is a flowchart showing a procedure of a preceding stage and a middle stage of a delay time calculation process by the device shown in FIG.

5 is a flow chart showing a procedure of a latter stage of the delay time calculation processing by the device shown in FIG.

FIG. 6 is a node connection diagram for explaining a method of continuous determination between nodes in step S5 of the flowchart shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Node designating means 2 ... Route searching means 3 ... Cell parasitic element extracting means 4 ... Wiring parasitic element extracting means 5 ... Netlist creating means 6 ... Simulation input file creating means 7 ... Circuit simulator 8 ... Delay time output means 10 ... Automatic layout tool 20 ... Large scale integrated circuit 21 ... Cell 22 ... Wiring between cells C ... Cell library C11 to C35 ... Individual cells F ... Simulation input file L ... Layout data N1 to N5, N11 to N16 ... Nodes

Claims (4)

[Claims] 1. A device for calculating a delay time between two designated nodes in an integrated circuit designed by combining cells in a cell library prepared in advance. Node designating means for presenting to the operator a connection relationship between cells based on the layout data indicating, and inputting information designating a start point node and an end point node from a plurality of nodes existing between cells, and the layout data Based on the route search means for searching the route from the start point node to the end point node, by referring to the in-cell information for each cell prepared in the cell library, Cell parasitic element extraction means for extracting the parasitic elements existing on the search path for each individual cell that exists, and the layout data Line parasitic element extraction means for extracting the parasitic elements existing on the individual inter-cell wiring along the search path, and the parasitic elements extracted by the cell parasitic element extraction means and the wiring parasitic element extraction means. For a parasitic circuit configured by arranging the above on a search path, a netlist creating means for creating a netlist, process data used for actually manufacturing the integrated circuit, and an input end of the netlist. A predetermined input signal waveform is set, and based on the set process data and input signal waveform and the netlist, a simulation input file creating means for creating an input file for simulation, and based on the input file , A stain in the propagation process of the signal waveform when the input signal waveform is applied to the parasitic circuit And a delay time output means for outputting a delay time between the start point node and the end point node on the basis of the result of the simulation by the circuit simulator. Delay time calculation device between nodes. 2. The delay time calculation device according to claim 1, wherein the node designating means presents to the operator by displaying the connection relationship between the cells on the display screen, and one point on this screen is displayed. A first specifying function for specifying a node by specifying with a mouse, and a second specifying function for presenting each node name of inter-cell nodes to an operator and specifying a specific node name from the keyboard And a delay time calculation device between designated nodes in an integrated circuit, wherein 3. The delay time calculation device according to claim 1 or 2, wherein the route search means determines whether or not a route through which a signal flows is formed from a start point node to an end point node. A delay time calculation device between designated nodes in an integrated circuit, having a function of notifying an operator of an error when such a route is not formed. 4. The delay time calculating device according to claim 1, wherein the cell parasitic element extracting means extracts a parasitic resistance element, a parasitic capacitance element, or a transistor element existing in the cell as a parasitic element. A delay time calculation device between designated nodes in an integrated circuit, wherein the wiring parasitic element extraction means extracts a parasitic resistance element and a parasitic capacitance element existing on the wiring as parasitic elements.