JPH07250362A - Radio selective call receiver with message - Google Patents

Abstract

PURPOSE:To attain optional setting of an alarm time by providing a means decoding a designated signal in response to the detection of a frame synchronizing signal and a means calibrating a calendar or time to a content of the decoded designated signal to the calling receiver. CONSTITUTION:A switching circuit 1 applies voltage with a prescribed waveform intermittently to a radio section 20 and a waveform shaping circuit 30 to make the operation of a power supply efficient. When a desired radio frequency signal comes while the voltage is applied, a reception signal is detected via an antenna 10, the radio section 20 and the circuit 30 and when the signal is an individual selective call signal of the receiver, a decoder 40 detects the signal to release battery saving. Then the voltage is applied continuously to the radio section 20 and when a succeeding frame synchronizing signal is detected, a content in a PROM 50 in which a call signal of a concerned receiver is written is compared with the reception signal and when the coincidence is confirmed, a processing section 60 processes a message signal to activate an alarm horn 80 and a display device 90.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio selective call receiver, and more particularly to a radio selective call receiver having a clock function.

[0002]

2. Description of the Related Art In recent years, the progress of device technology has been remarkable.
In the wireless selective call receiver as well, from the conventional call-only function to the one that can receive even a series of messages composed of numbers and letters, the reception function has been improved and the device has been downsized. Development is remarkable.

[0003]

Although a device having a clock function may be considered as a part of such an enhancement of the function ("Practical application No. 54-142160", a personal selective calling receiver with a display), an alarm time setting function. No device has been announced yet. An object of the present invention is to provide a wireless selective call receiver with a clock function (with a calendar function) for receiving time information (month / day information) sent regardless of an individual selective call number and sequentially calibrating an internal clock (internal calendar). Is to provide. Another object of the present invention is to provide a radio selective calling receiver having a clock function and capable of receiving a message, which can arbitrarily set an alarm time by the message signal.

[0004]

A radio selective call receiver with a message according to the present invention is a radio call receiver which receives a call signal composed of a frame synchronization signal, a selective call signal, a designation signal and a message signal. It is provided with first means for decoding the designated signal in response to the detection of the frame synchronization signal, and means for calibrating the calendar or the time to the content of the decoded designated signal.

[0005]

The present invention will be described in detail below with reference to the drawings.
1 and 3 are block diagrams of a receiver used in the present invention. The outline of the operation of this receiver is shown in FIGS. 1, 4 and 5.
Will be explained. FIG. 4 is a signal configuration diagram, [I]
Is a front signal pattern, [II] is a synchronization signal pattern,
[III] is a configuration pattern of the address signal and the message signal, [IV] is a configuration pattern of the first control signal,
[V] represents a configuration pattern of the second control signal, and [VI] represents an end signal pattern.
(I) and A (II) are diagrams showing a time chart in the normal operation together, and FIG. 5B is a diagram showing a time chart in the operation when the power is turned on after the preamble signal.

That is, the switching circuit 1 shown in FIG.
A state in which the voltage waveform shown in (j) of (I) is intermittently applied to the wireless unit 20 and the waveform shaping circuit 30 to achieve efficient operation of the power supply (this operation is generally referred to as battery saving. 5A (I) (a) in FIG. 5A (I) via the antenna 10, the radio unit 20, and the waveform shaping circuit 30 when a desired radio frequency arrives while a voltage is applied at (BS).
The received signal as shown in is detected. Here, the individual selective call number of the receiver (hereinafter referred to as "ID") "A1"
, The preamble signal for canceling the BS (hereinafter referred to as "P") is detected by the decoder 40 (D).
At T1), the BS is released and the voltage is continuously applied to the wireless section (j). In this way, the subsequent frame synchronization signal (hereinafter referred to as "SC") is detected (DT
2) and the programmable ID in which your own ID is written.
The contents of the read-only memory [P-ROM] 50 and the received signal are compared and collated to confirm the coincidence (DT3).
And a message data (hereinafter referred to as “MD”) processing unit 6
At 0, the message signal following the ID signal is processed. Then, the signal (d) drives the transmission means (for example, an alarm horn) via the buffer 70, or the signal (c).
The contents of the message data received by the liquid crystal display device [L
CD] 90, or output to the terminal 5 as a signal (g). Here, since a central processing unit (CPU) that requires high-speed processing capability and a dynamic drive type LCD drive usually require a voltage of 2 V or higher, a booster circuit 7 that boosts the voltage of the battery 6 is used. Now, in the received signal (a), each of the constituent elements P, SC, I
Details of D and MD are shown in FIG.

The preamble signal P is a repeating pattern of logic "1" and "0" as shown in FIG. 1I, and the frame synchronization signal SC is a specific pattern shown in FIG. Individually selected call number ID is shown in the figure [III]
The MSB (identification bit) is a BCH (31, 21) code having an inter-code distance 5 of logic "0" in the configuration pattern shown in FIG.
I], the MSB (identification bit)
Is given as a logic "1" and is divided into a first control signal "T", a second control signal "I" and an information message M as shown in FIGS. 5A (I) and A (II). There is. That is, the first control signal shown in [IV] of FIG.
(I) Code Z as message information indicated by "1" when there is a message addressed to the own device and "0" when there is no message
0, and (ii) information designating the format of the subsequent message (for example, "001" if the message is numeric information composed of BCD code, "010" if the message is ASCII code compatible, and "10" if it is JIS code compatible.
0 "or" 111 "for facsimile information) and (iii) the time from the first control signal to the next SC, T, or I as shown in FIG. 5A (I). 31 bits as 1 for the specified duration information
BCD code Z2 to represent the number of words in words
Made up of Z5.

The second control signal shown in FIG. 4 [V] is a signal "MCS" for designating the processing of the received message and a signal "TS" for indicating time or date information.
Composed of. Here, the meaning of Table 1 which defines the message processing corresponding to the MCS pattern is as follows.

[0009]

[Table 1]

First, item 1 means that the received message is not processed. Items 2 and 3 indicate that the ID corresponding to the received message is set as the ID of the own device, or conversely, the ID registered in the own device is changed. Item 4 sets the built-in clock and sounds the ring alert at the time corresponding to the received message. Item 5 secures the message memory area according to the ID and byte information corresponding to the received message. Item 6 is that the receiver receives the time from BS start to SC detection as a message signal, and when the SC cannot be detected within the time, some means (for example, an alarm horn sounds with a sound different from the normal ringing sound). Sound) to warn. Items 7 and 9 arrange and output the contents of the received message according to a predetermined format (see Tables 2 and 3) and output.

[0011]

[Table 2]

[0012]

[Table 3]

Item 8 processes the TS shown in FIG. 4 [V] as month / day information. Note that TS represents normal time information, and the code configuration in each case is shown in Table 4. Next, in FIG.
The pattern I] corresponds to the signal E in the signal (a) of FIG. 5A (II) and is used as an end signal.

[0014]

[Table 4]

Now, the decoder 40 shown in FIGS.
As the SC detection circuit, as shown in FIG. 6, a reception signal is fetched into the shift register 500 in series by a clock as shown in FIG. 6, and it is determined whether the read 31 bits have a predetermined desired pattern. That is, if it is a desired pattern, the AND gate 540 outputs a coincidence signal. Further, as shown in FIG. 7 as the ID detection circuit, the received signal (a) and the signal (e) from the P-ROM 50 in which the calling number of the own machine is written are EXNOR.
It is input to 610 and collated for each bit, and the coincidence output is input to the counter 600. As a result, the own device is called by the detection pulse output when the number of coincident inputs reaches a preset value.

Next, the buffer 70 is provided with a circuit configuration using transistors as shown in FIG. The message processing unit 60 in FIG. 2 is a 1-chip CPU (message decoder) 100, a random access memory [R
AM] 300 and an LCD driver 200, and the RAM 300 includes a diode 61 and a large-capacity capacitor 63. The backup circuit allows data protection even when the battery is replaced. And
The configurations of the 1-chip CPU 100 in the message processing unit 60 in FIGS. 1 and 3 are shown in FIGS. 9 and 11, respectively. The decoder 8 in FIG. 3 is provided by the one-chip CPU shown in FIG. 10, and the function of each block is as follows. 102 to 106, 119 to 121 are input ports, 101, 110 to 118 and 122 are output ports, 1
Reference numeral 07 is an interrupt port, 108 is a serial interface, 120 is a data bus, 130 is a program counter indicating the contents of an address, 140 is a sequence of instructions to be executed, and the contents of the address specified by the program counter 130 are read out. Ram memory, 160
Decodes the information from the program memory 140,
An instruction decoder for supplying a control signal corresponding to the instruction to each unit, 150 is an ALU (Arithmetic a) for performing various operations such as arithmetic operation and logical operation.
An ND Logic Unit) 180 is an RA used for storing various data, saving a program count and a program status in a subroutine and an interrupt.
M, ALU150 calculation result is stored, RAM1
80 ACC (A used to send and receive data between each boat
ccumulator), and 190 is a system clock generation circuit that determines the execution instruction cycle time.

Next, the LCD driver 200 is given in the block configuration of FIG. 12, and 295 is the one-chip CPU 100.
A serial interface 270 for serially connecting the data between the input and output terminals, a command decoder 270 for fetching and decoding an instruction input via the serial interface 295, and controlling each unit according to the content of the instruction, 29
0 is a character generation circuit for generating a pattern of a 5 × 7 dot matrix corresponding to the input data,
280 is a data pointer for designating the writing of data from the serial interface 295 or the reading address of the data to the serial interface 295, 250 is a data memory for storing the output of the character generation circuit 290 or the display data from the serial interface 295, Reference numeral 220 is a row driver for controlling the row of the LCD, 210 is a column driver for controlling the column of the LCD,
Reference numeral 230 denotes an LCD voltage controller that controls the voltage to the LCD, and 240 denotes L that controls the drive timing of the LCD.
The CD timing controller, and 260 is the system clock controller.

Further, the RAM 300 is provided in the block configuration of FIG. 13, 310 is a serial interface for serially transferring data to and from the one-chip CPU 100, 320 is an address counter, and 330 is data of the address counter 320. Memory array 340
Is an XY decoder for designating the address of, and writing or reading data in the memory, 340 is a memory array, and 350 is a control circuit. FIG. 14 is a configuration example of the switching circuit 1. FIG. 15 shows the data structure of the output signal (g) to the external terminal 5, where each character has 11 bits. FIG. 16 is a circuit example of the level shift 3. FIG. 17 shows an example of the key layout of the data input section. The operation of the receiver in each case will be described below.

A) The desired signal is received after the power is turned on.
At this time, as shown in FIG. 5A (I), among the receivers in the BS state, the one having the ID of A1 is SC after the reception of P.
Is detected, the subsequent signal T1 is decoded. At this time,
Since the message data M1 follows, Z0 is a logical "1", and the period represented by the BCD code of Z2 to Z5 (at least until the next SC, usually A2 and T2)
BS is released (OFF). Further, when "1000111" is received as the "MCS" pattern when decoding I1, the message data of M1 is decoded by the code corresponding to Z1 and stored in the RAM 300 and the LCD.
This is displayed on the LCD 90 via the driver 200, and the transmission means 80 is driven via the decoder 40 and the buffer 70 to notify the device holder of the calling. Also I
The built-in calendar is calibrated with the month / day information of the 1 “TS” pattern.

Then, the following SC, ID, T2 and I2 are detected and decoded. At this time, SC is detected, but since the ID signal is A2 and is not detected, the detection pulse DT3 is not output. Therefore, Z2-Z5 of T2 and "MCS" of I2,
Looking at only the "TS" pattern, Z2 after detecting the I2 signal
While turning on the BS for the period indicated by Z5 (usually before the next SC), when "MCS" is other than 1000111, the built-in clock is calibrated at the time corresponding to the "TS" pattern, and the received and stored message is stored. The reception time is added to. Thus, the BS is turned off again at the next SC time. Since this period also has a different ID for A3 and the internal clock has already been calibrated, the period is up to T3. Thereafter, such an operation is repeated, and when the end signal E indicating the end of the data is detected, the normal BS operation is restored.

In a receiver whose ID is A3, P
SC is detected following the reception of T1, but since the IDs do not match at A1, Z2 to Z5 and I1 of T1 are detected.
See only the "TS" pattern of. And after turning on the period BS shown by Z2-Z5 after detecting the signal of I1,
Calibrate the built-in calendar on the month and day corresponding to the "TS" pattern. Thus, at the next SC time, BS again
Is OFF until I2, SC is detected, but ID
Is not detected, Z2-Z5 of T2 and "M of I2"
Only see the "CS" and "TS" patterns. Then, after detecting I2, turn on the BS for the period of Z2 to Z5, and
When S "is other than 1000111, the built-in clock is calibrated at the time corresponding to the" TS "pattern. Of course, when the" MCS "pattern is 1000111, the built-in calendar is calibrated with the month / day information corresponding to the" TS "pattern. Thus, at the next SC time, the BS turns off again,
SC detection operation is performed. When SC and ID are detected, the BS OFF state continues for the period of Z2 to Z5 at T3, and the "MCS" pattern is 1000011.
Then, the time corresponding to M3 decoded by the code corresponding to Z1 is stored. When the built-in clock reaches the predetermined time, the transmission means 8 is passed through the decoder 40 and the buffer 70.
While 0 is driven, the fact that it is a setting alarm is displayed on the LCD 90 (FIG. 18 is an example). Also, the built-in clock is calibrated again with the time information corresponding to "TS" of I3. After that, when there is no ID corresponding to A3 and the end signal E is received, the normal BS operation is restored. By the way, in the present embodiment, unless the end signal E is received, the reception of SC
The signal T is checked regardless of whether it has not been received yet, and if this signal cannot be received correctly, the BS is forcibly turned off for a predetermined period (about 1 minute in this embodiment), and S
Effective use of the battery by shifting to C signal reception and returning to normal BS operation if it cannot be detected, and returning to normal BS operation by judging that the electric field is defective if SC is not detected twice or more consecutively. The reliability of the reception is improved as well as the measurement.

B) When a desired signal arrives and the power is turned on . In FIG. 5B, the receiver whose ID is AN is continuously turned on B for a predetermined period (about 1 minute in this embodiment) when the power is turned on.
S is turned off and the desired SC signal is detected. When the SC signal is detected in this way, the ID is detected but not received. Therefore, after the I2 is detected, the built-in calendar or clock is calibrated with the "TS" information according to the "MCS" pattern, and the Z2 of the T2 is detected. The BS is turned ON during the period of Z5. Then, at the next SC, the operation of turning off BS again is repeated. Thus, when the ID corresponding to AN is received, the BS of the TN during the period from Z2 to Z5 is turned off,
If the IN “MCS” pattern is 1000101, TN
The message data MN is decoded and stored by the code corresponding to Z1. As a result, if the SC is not detected by the time when the time corresponding to the received data is confirmed by the built-in clock after returning to the BS operation, a warning alarm is issued to notify that the user is not in a good service area. (When it is detected, the timer is stopped and restarted by returning to the BS.), And the BS is forcibly set to BSOFF for a predetermined fixed period (about 1 minute in this embodiment).
The C detection is performed, and the operation of returning to the BS operation is repeated if the SC is not detected in the certain period.

C) Registration / reading by manual input of fixed form information
The operation will be described below with reference to the protrusion table 5 and FIG.

[0024]

[Table 5]

A desired key is selected from the mode SW of the data input section 2 (however, when the "CAL" or "TIME" key is selected, the LCD 90 operates as a computer function or a clock function in cooperation with the CPU). . Also here, "TE
When the "L" key is pressed, an interrupt is issued from the K terminal of the interrupt port 107 shown in FIG.
The pattern corresponding to the "EL" key is input. As a result, the CPU recognizes that the device has been set to the "TEL" mode, and thereafter, the data such as "DA" is input from the input port 103.
TA IN ”,“ AOKI ”,“ DATA IN ”,
"NEC", "DATA IN", "03-262-5"
174 ”,“ DATA IN ”,“ KUDO ”,“ DA
"TA IN", "SONY", etc. are input. When the result of key input is confirmed, the data is read according to a predetermined format (see Table 2), and first "DATA" is input.
Pressing the “OUT” key causes “AOKI” to be displayed on the LCD, and then pressing the “→” key causes “NEC” to be further changed to “→”.
If you press the key, press "03-262-5174", then press the "→" key, "KUDO", and then press the "↓" key, "E"
NDO ”,“ → ”key to“ KDD ”,“ ↑ ”key to“ S ”
You can check it like "ONY".

Similarly, when the "MEMO" key is pressed,
An interrupt is generated from the K terminal of the interrupt port 107, and the pattern “0010011” corresponding to the “MEMO” key is input from the input port 102. This result C
The PU determines that the device has been set to the "MEMO" mode, and thereafter inputs the following data ["DATA IN", "FEB.10.1984" input from the input port 103.
"SCHEDULE", "DATA IN", "9: 0
0 ”,“ DATA IN ”,“ MEETING (NEW
PRODUCT) AT5-1 "," DATA I
N ”,“ 10:30 ”, ...] to read“ DATA
When the "OUT" key is pressed, "FEB. 10.1984 SCHEDULE ”is displayed, and when the“ → ”key is pressed, the LCD display is“ 9:00 ”.
The display changes to "MEETIN" when the "→" key is pressed again.
G (NEW PRODUCT) AT5-1 ", and then press the" ↓ "key," TEL (NTT MR KUD
O) ”, the necessary information can be checked at any time with a simple operation instead of a memo pad. Furthermore, since this receiver has a built-in calendar and a built-in clock," FE
B. At the time of "9:00", "10:30", ... of 10 ", the transmission device (for example, alarm horn) of the receiver is driven to call attention and the sounding time is displayed on the LCD 90. For example, if it is 18:00, "GINZA (MORE)" will be displayed on the LCD.

D) Registration of fixed form information by radio The operation of the receiver will be described with reference to FIGS. 1, 9, 12, and 13. When the preamble signal P is received while the voltage is applied to the radio section 20 and the waveform shaping circuit 30 of the receiver operating in the BS in the switching circuit 1, it is sufficient to detect the following predetermined synchronization signal SC. Period B
Only S is turned off. Then, if SC is detected during this time, the detection pulse DT2 activates the one-chip CPU 100 via the interrupt port 107 and the decoder 40
Shifts to the ID detection operation. That is, with the detection of the SC as the starting point, the P-R in which the ID number of the own device is written
The data of the OM50 and the received data are compared and collated bit by bit (FIG. 7). When the coincidence is confirmed, the detection pulse DT3 causes the 1-chip CPU 10 via the input port 121.
Clock C that is input to 0 and corresponds to the transmission speed
L is supplied from the input port 105. At this time, DT
2 from the interrupt activation by a predetermined fixed period (DT
(Time until 3 is detected) and DT3 is input later, I
It is determined that D has been detected, and if not, it is determined that the IDs do not match and the preparation for the subsequent signal reception is made. As a result, in the 1-chip CPU 100, the message signal D is read from the input port 106 at the clock CL, the contents of the predetermined program memory 140 are translated by the instruction decoder 160, and processed in accordance with each instruction.
That is, the read signal is the data bus 120, AC
It is written to the RAM 180 via C170. In this way, every time 31 bits forming the BCH (31, 21) code are input, the ALU 150 performs an operation to decode the received signal.

The one-chip CPU 100 decodes 20 information bits of the first decoded BCH (31, 21) code in accordance with FIG. 4 [IV], and thereafter performs the BS operation of the receiver via the output port 112. Control.
At this time, if the 20 information bits have the following pattern, "110100000000000100000"
A "0" call is accompanied by a message, the message data has a 7-bit structure, and it is necessary to release the BS for at least 20 words (here, one word is 31 bits). Then, the signal I is decoded after waiting for the input of the next 31 bits. Thus, the 20-bit information area is analyzed according to FIG. 4 [V], Table 1 and Table 4. That is, if the information bit has the following pattern, "110001100101000100000" indicates that the subsequent message data is processed in the telephone directory mode, and the data transmission time is 10:20 AM.

The subsequent message is processed according to the control contents decoded in this way. Therefore, the information area (20-bit data) decoded every 31 bits is decoded in 7-bit units and sequentially stored in the external RAM 300. That is, by setting the chip select CS1 (negative logic) to the logic "0" level, the RAM 300 is set to the operation mode, and the address of the RAM 300 to be written is determined by the serial interface 108.
The corresponding address information is transferred via the signal line SO via. At this time, the 1-chip CPU 100 sends the system clock to the RAM 300 by SCK (negative logic) and at the same time, indicates that it is an address, and the signal line A / D (negative logic).
The signal line A / D (negative logic) is set to the logic "1" level to indicate that it is an address at the same time. And
At this time, in FIG. 13, the RAM 300 receives the input control signals (CS (negative logic), A / D (negative logic), R / W).
(Negative logic)), the signal input from the signal line SO is determined to be an address signal, and the address counter 320, X
An address to be written in the memory array 340 is designated via the Y decoder 330.

Next, the 1-chip CPU 100 sends the message data to be written to the serial interface 10
No. 8 signal line SO and the signal line A / D (negative logic) is set to a logic “0” level to indicate that the send data is message data, and the signal line R / W (negative logic) is used to instruct writing. ) Is a logic "0" level. As a result, in the RAM 300 of FIG. 13, the data input via the signal line SO is designated as message data corresponding to each input control signal via the XY decoder 330, and the RAM array 340 has been designated. Write in the address.

When the message data is sequentially decoded in the above process, when the SC or the end code is detected in the BCH (31, 21) unit or the reception cannot be performed continuously for two words, the 1-chip CPU 100 is used. Determines that the message data has ended, notifies the decoder 40 of the end of the message from the output port 110 via the signal line ME, and causes the sound generation circuit of the decoder 40 to operate with the signal line AC via the output port 111. To drive. The resulting signal (d), the alarm horn 8 via the buffer 70
0 sounds. Here, in case of SC detection, 1 chip CP
U100 repeats the same operation as above, but when the end code is received or two consecutive words have not been received,
Return to S operation. As described above, the code corresponding to the desired content is input to the receiver as a normal message.

Next, in order to read the data received and stored in this way, the one-chip CPU 100 supplies the first address information of the corresponding message data to the RAM 300 from the signal line SO by pressing the read switch S1. , The chip enable signal line CS1 (negative logic) to the logic "0" level, the chip select signal line CS2
(Negative logic) (this is a signal line for selecting the LCD driver 200) and the signal line A / D (negative logic) are set to the logic "1" level. Next, the signal line A / D (negative logic) is set to the logic "0" level, and the signal line R / W (negative logic) is set to the logic "1" level. As a result, the data corresponding to the above-mentioned first address is X.
The data is read from the memory array 340 via the Y decoder 330 and the data is read from the serial interface 3
It is supplied to the one-chip CPU 100 via the signal line SI via 10. In this way, when the data is read from the RAM 300 and supplied to the 1-chip CPU 100, the signal line CS1
(Negative logic) and the signal line C / D (negative logic) are set to the logic "1" level, and the chip select signal line CS2 (negative logic) is set to the logic "0" level to select the LCD driver 200. The character conversion instruction and the storage address information are supplied to the LCD driver 200 from the signal line SO. Subsequently, the 1-chip CPU 100 sets the data read from the RAM 300 to the signal line S by setting the signal line C / D (negative logic) to the logic “0” level.
O is supplied to the LCD driver 200.

As a result, the LCD driver 200 shown in FIG.
In the case of the information which is serial-parallel converted by the serial interface circuit 295, when the signal line C / D (negative logic) is at the logic "1" level, the command decoder 27
0, the command decoder 270 generates an internal control signal. Here, if the command is a write command or a character conversion command, the data pointer 280 is accessed to set the write address, and when the signal line C / D (negative logic) becomes the logic “0” level, the serial interface 295. The data input via the character generation circuit 290 is converted into a pattern of a 5 × 7 dot matrix by the character generation circuit 290 and written in the data memory 250, and is also controlled by the LCD timing controller 240 via the column driver 210 and the row driver 220. Signal C is displayed on the LCD 90.

E) Registration / Changing of Common ID The operation of the receiver will be described with reference to FIGS. 3, 10, and 11. 3 is a partially modified configuration between the decoder 40 and the message processing unit 60 (the configuration example of the one-chip CPU 100 is FIG. 11) in FIG.
Decoder 8 (also a 1-chip CPU in this example)
Is used, and the configuration is shown in FIG. 10). Now, when the preamble signal P is received while the voltage is applied to the radio section 20 and the waveform shaping circuit 30 of the receiver operating in the BS in the switching circuit 1, the following predetermined synchronization signal SC is detected. The BS operation is stopped for a sufficient period of time. Then, when SC is detected during this time, the detection pulse DT2 activates the one-chip CPU 100 and the decoder 8 via the interrupt port 107, and the decoder 40 writes the individual selective call number of its own machine from the detection of SC as a starting point. The data in the P-ROM 50 and the received data are compared and collated bit by bit.

In this way, if the received data matches the own calling number in the P-ROM 50, the detection signal DT3 is input from the input port 121 in FIG.
As a result, the CPU activated by the SC detection pulse DT2
1 instead of input port 119 at the time D should be detected
It is judged that the input is from 21, and the detected ID is recognized as the individual selective call number, and the system prepares for reception of the message signal sent subsequently. That is, 1-chip CPU 100
Then, the signal following the ID is read from the input port 106 at the clock CL and written in the RAM 180 via the data bus 120 and the accumulator ACC 170. In this way, every time 31-bit data forming the BCH (31, 21) code is input, the ALU 150 performs an operation.
Decode the received signal. Of the 31 bits that have been decoded, 20 information bits are decoded according to FIG. 4 [IV], and thereafter, B of the receiver is output via the output port 112.
Control S operation. At this time, if the 20 information bits have the following pattern, "110100
000000000110010 "indicates that the call has message information composed of a 7-bit unit code afterwards, and indicates that the BS operation needs to be canceled for 32 words. That is, the 1-chip CPU 10
0 sets and starts a 32-word timer.

Then, the signal I is decoded after waiting for the input of the next 31 bits. The 20-bit information area thus obtained is analyzed in accordance with FIG. 4 [V], Table 1 and Table 4. That is, if the information bit has the following pattern, "11000100011001000110110",
Some message data that follows is registered as a common ID, which means that the current time is PM 2:36 minutes. Therefore, the built-in clock of the 1-chip CPU 100 is calibrated, and the subsequent message data is decoded in 31-bit units, and 20 bits therein are decoded in 7-bit units. Here, if the pattern of the 20-bit information area of the received message is as follows, Table 6 (I), 6
(II) (ISO 7-bit code correspondence table, ISO646
By more extraction)

[0037]

[Table 6]

Sony brand, ID "01101 ... 01"
1011 ”is registered, but the one-chip CPU 100 is RA
A label of Sony is attached to an empty number of the common ID area of M300, and the corresponding number and ID pattern of the ID area are transferred to the decoder 8.

[0039]

[Table 7]

[0040]

[Table 8]

That is, the chip select CS4 (negative logic) is set to the logic "0" level, and the system clock SCK is set.
(Negative logic) and serial output SO from the common ID area number (for example, 0110 = 6) and the ID pattern “0110”.
1 ... 011011 ”is output. At this time, the decoder 8
Since the chip enable CE (negative logic) becomes logic "0", it prepares for reception, and the data input together with the subsequent system clock is transferred from the serial input SI through the serial interface 108 and the data bus 120 to the R level.
Register as the sixth ID in the AM 180. If the pattern of the information bits of the received signal I is as follows, "110000100101000110"
000 ”, the following message data has a common ID to be changed, and the time of transmission is AM 11:30. If the pattern of the 20-bit information area of the received message is as follows, 1 chip C in FIG.
PU100 is

[0042]

[Table 9]

The area corresponding to the TDK of the label of the common ID area of the RAM 300 is searched, the area is changed from TDK to NEC, the chip select CS4 (negative logic) is set to the logic "0" level, and serialized with the system clock SCK (negative logic). The output SO outputs the common ID area number and the ID pattern “011010 ... 0111”. As a result, the input data is written in the area corresponding to the ID number in the RAM of the decoder 8. In this way, when the detection of SC is confirmed in the state where the common ID is registered in the decoder 8, in FIG. 10, the decoder 8 is supplied with the clock CL corresponding to the transmission speed from the input port 105.
The data D following the SC is read from the input port 106, the contents of the predetermined program memory 140 are translated by the instruction decoder 160, and the instructions are processed in accordance with each instruction. That is, the above-mentioned read data is stored in the RAM 18 in advance in the ACU 150 via the data bus 120.
Each bit is compared and collated with the common ID (a plurality if there are a plurality) registered in 0. Then, if a match with the common 1D is confirmed, the data detection information DI is output port 1
13 to 1-chip CPU 10 in the message processing unit 60
0 (FIG. 11) and the detected ID is common I
Information DE indicating the number of the D area is output port 11
Output from 4 to 1-chip CPU 100.

The one-chip CPU 100 recognizes that the common ID is received by the signal from the input port 119 during the fixed period required for ID detection from the interrupt activation by the detection pulse DT2 of the SC, and the subsequent common ID area information is input to the input port 120. Read from. As a result, in order to store the received message data in the RAM 300, the chip select CS1 (negative logic) is set to the logic “0” level and the input port 120 via the serial interface 108.
The address information corresponding to the data from is transferred from the signal line SO. At this time, the one-chip CPU 100 sends the system clock by SCK (negative logic) and, at the same time, sets the signal line A / D (negative logic) to the logic "1" level in order to specify the address. In this way, when the address setting of the RAM 300 is completed, the received message data is written from the signal line SO to the designated address area of the RAM 300 with A / D (negative logic) at the logic "0" level.

Further, when the received message data is output to the outside, the chip select CS3 (negative logic) is set to logic "0" and the structure of one character is output from the output port 122 to the level shift circuit 3 in the format shown in FIG. Output. Here, if a signal processing unit connectable to the external terminal 5 of the receiver is used, it is possible to add desired processing to the data received via wireless. Here, since the receiver has an individual selective call number as an ID and a common ID, it is conceivable that the message storage areas of the RAM 300 are individually provided. Then, if it is desired to change the distribution of the area, it can be arbitrarily set by using the MCS pattern of the signal I and the message data.

[0046]

As described above, according to the present invention, at least a frame synchronization signal, a selective calling signal, a control signal and a message signal are arranged in this order, and a predetermined code of the control signal is used. Depending on the contents of the subsequent message signal, a wireless selection that can receive message information equipped with means for calibrating the built-in clock (built-in calendar) installed in the receiver and means for issuing an alarm at the time specified by the message signal A call receiver can be provided. Moreover, since the frame synchronization signal (FIG. 4II) and the designation signal (FIG. 4V) are received to calibrate the time, it is possible to calibrate a plurality of receivers at the same time on a regular basis. It has an effect that there is no difference in time information.

[Brief description of drawings]

FIG. 1 is a block diagram of a wireless selective calling receiver with display.

FIG. 2 is a block diagram of a message data processing unit 60.

FIG. 3 is a second block configuration diagram of a wireless selective calling receiver with display.

FIG. 4 is a signal configuration diagram.

FIG. 5 is a time chart during normal operation and when the power is turned on after the preamble signal.

FIG. 6 is a block diagram showing a detection circuit for a synchronization signal and an end signal.

FIG. 7 is a block diagram showing an address detection circuit.

FIG. 8 is a circuit configuration diagram of a buffer 70.

FIG. 9 is a block configuration diagram of a one-chip CPU 100.

FIG. 10 is a block configuration diagram of a 1-chip CPU 8.

11 is a chip C in the message processing unit 60 of FIG.
It is a block diagram of PU100.

FIG. 12 is a block diagram of an LCD driver 200.

13 is a block diagram of an external RAM 300. FIG.

FIG. 14 is a block diagram of a switching circuit 1.

15 is a diagram showing an output data format from the data input unit 2. FIG.

16 is a configuration diagram of a level shift circuit 3. FIG.

17 is a diagram showing a key layout of the data input unit 2. FIG.

FIG. 18 is a diagram showing an example of a display indicating that a setting alarm has been issued.

FIG. 19 is a diagram showing that the battery is turned on in a time slot (G7) of a group to which the own device belongs, as an example of battery saving.

[Explanation of symbols]

 1 Switching Circuit 2 Data Input Section 3 Level Shift Circuit 6 Battery 7 Booster Circuit 8 Decoder 10 Antenna 20 Radio Section 30 Waveform Shaping Circuit 40 Decoder 50 P-ROM 60 Message Data Processing Section 61 and 62 Diode 63 and 64 Capacitor 70 Buffer 80 Alarm Horn (Transmission Means) 90 LCD 100 1 Chip CPU (Message Decoder) 101 / 110-118 Output Port 102-106 / 119 Input Port 107 Interrupt Port 108 Serial Interface 120 Data Bus 130 Program Counter 140 Program Memory 150 ALU 160 Instruction Decoder 170 ACC 180 RAM 190 System clock generation circuit 200 LCD driver 210 Column driver 220 Row driver 230 LCD voltage controller 240 LCD timing controller 250 Data memory 260 System clock controller 270 Command decoder 280 Data pointer 290 Character generation circuit 295 Serial interface 300 External RAM 310 Serial interface 320 Address counter 330 XY decoder 340 Memory array 350 Control Circuit 500 Shift register 510-530 Inverter 540 AND gate 600 Counter 610 EXNOR gate 710/720 Resistor 730 NPN transistor 740 PNP transistor 800 Alarm horn 1a PNP transistor 1b and 3c NPN transistor

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[Procedure amendment]

[Submission date] March 1, 1995

[Procedure amendment 4]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

FIG. 18

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

[Figure 10]

FIG. 14

FIG. 15

FIG. 16

FIG. 11

[Fig. 12]

[Fig. 13]

FIG. 17

FIG. 19

Claims (2)

[Claims] 1. A radio paging receiver, which receives a paging signal composed of a frame synchronization signal, a selective paging signal, a designation signal and a message signal, decodes the designation signal in response to detection of the frame synchronization signal. A wireless selective call receiver with a message, comprising: a first means; and a means for calibrating the calendar or time based on the content of the decoded designated signal. 2. The radio selective calling receiver according to claim 1, wherein when receiving and storing the message signal, a time of a clock mounted on the receiver is added to the received message and stored as the reception time. A wireless selective calling receiver with a message, characterized by being provided with means for performing.