JPH0535611B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a signal transmission system for wireless selective calling that is capable of multi-address support, improved paging services, and message reception. [Prior art] With the development of integrated technology in recent years, wireless selective calling receivers have changed from conventional calling only to numbers and numbers.
The functionality has improved dramatically to the point where it can even receive a series of messages consisting of letters and symbols. [Problems to be Solved by the Invention] By the way, wireless selective calling receivers are always carried nearby due to their nature. Therefore, if the receiver has a display with a large amount of message memory, it is conceivable to use the memory of the receiver as a memo pad (so-called electronic memo pad). However, when using the device in this way, if data is input into the device using a keyboard or the like, it is not possible to downsize the device. Furthermore, in portable devices such as pacing receivers, longer lifespan of the power supply is an essential requirement as well as miniaturization. However, conventional signal transmission methods (e.g.
In the POCSAG system (especially with the alpha numeric function), even when a message unrelated to the machine is being transmitted, the time slot of the group to which the machine belongs enters reception mode and performs address verification (Figure 19). Therefore, in a system in which long messages are frequently handled, power consumption in the receiver that is unrelated to the transmitted messages cannot be ignored. By the way, in an asynchronous system, there is a prefix signal at the beginning of the transmitted signal to start up the receiver that is in an intermittent receiving state, but when the receiver comes out from inside an underground building or the like, or when the power is turned on. It is conceivable that the data after the time prefix signal continues for a while. In such a case, the receiver in the intermittent reception state cannot wake up until the prefix signal is present, so there is a drawback that even if the receiver's own selective call signal is present in the data, it cannot receive it. This becomes a very serious problem when a long message signal continues in one prefix signal. This accelerates the above-mentioned drawbacks in message services in paging services in recent years. In other words, the feature of the paging service is that it is a wireless service that takes advantage of its one-way communication to make effective use of channels.
Message supplementary services in recent years have tended to lose their major features. On the other hand, for paging service companies, stock price information and various commodity transaction information services can be considered as services that effectively utilize the immediacy of the system by adding a message transmission function. The problem with providing these services is the addresses assigned to each company or product (hereinafter these addresses will be referred to as common addresses).
Due to its nature, cancellation of registration and changes for each user is likely to occur extremely frequently. Therefore, if a service company were to register, change, or cancel a common address, the user would have to go to the service company each time, causing inconvenience. On the other hand, in addition to the complexity of counter operations at service companies, if a user who has registered monthly once unilaterally defaults on service fees, the base station can cancel the individual address, but the common address cannot be cancelled. This is a problem because the service cannot be stopped because it would cause inconvenience to other legitimate users, and it is also not possible to change the number correspondence of the common address, so it is necessary to deal with it individually. SUMMARY OF THE INVENTION An object of the present invention is to overcome the above-mentioned drawbacks and to provide a signal transmission system for radio selective calling that is suitable for message services. [Means and effects for solving the problem] According to the present invention, at least a synchronization signal for synchronizing frames, a selective calling signal for selectively calling individual receivers, and processing of subsequent messages. specifying a code, decoding the subsequent message signal according to a predetermined procedure and instructing data processing, calibrating the receiver's clock according to the contents of the subsequent message signal, and performing battery saving operations. It is possible to realize a signal transmission system for wireless selective calling compatible with a message service, which is composed of a control signal for controlling a message signal and a message signal in this order. [Example] The present invention will be described in detail below. FIGS. 1 and 3 are block diagrams of receivers according to the present invention. An overview of the operation of this receiver will be explained using FIGS. 1, 4, and 5. That is, in the switching circuit 1, as shown in FIG.
A state in which the voltage waveform shown in j is intermittently applied to the wireless section 20 and the waveform shaping circuit 30 to ensure efficient operation of the power supply (this operation is generally referred to as battery saving, hereinafter referred to as "BS"). When a desired radio frequency arrives while a voltage is being applied at
0, a received signal as shown in a of FIG. 5A is detected. Here, if the receiver has an individual selective calling number (hereinafter referred to as "ID") "Al", a preamble signal (hereinafter referred to as "P") for canceling BS is detected by the decoder 40. DT
1, BS is released and voltage is continuously applied to the wireless section. In this way, the programmable read-only memory [P-
The contents of ROM〕50 and the received signal are compared and verified.
Following the ID signal, the message signal is processed by the DT 3 and the message data (hereinafter referred to as "MD") processing unit 60 where the match is confirmed. The signal d drives a transmission means (for example, an alarm horn) via the buffer 70, the signal c displays the contents of the received message data on a liquid crystal display (LCD) 90, or the signal g drives a terminal. 5. Here, since a central processing unit (CPU) that requires limited processing capacity and a dynamic drive type LCD drive usually require a voltage of 2V or more, a booster circuit 7 is used to boost the voltage of the battery 6. ing. Now, each component P, SC, of the above-mentioned received signal a,
Details of ID and MD are shown in FIG. As shown in the figure, the preamble signal P is a repeating pattern of logic "1" and "0", the frame synchronization signal SC is a specific pattern shown in the figure, and the individual selective call number ID is as shown in the figure. In the configuration pattern shown in the figure, the MSB (identification bit) is a BCH31, 21 code having an inter-code distance of 5 and the logic "0", and the message data MD has the configuration pattern shown in the same figure, and the MSB (identification bit)
is given as logic “1”, and Fig. 5A, ,A,
As shown in FIG.
control signal "I" and information message M. That is, the first control signal shown in Fig. 4 is (i) "1" when there is a message addressed to the aircraft;
Code Z0 as message information, which is indicated as “0” if there is no code, and (ii) Information specifying the format of the following message (for example, “001” if the message is numerical information consisting of a BCD code, ASCII code compatible message) (3) code Z1 from the first control signal as shown in Figure 5A. BCD code Z2, which represents the number of words when 31 bits are one word, as duration information that specifies the time until the next SC, T, or I.
- Consists of Z5. The second control signal indicated by V in FIG. 4 is composed of a signal "MCS" for specifying processing of the received message, and a signal "TS" representing time or date information. Here, Table 1 that defines message processing corresponding to the MCS pattern is as follows. First, item 1 means that no processing is performed on the received message. Items 2 and 3 indicate setting the ID corresponding to the received message as the own device's ID, or conversely changing the ID registered in the own device.
Item 4 sets the built-in clock to the time corresponding to the received message and sounds a call alarm. Item 5 secures the memory area of the message memory area according to the ID and byte information corresponding to the received message. Item 6 is that the receiver receives the time from the start of BS to SC detection as a message signal, and if the SC cannot be detected within that time, it uses some means (for example, sounds an alarm horn with a different sound than the normal ring tone). (make a sound) to warn you. Items 7 and 9 arrange and output the contents of the received message according to a predetermined format (see Tables 5 and 6). Item 8 processes the TS shown in Figure 4 as month/day information. Note that TS usually represents time information, and the code structure in each case is shown in Table 2.
Next, the pattern in Figure 4 is the signal a in Figure 5 A.
This corresponds to signal E in , and is used as an end signal. Now, the decoder 40 in FIGS. 1 and 3
As shown in FIG. 6, the SC detection circuit takes in the received signal into the shift register 500 in series with a clock, and determines whether or not the read 31 bits are a predetermined desired pattern. That is, if the pattern is a desired one, a match signal is output from the AND gate 540. Also
As shown in FIG. 7 as an ID detection circuit, a received signal a and a signal e from a P-ROM 50 in which the calling number of the own device is written in advance are input to an EXNOR (exclusive nor) 610, and a 1-bit The matching output is input to the counter 600. As a result, the own device is called by the detection pulse that is output when the number of matching inputs reaches a preset value. Next, the buffer 70 is provided with a circuit configuration using transistors, for example, as shown in FIG. The message processing unit 60 in FIG.
CPU (message decoder) 100, random
Access memory [RAM] 300, and
It consists of an LCD driver 200. RAM3
00 is a diode 61 and a large capacitor 63
The backup circuit, which consists of the following, allows data protection even when replacing batteries. Message processing unit 60 in FIGS. 1 and 3
The configuration of one chip CPU 100 is shown in Figure 9, respectively.
This is shown in FIG. The decoder 8 in FIG. 3 is provided by a one-chip CPU shown in FIG. 10, and the functions of each block are as follows. 102-106, 119-121 are input ports, 101, 110-118, 122 are output ports, 107 is an interrupt port, 108 is a serial interface, 120 is a data bus, 130
is a program counter indicating the contents of the address, 140
160 is a program memory in which a sequence of instructions to be executed is stored and reads out the contents of the address specified by the program counter 130; 160 is a program memory that decodes information from the program memory 140 and supplies control signals corresponding to the instructions to each section; an instruction decoder 150 for performing arithmetic operations;
ALU that performs various operations such as logical operations
(Arcthmetic and Logic Unit) 180 is a RAM used for storing various data, saving program counts and program status in subroutines and interrupts, and used to store the calculation results of ALU 150 and for sending and receiving data between each port of RAM 180. ACC (Accumulator)
190 is a system clock generation circuit that determines the execution instruction cycle time. Next, the LCD driver 200 is given by the block configuration shown in FIG.
A serial interface 270 serially connects data to and from the serial interface 295, a command decoder 270 that takes in and decodes commands input through the serial interface 295, and controls each part according to the contents of the command; A character generation circuit 280 generates a 5×7 dot matrix pattern in response to input data; 280 is a circuit for writing data from the serial interface 295;
250 is a character generation circuit 290;
A data memory 220 stores display data from the serial interface 295 or the output from the serial interface 295.
A row driver 210 performs row control of the LCD.
The column driver 230 performs column control of the LCD.
The LCD voltage controller 240 controls the voltage to the LCD, and 240 controls the LCD drive timing.
LCD timing controller, and 260 is a system clock controller. Furthermore, the RAM 300 has the block configuration shown in FIG.
0 specifies the address of the memory array 340 by analyzing the data of the address counter 320, and X is used to write or read data in the memory.
-Y decoder, 340 is a memory array, and 350 is a control circuit. FIG. 14 shows the switching circuit 1 and a configuration example. FIG. 15 shows the data structure of the output signal g to the external terminal 5, with 11 bits per character. FIG. 16 is a circuit example of level shift 3. FIG. 17 is an example of the key arrangement of the data input section. The receiver and its operation in each case will be explained below. (a) When the desired signal is received after the power is turned on.As shown in Figure 5A, among the receivers in the BS state, the one whose ID corresponds to A1 detects the SC following the reception of P. , followed by signal T1
Compound. At this time, message data M1 follows, so Z0 is logic “1” and Z2 to Z5
The BS is canceled (OFF) for the period indicated by the BCD code (at least until the next SC, usually further up to A2 and T2). Furthermore, when "1000111" is received as the "MCS" pattern when decoding I1, the message data of M1 is decoded with the code corresponding to Z1, stored in the RAM 300, and sent to the LCD 9 via the LCD driver 200.
0, and the decoder 40 and buffer 70
The transmission means 80 is activated via the device to notify the device owner that he or she has been called. Also “TS” of I1
Calibrate the built-in calendar with the month and day information of the pattern. Then, the next SC, ID, T2, and I2 are detected and decoded. At this time, SC is detected, but since the ID signal is A2, it is not detected, so detection pulse DT3
It doesn't appear. Therefore, looking only at Z2 to Z5 of T2 and the "MCS" and "TS" patterns of I2, turn on BS (usually until before the next SC) for the period indicated by Z2 to Z5 after detecting the signal of I2, and , “MCS”
When the value is other than 1000111, the built-in clock is calibrated to the time corresponding to the "TS" pattern, and the reception time is added to the received and stored message. In this way, when it is time for the next SC, the BS will be activated again.
It becomes OFF. This period is different for IDF and A3, and since it is a calibration agent for the built-in clock, it will last until T3. Thereafter, such operations are repeated, and when the end signal E indicating the end of data is detected, the normal BS operation is resumed. In addition, the receiver whose ID corresponds to A3 detects SC after receiving P, but since the ID does not match at A1, Z2 to Z5 of T1 and
Look only at the “TS” pattern of I1. After the signal I1 is detected, the BS is turned ON for a period indicated by Z2 to Z5, and the built-in calendar is calibrated on the month and day that correspond to the "TS" pattern. Thus the next
At SC time, BS is turned off again until I2.
So, SC is detected but ID is not detected, so Z2 to Z5 of T2 and “MCS” and “TS” of I2
Just look at the pattern. And after the detection of I2 Z2~
While turning on the BS for Z5, "MCS"
If the value is other than 1000111, calibrate the built-in clock at the time that corresponds to the “TS” pattern. Of course, when the "MCS" pattern is 1000111, the built-in calendar is calibrated using the month and day information corresponding to the "TS" pattern. In this way, when it is time for the next SC, the BS will be activated again.
is turned OFF, and SC detection operation is started. and,
When SC and ID are detected, the BS OFF state continues for the period Z2 to Z5 at T3, and “MCS”
If the pattern is 1000011, the time corresponding to M3 decoded with the code corresponding to Z1 is recorded. When the built-in clock reaches the predetermined time, the transmission means 80 is transmitted via the decoder 40 and the buffer 70.
At the same time, a setting alarm is displayed on the LCD 90 (FIG. 18 is an example). Also, calibrate the built-in clock again using the time information corresponding to “TS” in I3. Thereafter, there is no ID that corresponds to A3, and when the end signal E is received, normal BS operation is resumed. By the way, in this embodiment, unless the end signal E is received, the signal T is checked regardless of whether the SC is received or not. Forcibly turns off the BS (about 1 minute in the example), shifts to SC signal reception, and if it cannot be detected, returns to normal
Return to BS operation, and if SC is not detected two or more times in a row, it is determined that there is an electric field failure, and normal operation is resumed.
By returning to BS operation, we are making effective use of the battery and increasing the reliability of reception. (b) When the power is turned on when the desired signal arrives In Figure 5B, the receiver with ID AN is powered on.
ON, the BS is turned off continuously for a predetermined period of time (approximately 1 minute in this example), and the desired SC is turned off.
Perform signal detection. When the SC signal is detected in this way, the ID is detected, but it is not received, so after I2 detection, according to the "MCS" pattern,
Calibrate the built-in calendar or clock using the "TS" information, and turn on BS for the period Z2 to Z5 of T2. Then, at the next SC, the operation of turning BS off again is repeated. In this way, when the ID corresponding to the AN is received, the BS for the period Z2 to Z5 of the TN
becomes OFF, and the IN “MCS” pattern
If it is 1000101, the message data MN is decoded and stored with the code corresponding to Z1 of TN. As a result, if SC is not detected before returning to BS operation and checking the elapsed time corresponding to the received data on the built-in clock, a warning will be issued to notify you that you are not in a good service area. (When detected, the timer stops and restarts when returning to BS), forces BS OFF for a predetermined period of time (approximately 1 minute in this example), and switches off SC.
Detection is performed, and if SC is not detected within the certain period of time, the operation of returning to BS operation is repeated. (c) Registering/reading fixed form information by manual input Select the desired key from the mode SW of data input section 2 (however, "CAL" or "TIME"
When a key is selected, the LCD 90 operates as a computer function or a clock function in conjunction with the CPU). If the "TEL" key is pressed here, an interrupt is generated from the K terminal of the interrupt port 107 in FIG. 9, and a pattern corresponding to the "TEL" key is input from the input port 102. As a result
The CPU confirms that the device is set to “TEL” mode, and then inputs data from the input port 103, such as “DATA IN”, “AOKI”, “DATA IN”.
IN”, “NEC”, “DATA IN”, “03−262−
5174”, “DATA IN”, “KUDO”, “DATA
IN”, “SONY”, etc. are input. When the result of key input is confirmed in this way, it is read out according to the predetermined format (see Table 5), and first the “DATA OUT” key is pressed. and “AOKI”
will be displayed on the LCD, then press the “→” key.
When “NEC” presses the “→” key again, “03−262
−5174”, and then press the “→” key to select “KUDO”,
Next, press the “↓” key to confirm “ENDO,” press the “→” key to confirm “KDD,” and press the “↓” key to confirm “SONY.” Similarly, when the "MEMO" key is pressed, an interrupt is generated from the K terminal of the interrupt port 107 in FIG. 9, and the pattern "0010011" corresponding to the "MEMO" key is input from the input port 102. As a result, the CPU determines that the device is set to “MEMO” mode, and from now on input port 103
The following data input from “DATA
IN”, “FEB.10.1984 SCHEDULE”, “DATA
IN”, “9:00”, “DATA IN”, “MEETING”
(NEW PRODUCT) AT 5-1”, “DATA
IN”, “10:30”, …], press the “DATA OUT” key to read out the data as shown in Table 6.
“FEB.10.1984 SCHEDULE” on LCD90
is displayed, and when you press the “→” key, the LCD display changes to “9:00”, and when you press the “→” key again, the display changes to “MEETING (NEW PRODUCT) AT”.
5-1” and press the “↓” key again to display “TEL”.
(NTT MR KUDO)", and you can check the necessary information at any time with a simple operation instead of a memo pad. Furthermore, since this receiver has a built-in calendar and a built-in clock, "FEB.10" At "9:00", "10:30", etc., the receiver's transmission device (for example, an alarm horn) is activated to alert the user, and a display corresponding to the sound time is displayed on the LCD 90. For example 18:
At 00 o'clock, "GINZA (MORE)" will be displayed on the LCD. (d) Registration of fixed form information by radio The operation of the receiver will be explained using FIGS. 1, 9, 12, and 13. When voltage is applied to the radio unit 20 and waveform shaping circuit 30 of the receiver operating BS in the switching circuit 1, when a preamble signal P is received, a subsequent predetermined synchronization signal SC is applied.
BS shall be OFF for a period sufficient to detect. When SC is detected during this period, the 1-chip CPU 100 is activated via the interrupt port 107 with the detection pulse DT2, and the decoder 4
0 shifts to ID detection operation. That is, SC
Starting from the detection of DT3, the data in the P-ROM 50 in which the ID number of the own machine is written is compared bit by bit with the received data (Fig. 7), and when a match is confirmed, the detection pulse DT3 is 1 chip CPU 10 via input port 121
0 and a clock CL corresponding to the transmission speed is supplied from the input port 105.
At this time, if DT3 is input after a predetermined period of time (time until DT3 is detected) from the interrupt activation by DT2, it is determined that the ID has been detected, and if not, it is determined that the ID does not match, and the subsequent Be prepared to receive the signal. Result 1
In the chip CPU 100, the message signal D is read from the input port 106 by the clock CL, the contents of the predetermined program memory 140 are translated by the instruction decoder 160, and processed in accordance with each instruction. That is, the read signal is connected to the data bus 120, ACC
170 to RAM 180. 31 thus forming the BCH31,21 code
Every time a bit is input, the ALU 150 performs an operation and decodes the received signal. 1 chip CPU 100 is the first decrypted
The 20 information bits of the BCH31 and BCH21 codes are decoded according to FIG. 4, and thereafter the BS operation of the receiver is controlled via the output port 112. At this time, if the 20-bit information bits have the following pattern, "1 1010 0000
0000 0010 0000" call with a message,
The message data is composed of 7 bits,
At least 20 words (where 1 word is 31)
Indicates that the BS between bits) needs to be released. Then, the signal I is decoded using the next 31 bits input. In this way, the 20-bit information area is analyzed according to Table 1 and Table 2 of Figure 4. In other words, if the information bit has the following pattern, "1 1000 1100 1010 0010 0000" indicates that the subsequent message data will be processed in the telephone directory mode, and the data transmission time will be
AM10: Indicates 20 minutes. Subsequent messages are processed in accordance with the control contents decoded in this way. Therefore, the information area (20 bits of data) decoded in units of 31 bits is decoded in units of 7 bits and sequentially stored in the external RAM 300. That is, by setting chip select 1 to the logic level "0" level, the RAM 300
is set to the operation mode, and the corresponding address information is transferred via the serial interface 108 via the signal line SO to determine which address in the RAM 300 is to be written. At this time, the 1-chip CPU 100 sends the system clock to the RAM 300 and at the same time sets the signal line A/ to logic "1" level to indicate an address. At this time, in FIG. 13, the RAM 300 determines that the signal input from the signal line S0 is an address signal according to each input control signal (, A/, R/), and the address counter 320,
The address to be written in memory array 340 is specified via X/Y decoder 330. Next, in the 1-chip CPU 100, the message data to be written is sent to the serial interface 1.
08 signal line S0, the signal line A/ to indicate that the data to be sent is message data is set to logic "0" level, and the signal line R/ is set to logic "0" level to instruct writing. . As a result, the RAM 300 in FIG. 13 uses the data input via the signal line S0 as message data in response to each input control signal, and sends the data input via the X/Y decoder 330 to the previously specified memory array 340. write to the specified address. When message data is sequentially decoded in the above process, if SC or end code is detected in BCH31, BCH21 unit, or if two consecutive words cannot be received, 1 chip CPU1
00 determines that the message data has ended, and notifies the decoder 40 from the output port 110 via the signal line ME that the message has ended, and also sends a message via the output port 111 to the signal line ME.
AC drives the sound generation circuit of the decoder 40.
As a result, the alarm horn 80 sounds via the signal d and the buffer 70. Here, in the case of SC detection, the 1-chip CPU 100 repeats the same operation as described above, but when the end code is received or when two consecutive words are not received, the receiver returns to the BS operation. As described above, a code corresponding to the desired content is input to the receiver as a normal message. Next, to read the data received and stored in this way, by pressing the read switch S1, the 1-chip CPU 100 reads the first address information of the corresponding message data from the signal line S1.
0 to the RAM 300, and also sets the chip enable signal line 1 to logic “0” level.
Chip select signal line 2 (this is a signal line for selecting LCD driver 200) and signal line A/ are set to logic "1" level. Next, the signal line A/ is set to the logic "0" level, and the signal line R/ is set to the logic "1" level. As a result, data corresponding to the above-mentioned first address is sent to the X/Y decoder 330 in 1-byte units.
The data is read from the memory array 340 via the serial interface 3.
1 chip CPU100 via signal line SI through 10
supplied to When the data is read from the RAM 300 and supplied to the 1-chip CPU 100, the signal line 1 and the signal line C/ are set to logic "1" level, and the chip select signal line is set to select the LCD driver 200.
By setting CS2 to logic “0” level,
Character conversion instructions and storage address information are supplied to the LCD driver 200 from the signal line S0.
Next, the 1-chip CPU 100 connects the signal line C/
RAM by setting it to logic “0” level.
The data read from LCD driver 300 is supplied to LCD driver 200 via signal line S0. As a result, in the LCD driver 200 shown in FIG.
When the signal line C/ is at logic "1" level, the information serial-to-parallel converted is decoded by the command decoder 270, and the command decoder 270 generates an internal control signal. Here, if the command is a write command or a character conversion command, the data pointer 280 is accessed to set the write address, and when the signal line C/ becomes a logic "0" level, it is input via the serial interface 295. The data to be generated is sent to the character generation circuit 290.
It is converted into a 5×7 dot matrix pattern and written to the data memory 250, and also written to the LCD timing controller 2.
40, the signal C is displayed on the LCD 90 via the column driver 210 and the row driver 220. (e) Registration/change of common ID The operation of the receiver will be explained using FIGS. 3, 10, and 11. FIG. 3 shows a partially modified configuration between the decoder 40 and the message processing unit 60 (FIG. 11 for a configuration example of a one-chip CPU 100) in FIG. (In this example, a 1-chip CPU is used,
The configuration is shown in FIG. 10). Now, when voltage is applied to the radio section 20 and waveform shaping circuit 30 of the receiver operating BS in the switching circuit 1, the preamble signal P
When receiving SC, the BS operation is stopped for a period sufficient to detect a subsequent predetermined synchronization signal SC. If an SC is detected during this period, the detection pulse DT2 activates the 1-chip CPU 100 and the decoder 8 via the interrupt port 107, and the decoder 40 has its own individual selection call number written therein starting from the detection of the SC. The data in the P-ROM 50 and the received data are compared bit by bit. In this way, if the received data matches the individual calling number of the own device in the P-ROM 50, the detection signal DT3 is transmitted to the input port 121 in FIG.
Input from As a result, SC detection pulse DT2
The CPU that was activated in Prepare for reception. That is, in the 1-chip CPU 100, the signal following the ID is sent to the input port 10 by the clock CL.
6 is read and written to the RAM 180 via the data bus 120 and the accumulator ACC 170. In this way, each time the 31-bit data forming the BCH31, 21 code is input, ALU1
50 performs calculations and decodes the received signal. Of the 31 decoded bits, 20 information bits are decoded according to FIG. 4, and thereafter the BS operation of the receiver is controlled via the output port 112. At this time, if the 20 information bits have the following pattern, ``1
1010 0000 0000 0011 0010'', indicating that the call has message information consisting of a 7-bit code, and a 32-word BS
Indicates that the operation needs to be canceled. That is, the 1-chip CPU 100 sets and starts a 32-word timer. Then, with the next 31 bits input, the signal I
Performs decoding. The 20-bit information area thus obtained is analyzed according to FIG. 4 and Tables 1 and 2. In other words, if the information bit has the following pattern, "1 1000 0011 0010
0011 0110”, common to subsequent message data
There is something to register as an ID, and the current time is
PM2: means 36 minutes. Therefore, the built-in clock of the 1-chip CPU 100 is calibrated, and the subsequent message data is
It is decoded every 31 bits, and 20 of them are decoded into 7-bit units. Here, if the pattern of the 20-bit information area of the received message is as follows, then according to Table 3,

【table】 〓

Claims (1)

[Scope of Claims] 1. A calling signal transmission system comprising at least a frame synchronization signal, a selective calling signal for selectively calling individual receivers, and a message signal for message information, wherein the message signal indicates the duration of the battery of the receiver.
Message duration information for controlling a saving operation is added to the calling signal and transmitted, and the receiver responds to the message duration information and performs a battery saving function in accordance with the duration of the message signal. A signal transmission method for wireless selective calling suitable for a message service characterized by canceling the call. 2. A signal transmission system for radio selective calling suitable for a message service according to claim 1, characterized in that said message duration information is inserted between said selective calling signal and said message signal.