JPH07240518A - Vertical MOS semiconductor device and manufacturing method thereof - Google Patents
Vertical MOS semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH07240518A JPH07240518A JP6030304A JP3030494A JPH07240518A JP H07240518 A JPH07240518 A JP H07240518A JP 6030304 A JP6030304 A JP 6030304A JP 3030494 A JP3030494 A JP 3030494A JP H07240518 A JPH07240518 A JP H07240518A
- Authority
- JP
- Japan
- Prior art keywords
- body region
- resistor
- cell portion
- semiconductor device
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 210000000746 body region Anatomy 0.000 claims abstract description 44
- 238000009792 diffusion process Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 230000015556 catabolic process Effects 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract 1
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000000758 substrate Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【目的】 オン抵抗の上昇を招くことなく、高耐圧化さ
れた縦型ＭＯＳ半導体装置を及びその製造方法を提供す
る。
【構成】 セル部分の拡散領域６の最外周に該セル部分
の拡散領域を取囲むボディ領域１３を備え、該最外周の
ボディ領域は抵抗体２０を介して前記セル部分のソース
電極９に接続されている。
(57) [Summary] [Object] To provide a vertical MOS semiconductor device having a high breakdown voltage and a method for manufacturing the same, without causing an increase in on-resistance. A body region 13 surrounding the diffusion region of the cell portion is provided on the outermost periphery of the diffusion region 6 of the cell portion, and the body region of the outermost periphery is connected to a source electrode 9 of the cell portion via a resistor 20. Has been done.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、縦型ＭＯＳ半導体装置
及びその製造方法に係り、特に、パワーＭＯＳＦＥＴ、
又は絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）等
の縦型ＭＯＳ半導体装置及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS semiconductor device and its manufacturing method, and more particularly to a power MOSFET,
Alternatively, the present invention relates to a vertical MOS semiconductor device such as an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】図４は、従来の一般的なパワーＭＯＳＦ
ＥＴのチップ周辺部分の断面図である。Ｎ+ 型半導体基
板１には、ドレイン領域となるＮ- 型エピタキシャル層
２を有しており、エピタキシャル層２には、ＭＯＳＦＥ
Ｔの一単位となるセル６が多数、規則的に配列され、セ
ル部分を構成している。ＭＯＳＦＥＴの一単位となるセ
ルは、１個のＰ型のボディ領域６内にＮ+ 型のソース領
域５が形成され、多結晶シリコンからなるゲート電極８
に閾値以上の正電圧が印加されると、Ｎ+ 型のソース領
域５とＮ型のドレイン領域４間のチャネル領域の表面に
反転層が生じ、多数キャリアのチャネルが形成されＦＥ
Ｔはオン状態となる。2. Description of the Related Art FIG. 4 shows a conventional general power MOSF.
It is sectional drawing of the chip peripheral part of ET. The N + type semiconductor substrate 1 has an N − type epitaxial layer 2 to be a drain region, and the epitaxial layer 2 has a MOSFE structure.
A large number of cells 6, which are one unit of T, are regularly arranged to form a cell portion. A cell, which is one unit of the MOSFET, has an N + type source region 5 formed in one P type body region 6 and has a gate electrode 8 made of polycrystalline silicon.
When a positive voltage equal to or higher than the threshold value is applied to the FE, an inversion layer is formed on the surface of the channel region between the N + type source region 5 and the N type drain region 4, and a majority carrier channel is formed.
T is turned on.
【０００３】半導体基板１の側端部にはＮ+ 型のチャネ
ルストップ領域１１が拡散により形成され、その上部に
はシールド電極１０が配置されている。Ｐ型のボディ領
域１３は、ＭＯＳＦＥＴを構成するセル部分のボディ領
域６を取囲むように配置された最外周のボディ拡散領域
である。最外周のボディ領域１３は、逆バイアス時にド
レイン領域４とセル部分のボディ領域６間のＰＮ接合の
ドレイン領域側に広がる空乏層の曲率を緩和し、逆バイ
アス時のソース／ドレイン間の耐圧を高めるために設け
られたものである。An N + type channel stop region 11 is formed by diffusion at a side end portion of the semiconductor substrate 1, and a shield electrode 10 is arranged above the N + type channel stop region 11. The P-type body region 13 is an outermost body diffusion region arranged so as to surround the body region 6 of the cell portion that constitutes the MOSFET. The outermost body region 13 relaxes the curvature of the depletion layer that spreads to the drain region side of the PN junction between the drain region 4 and the body region 6 of the cell portion at the time of reverse bias, and increases the breakdown voltage between the source and drain at the time of reverse bias. It is provided to raise it.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら、係るパ
ワーＭＯＳＦＥＴあるいはＩＧＢＴ等の縦型ＭＯＳ半導
体装置においては、低いオン抵抗と共に、耐圧はなるべ
く高いことが好ましい。縦型ＭＯＳ半導体装置の耐圧を
向上させるには、半導体基板、特にボディ領域とドレイ
ン領域間のＰＮ接合のドレイン領域側の不純物濃度を下
げればよい。しかしながら、ドレイン領域側の不純物濃
度を下げると、縦型ＭＯＳ半導体装置のオン抵抗が上昇
してしまう。However, in the vertical MOS semiconductor device such as the power MOSFET or the IGBT, it is preferable that the breakdown voltage is as high as possible in addition to the low on-resistance. In order to improve the breakdown voltage of the vertical MOS semiconductor device, the impurity concentration on the semiconductor substrate, particularly on the drain region side of the PN junction between the body region and the drain region, may be lowered. However, if the impurity concentration on the drain region side is lowered, the on-resistance of the vertical MOS semiconductor device increases.
【０００５】本発明は、上記従来の事情に鑑みて為され
たものであり、オン抵抗の上昇を招くことなく、高耐圧
化された縦型ＭＯＳ半導体装置及びその製造方法を提供
することを目的とする。The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a vertical MOS semiconductor device having a high breakdown voltage and a method of manufacturing the same without causing an increase in on-resistance. And
【０００６】[0006]
【課題を解決するための手段】本発明の縦型ＭＯＳ半導
体装置は、セル部分の拡散領域の最外周に該セル部分の
拡散領域を取囲むボディ領域を備え、該最外周のボディ
領域は抵抗体を介して前記セル部分のソース電極に接続
されていることを特徴とする。A vertical MOS semiconductor device according to the present invention comprises a body region surrounding the diffusion region of the cell portion at the outermost periphery of the diffusion region of the cell portion, and the body region at the outermost periphery is a resistor. It is characterized in that it is connected to the source electrode of the cell portion through the body.
【０００７】本発明の縦型ＭＯＳ半導体装置の製造方法
は、セル部分のボディ領域と共に該セル部分を取囲む最
外周のボディ領域を形成する工程と、前記セル部分に多
結晶シリコンからなるゲート電極を形成すると共に前記
最外周のボディ領域付近に多結晶シリコンからなる抵抗
体を形成する工程と、セル部分のソース領域及びボディ
領域に金属配線電極を接続すると共に、該金属配線電極
は前記抵抗体の一端と接続し、前記抵抗体の他端は前記
最外周のボディ領域と接続する金属配線電極を形成する
工程とを備えたことを特徴とする。A method of manufacturing a vertical MOS semiconductor device according to the present invention comprises a step of forming a body region of a cell portion and an outermost body region surrounding the cell portion, and a gate electrode made of polycrystalline silicon in the cell portion. And forming a resistor made of polycrystalline silicon in the vicinity of the outermost body region, and connecting a metal wiring electrode to the source region and the body region of the cell portion, and the metal wiring electrode is the resistor. Forming a metal wiring electrode connected to one end of the resistor and the other end of the resistor to the outermost body region.
【０００８】[0008]
【作用】本発明の縦型ＭＯＳ半導体装置によれば、逆バ
イアス印加時には、最外周のボディ領域とドレイン領域
間の接合にリーク電流が生じ、このリーク電流は最外周
のボディ領域に接続された抵抗体を介してソース電極に
流れる。リーク電流により抵抗体ではオームの法則に従
った電位差が生じ、この電位差は、最外周のボディ領域
とドレイン領域間のＰＮ接合に印加される逆バイアス電
圧を低減することとなる。従って、抵抗体の電位差分だ
け耐圧を向上させることができる。According to the vertical MOS semiconductor device of the present invention, when a reverse bias is applied, a leak current is generated in the junction between the outermost body region and the drain region, and this leak current is connected to the outermost body region. It flows to the source electrode through the resistor. The leakage current causes a potential difference according to Ohm's law in the resistor, and this potential difference reduces the reverse bias voltage applied to the PN junction between the outermost body region and the drain region. Therefore, the breakdown voltage can be improved by the potential difference of the resistor.
【０００９】本発明の半導体装置の製造方法によれば、
抵抗体はゲート電極と同じ材料である多結晶シリコンで
形成され、その抵抗体に最外周のボディ領域とソース電
極とを接続する金属配線電極を設ければよい。従って、
従来の縦型ＭＯＳ半導体装置の基本的な製造工程を変更
することなく、マスクパターンを変更することのみで本
発明の半導体装置を製造することができる。すなわち、
製造コストの上昇を伴うことなく高耐圧化された半導体
装置を製造することが可能となる。According to the method of manufacturing a semiconductor device of the present invention,
The resistor is made of polycrystalline silicon which is the same material as the gate electrode, and the resistor may be provided with a metal wiring electrode connecting the outermost body region and the source electrode. Therefore,
The semiconductor device of the present invention can be manufactured only by changing the mask pattern without changing the basic manufacturing process of the conventional vertical MOS semiconductor device. That is,
It is possible to manufacture a semiconductor device having a high breakdown voltage without increasing the manufacturing cost.
【００１０】[0010]
【実施例】以下、本発明の一実施例について添付図面を
参照しながら説明する。図１は、本発明の一実施例のパ
ワーＭＯＳＦＥＴのチップ周辺の断面図であり、図２は
対応する部分のパターン図である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of the periphery of a power MOSFET chip according to an embodiment of the present invention, and FIG. 2 is a pattern diagram of a corresponding portion.
【００１１】本実施例は、従来の技術において図４を参
照して説明したＮチャネル型パワーＭＯＳＦＥＴを高耐
圧化したものであり、ＭＯＳＦＥＴを構成する基本的な
セル部分の配置は同じである。又、セル部分を取囲む最
外周のボディ領域を備えることも同様であり、同一の構
成要素には同一の符号を付して重複した説明を省略す
る。In this embodiment, the N-channel type power MOSFET described in the prior art with reference to FIG. 4 has a high breakdown voltage, and the arrangement of the basic cell portions constituting the MOSFET is the same. Further, it is also the same as the provision of the outermost body region that surrounds the cell portion, and the same components are designated by the same reference numerals and the duplicated description will be omitted.
【００１２】本実施例においては最外周のボディ領域１
３は、抵抗体２０を介してセル部分のソース電極９に接
続されている。抵抗体２０は、ゲート電極８と同様に多
結晶シリコンから形成されており、その一端が最外周の
ボディ領域１３へアルミから成る金属電極２１により接
続されている。抵抗体２０の他端は、同様にアルミから
成るソース電極９に接続されている。即ち、図２に示す
ように、抵抗体２０は、その一端がコンタクト２３を介
してアルミ配線２１に接続され、アルミ配線２１はコン
タクト２４を介して最外周のボディ領域１３に接続され
ている。抵抗体２０の他端は、コンタクト２６を介して
アルミから成るセル部分のソース電極９に接続されてい
る。ソース電極９は、セル部分において、コンタクト２
９を介して、単位となるＭＯＳＦＥＴを構成するそれぞ
れのセルのソース領域５及びボディ領域６に共通に接続
されている。In the present embodiment, the outermost body region 1
3 is connected to the source electrode 9 of the cell portion via the resistor 20. The resistor 20 is made of polycrystalline silicon like the gate electrode 8, and one end thereof is connected to the outermost body region 13 by a metal electrode 21 made of aluminum. The other end of the resistor 20 is connected to the source electrode 9 also made of aluminum. That is, as shown in FIG. 2, one end of the resistor 20 is connected to the aluminum wiring 21 via the contact 23, and the aluminum wiring 21 is connected to the outermost body region 13 via the contact 24. The other end of the resistor 20 is connected to the source electrode 9 of the cell portion made of aluminum via a contact 26. The source electrode 9 has a contact 2 in the cell portion.
9 are commonly connected to the source region 5 and the body region 6 of each cell constituting the unit MOSFET.
【００１３】金属電極２８は、コンタクト２７を介して
多結晶シリコンから成るゲート電極８に接続されてい
る。金属電極２８は、図示しないチップのゲート電極パ
ッドに接続され、ゲート電圧を多数のセルのゲート電極
８に均一に供給するためのものである。なお、抵抗体２
０は、例えば１本が１００ＭΩ程度のものをチップ全体
に１０本程度配置し、全体として１０ＭΩとしてもよ
い。又、より多数の抵抗体をセル部分の四周に配置して
もよい。又、抵抗体２０は図示の場合は長方形をなして
いるが、蛇行状の形状を用いてもよく、デバイスに要求
される特性、パターン形状から適宜選定される。The metal electrode 28 is connected to the gate electrode 8 made of polycrystalline silicon via the contact 27. The metal electrode 28 is connected to a gate electrode pad of a chip (not shown) and serves to uniformly supply a gate voltage to the gate electrodes 8 of many cells. The resistor 2
As for 0, for example, about 10 pieces each having about 100 MΩ may be arranged on the entire chip, and may be set to 10 MΩ as a whole. Further, a larger number of resistors may be arranged on the four circumferences of the cell portion. Although the resistor 20 has a rectangular shape in the illustrated case, it may have a meandering shape and is appropriately selected according to the characteristics and pattern shape required for the device.
【００１４】本実施例のパワーＭＯＳＦＥＴの動作につ
いて、次に図３を参照しながら説明する。図３（Ａ）
は、従来の抵抗体なしの場合の逆バイアス降伏直前の空
乏層３２Ａの広がりを示し、（Ｂ）は本発明の抵抗体２
０ありの場合の（Ａ）と同じ逆バイアスを印加した場合
の空乏層３２Ｂの広がりを示し、（Ｃ）は本発明の抵抗
体２０ありの場合の降伏直前の空乏層３２Ｃの広がりを
示す。ソース電極８を接地した状態で、ドレイン電極１
２に印加する電圧を上昇させて耐圧の試験を行なう際
に、ドレイン電極１２に例えば１００Ｖ程度の逆バイア
ス高電圧を印加する。（Ａ）の最外周のボディ領域１３
がソース電極９に直接接続されている場合には、ボディ
領域とドレイン領域４間のＰＮ接合のドレイン領域４側
の空乏層３２Ａが図示するように広がり、最外周のＰボ
ディ領域１３の角部近傍３０で電位傾度が最も高くな
り、降伏に至る。この際、図５に示すように、ＰＮ接合
に印加する逆バイアス電圧Ｖを上昇させていくと、ＰＮ
接合のリーク電流が徐々に増加し、降伏に至る。The operation of the power MOSFET of this embodiment will be described below with reference to FIG. Figure 3 (A)
Shows the spread of the depletion layer 32A immediately before the reverse bias breakdown without the conventional resistor, and (B) shows the resistor 2 of the present invention.
The spread of the depletion layer 32B when the same reverse bias as that in (A) with 0 is applied, and the spread of the depletion layer 32C immediately before breakdown with the resistor 20 of the present invention are shown. With the source electrode 8 grounded, the drain electrode 1
When the withstand voltage test is performed by increasing the voltage applied to 2, the reverse bias high voltage of about 100 V is applied to the drain electrode 12. Outermost body region 13 in (A)
Is directly connected to the source electrode 9, the depletion layer 32A on the drain region 4 side of the PN junction between the body region and the drain region 4 spreads as shown in the drawing, and the corner portion of the outermost P body region 13 is formed. In the vicinity 30, the potential gradient becomes the highest, leading to breakdown. At this time, if the reverse bias voltage V applied to the PN junction is increased as shown in FIG.
The leakage current of the junction gradually increases, leading to breakdown.
【００１５】しかしながら、（Ｂ）の最外周のボディ領
域６が抵抗体２０を介してソース電極９に接続されてい
る場合には、抵抗体２０に逆バイアス時のリーク電流Ｉ
が流れ、空乏層の広がりが（Ａ）の場合と変わってく
る。（Ａ）の場合の降伏電圧（１００Ｖ程度）直前の逆
バイアス電圧が印加された場合には、例えばリーク電流
が１μＡ程度であり、抵抗体２０の抵抗値が１０ＭΩ程
度であるとすると、１０Ｖの電位差が抵抗体２０の両端
に生じる。すなわち、ボディ領域１３の電位は接地電位
であるソース電極９よりも１０Ｖ程度高くなる。従っ
て、ボディ領域１３とドレイン領域４間のＰＮ接合にか
かる逆バイアス電圧は、（Ａ）の場合と比較して１０Ｖ
程度小さくなる。従って、（Ｂ）に示すように空乏層３
２Ｂの広がりは最外周のボディ領域１３の周辺において
緩和された形となる。更にドレイン電極１２へ印加する
逆バイアス電圧を上昇させると、（Ｃ）に示す空乏層３
２Ｃの広がりとなり、セル領域側のボディ領域６の角部
分近傍３１又は最外周のＰボディ領域１３の角部分３０
のいずれかで降伏が発生する。しかしながら、この降伏
電圧は、抵抗体２０のリーク電流に基づく電位差分だけ
高いものとなる。However, in the case where the outermost body region 6 in (B) is connected to the source electrode 9 via the resistor 20, the resistor 20 has a leakage current I in reverse bias.
Flow and the spread of the depletion layer is different from the case of (A). When the reverse bias voltage immediately before the breakdown voltage (about 100 V) in the case of (A) is applied, for example, if the leak current is about 1 μA and the resistance value of the resistor 20 is about 10 MΩ, then A potential difference is created across the resistor 20. That is, the potential of the body region 13 is higher than that of the source electrode 9, which is the ground potential, by about 10V. Therefore, the reverse bias voltage applied to the PN junction between the body region 13 and the drain region 4 is 10 V as compared with the case of (A).
It gets smaller. Therefore, as shown in FIG.
The spread of 2B is relaxed around the outermost body region 13. When the reverse bias voltage applied to the drain electrode 12 is further increased, the depletion layer 3 shown in FIG.
2C spreads, which is near the corner portion 31 of the body region 6 on the cell region side or the corner portion 30 of the outermost P body region 13.
Surrender occurs in any of the. However, this breakdown voltage is increased by the potential difference based on the leak current of the resistor 20.
【００１６】次に、本実施例のパワーＭＯＳＦＥＴの製
造方法について説明する。この製造方法は、従来のパワ
ーＭＯＳＦＥＴの製造方法とそのマスクパターンを変更
するのみで従来の製造工程をほとんど変更することなく
製造することができる。まず、多結晶シリコンからなる
ゲート電極８を形成する時に、最外周のボディ領域付近
に多結晶シリコンから成る抵抗体２０を同時に形成す
る。これは、多結晶シリコンのゲート電極８を形成する
マスクパターンにおいて、抵抗体２０を形成するパター
ンを合わせて設けておくだけでよい。尚、抵抗体２０の
抵抗値は、不純物のイオン注入量により制御できるの
で、セル領域側のゲート電極とこの抵抗体２０のシート
抵抗をそれぞれ異なる値に設定する必要がある場合に
は、一方をレジストマスクでカバーして別々にイオン注
入量を制御すればよい。そして、コンタクトの開口を行
なうマスクパターンと、アルミ膜の金属電極配線を行な
うマスクパターンとを従来のものから変更し、抵抗体２
０の一端を最外周のボディ領域１３に接続し、他端をソ
ース電極９に接続するようにすればよい。その他の製造
工程は、全く従来と同一である。Next, a method of manufacturing the power MOSFET of this embodiment will be described. This manufacturing method can be manufactured only by changing the conventional manufacturing method of the power MOSFET and its mask pattern without changing the conventional manufacturing process. First, when the gate electrode 8 made of polycrystalline silicon is formed, the resistor 20 made of polycrystalline silicon is simultaneously formed near the outermost body region. This only needs to be provided together with the pattern for forming the resistor 20 in the mask pattern for forming the gate electrode 8 of polycrystalline silicon. Since the resistance value of the resistor 20 can be controlled by the ion implantation amount of impurities, if it is necessary to set the sheet resistance of the gate electrode on the cell region side and the sheet resistance of the resistor 20 to different values, one of them should be set. The amount of ion implantation may be controlled separately by covering with a resist mask. Then, the mask pattern for forming the contact opening and the mask pattern for forming the metal electrode wiring of the aluminum film are changed from the conventional ones to make the resistor 2
One end of 0 may be connected to the outermost body region 13 and the other end may be connected to the source electrode 9. The other manufacturing process is completely the same as the conventional one.
【００１７】なお、以上に説明した最外周のボディ領域
とソース電極間に接続する抵抗体は、本実施例のような
多結晶シリコンを用いたものに限定されず、例えば半導
体基板表面に設けられた拡散抵抗を用いてもよい。又、
本実施例においては、パワーＭＯＳＦＥＴについて説明
したが、反対導電型の半導体基板を用いることによっ
て、ＩＧＢＴについても同様に適用できるのは勿論のこ
とである。このように、本発明の趣旨を逸脱することな
く種々の変形実施例が可能である。The resistor connected between the outermost body region and the source electrode described above is not limited to the one using polycrystalline silicon as in this embodiment, but is provided on the surface of a semiconductor substrate, for example. A diffused resistor may be used. or,
Although the power MOSFET has been described in this embodiment, it is needless to say that the power MOSFET can be similarly applied to the IGBT by using the semiconductor substrate of the opposite conductivity type. As described above, various modified embodiments are possible without departing from the spirit of the present invention.
【００１８】[0018]
【発明の効果】以上に説明したように、本発明によれ
ば、最外周のボディ領域とソース電極との間に抵抗体を
接続することにより、オン抵抗の増大等の問題を生じる
ことなく、縦型ＭＯＳ半導体装置の耐圧を向上させるこ
とができる。又、本発明の製造方法によれば、係る半導
体装置を従来の製造工程をほとんど変更することなく、
マスクパターンを少し変更するのみで容易に製造するこ
とが可能となる。As described above, according to the present invention, by connecting the resistor between the outermost body region and the source electrode, there is no problem such as an increase in on-resistance. The breakdown voltage of the vertical MOS semiconductor device can be improved. Further, according to the manufacturing method of the present invention, the semiconductor device can be manufactured without changing the conventional manufacturing process.
It is possible to easily manufacture it by only slightly changing the mask pattern.
【図１】本発明の一実施例の縦型ＭＯＳ半導体装置のチ
ップ周辺部分の断面図。FIG. 1 is a sectional view of a peripheral portion of a chip of a vertical MOS semiconductor device according to an embodiment of the present invention.
【図２】上記半導体装置の対応する部分のパターン図。FIG. 2 is a pattern diagram of a corresponding portion of the semiconductor device.
【図３】上記半導体装置の動作を説明するための断面
図。FIG. 3 is a cross-sectional view illustrating the operation of the semiconductor device.
【図４】従来の縦型ＭＯＳ半導体装置のチップ周辺部分
の断面図。FIG. 4 is a cross-sectional view of a peripheral portion of a chip of a conventional vertical MOS semiconductor device.
【図５】逆バイアス時の電圧と電流の関係の説明図。FIG. 5 is an explanatory diagram of a relationship between voltage and current during reverse bias.
Claims (2)
分の拡散領域を取囲むボディ領域を備え、該最外周のボ
ディ領域は抵抗体を介して前記セル部分のソース電極に
接続されていることを特徴とする縦型ＭＯＳ半導体装
置。1. A body region surrounding the diffusion region of the cell portion is provided on the outermost periphery of the diffusion region of the cell portion, and the body region of the outermost periphery is connected to a source electrode of the cell portion via a resistor. A vertical MOS semiconductor device characterized in that
を取囲む最外周のボディ領域を形成する工程と、前記セ
ル部分に多結晶シリコンからなるゲート電極を形成する
と共に前記最外周のボディ領域付近に多結晶シリコンか
らなる抵抗体を形成する工程と、セル部分のソース領域
及びボディ領域に金属配線電極を接続すると共に、該金
属配線電極は前記抵抗体の一端と接続し、前記抵抗体の
他端は前記最外周のボディ領域と接続する金属配線電極
を形成する工程とを備えたことを特徴とする縦型ＭＯＳ
半導体装置の製造方法。2. A step of forming an outermost body region surrounding the cell portion together with the body region of the cell portion, and forming a gate electrode made of polycrystalline silicon in the cell portion and near the outermost body region. And a metal wiring electrode is connected to the source region and the body region of the cell portion, the metal wiring electrode is connected to one end of the resistor, and the other of the resistor is formed. And a step of forming a metal wiring electrode connected to the outermost body region at the end thereof.
Manufacturing method of semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6030304A JPH07240518A (en) | 1994-02-28 | 1994-02-28 | Vertical MOS semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6030304A JPH07240518A (en) | 1994-02-28 | 1994-02-28 | Vertical MOS semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07240518A true JPH07240518A (en) | 1995-09-12 |
Family
ID=12300023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6030304A Pending JPH07240518A (en) | 1994-02-28 | 1994-02-28 | Vertical MOS semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07240518A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007005823A (en) * | 2006-08-28 | 2007-01-11 | Mitsubishi Electric Corp | Semiconductor device |
| KR100685091B1 (en) * | 2005-07-21 | 2007-02-22 | 주식회사 케이이씨 | Trench transistors and manufacturing method |
| WO2011102254A1 (en) * | 2010-02-16 | 2011-08-25 | 住友電気工業株式会社 | Silicon carbide insulated gate semiconductor element and method for producing same |
-
1994
- 1994-02-28 JP JP6030304A patent/JPH07240518A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100685091B1 (en) * | 2005-07-21 | 2007-02-22 | 주식회사 케이이씨 | Trench transistors and manufacturing method |
| JP2007005823A (en) * | 2006-08-28 | 2007-01-11 | Mitsubishi Electric Corp | Semiconductor device |
| JP4574601B2 (en) * | 2006-08-28 | 2010-11-04 | 三菱電機株式会社 | Semiconductor device |
| WO2011102254A1 (en) * | 2010-02-16 | 2011-08-25 | 住友電気工業株式会社 | Silicon carbide insulated gate semiconductor element and method for producing same |
| JP2011171374A (en) * | 2010-02-16 | 2011-09-01 | Sumitomo Electric Ind Ltd | Silicon carbide insulated gate type semiconductor element and method of manufacturing the same |
| US8901568B2 (en) | 2010-02-16 | 2014-12-02 | Sumitomo Electric Industries, Ltd. | Silicon carbide insulating gate type semiconductor device and fabrication method thereof |
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