JPH07211772A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE: To provide a semiconductor device, together with its manufacturing method, wherein the degree of process margin in the element separation process of high-integrated semiconductor device is improved, while a plagiarized element separation film is formed. CONSTITUTION: This semiconductor device comprises a semiconductor substrate 11 consisting of an active region and element separation region, a first region which positioned in the element separation region of the semiconductor substrate 11, having a surface which is lower than the surface of the semiconductor substrate 11, a second region, which positioned at both side surface parts of the first region, having narrower width and deeper depth than those of the first region, and an element separation film 22 embedded in the first region and the second region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an element isolation film for a semiconductor device having a flat surface and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, the process of forming an element isolation film on a silicon substrate is one of the important steps in the manufacture of semiconductor integrated circuits. Generally, a semiconductor device includes an active region separated by an element isolation region. Therefore, the density of the semiconductor integrated circuit is limited by the size of the element isolation region. This is more remarkable in a semiconductor integrated circuit such as an EEPROM in which a high voltage region exists on the integrated circuit chip.

In recent years, the most widely used conventional method for forming an element isolation region is LOCOS (Local Oxi).
The process is described as follows.

The active region of the semiconductor substrate is masked with a silicon nitride film. Subsequently, after performing channel stop ion implantation in the element isolation region between the active regions, only the element isolation region of the semiconductor substrate is selectively oxidized using the silicon nitride film as a mask to form a thick element isolation oxide film, that is, , Forming a field oxide film. At this time, the field oxide film is formed to a thickness of 5000 Å or more. With the field oxide film formed in this way,
The active areas on the silicon substrate will be separated.

However, the LOCOS process is not suitable as a device isolation method for a highly integrated semiconductor integrated circuit having sub-micro dimensions. The reason is,
During the oxide film process for forming the field oxide film, lateral oxidation (Lateral Oxidation) is formed below the silicon nitride film used as a masking layer.
n) occurs and an oxide film is formed even in the active region, resulting in a decrease in the active region. This is called the "bird's beak" phenomenon.

In the LOCOS process, the dopant into which the channel stop ions are implanted is laterally diffused into the active region in the high temperature heat treatment stage of the field oxide film process, which makes it difficult to form a device having a sub-micro size.

Another problem with the LOCOS process is that the thick field oxide forms an uneven surface. This will act as a factor that has an extremely adverse effect on the post process. The thick field oxide film causes a step difference of 5000 Å or more between the active region and the element isolation region adjacent thereto.

When the LOCOS process is applied to an element isolation process of a highly integrated semiconductor device, another problem that occurs is that as the semiconductor device is highly integrated, the sizes of the active region and the element isolation region also decrease. To do. As a result, the thickness of the field oxide film formed in the element isolation region between the adjacent active regions is limited. If the device isolation region is not sufficiently secured between the active regions, the electric field formed in the active region through the lower portion of the field oxide film of the device isolation region may affect the adjacent active regions. Can cause a malfunction. In order to prevent this, a method of performing so-called channel stop ion implantation, which increases the dose of channel stop ions implanted into the element isolation region before the oxidation process for forming the field oxide film, is used. This is used to prevent the electric field generated in the active region from being laterally diffused into the element isolation region by the channel stop ion implantation region formed in the element isolation region. However, increasing the ion dose during channel stop ion implantation will cause more lateral diffusion of the ions implanted during the field oxidation process, and will further penetrate into the channel region of the adjacent active region. This causes an adverse effect, which causes a junction breakdown voltage (jun
There is a problem that the action voltage breakdown is lowered.

In order to solve the above problems of the LOCOS process, various element isolation methods have been proposed. Among these, the element isolation method of the semiconductor device disclosed in US Pat. No. 5,229,315 will be described with reference to FIGS.

First, as shown in FIG. 1, after a pad oxide film 2 and a nitride film 3 are sequentially formed on a semiconductor substrate 1, a part of the nitride film 3 in an element isolation region is formed by a photolithography etching process. After selectively etching the pad oxide film 2 and the pad oxide film 2, a polysilicon layer 4 is formed to a constant thickness on a part of the exposed substrate and the entire surface of the nitride film 3, and field stop ion implantation is performed.

Subsequently, as shown in FIG. 2, after a planarizing insulating film 5 is formed on the entire surface of the polysilicon layer 4, the substrate surface is flattened by etching back until the polysilicon layer 4 is exposed. .

Next, as shown in FIG. 3, the polysilicon layer 4 is etched using the planarizing insulating film 5 as a mask, and the substrate exposed by the etching is etched to form a groove 7.

Subsequently, as shown in FIG. 4, after removing the flattening insulating film 5, an oxide film 8 is formed on the entire surface of the substrate in which the groove 7 is formed as described above.

Next, as shown in FIG. 5, the oxide film 8 is etched back so that the remaining polysilicon layer 4 is exposed.

Next, as shown in FIG. 6, the polysilicon layer 4 is oxidized and the nitride film 3 is removed to form a cylindrical element formed by being driven into a groove 7 formed in the substrate. The separation film 9 is formed.

According to the above technique, since the effective channel length of the parasitic field transistor is increased, the element isolation characteristic is improved, and a certain cylinder structure can be formed regardless of the pattern size. is there.

[0017]

However, in the above-mentioned conventional technique, the width of the silicon substrate during etching, that is, the width of the cylindrical separation film is reduced due to the process deviation due to the deposition and etchback of the planarization insulating film. There is a problem in that the surface of the isolation film 9 is not flat due to the oxidation of the polysilicon layer.

An object of the present invention is to solve the above problems, and to improve the process margin in the element isolation process of a highly integrated semiconductor device, and to provide a planarized element isolation film. It is to provide a semiconductor device that can be formed and a manufacturing method thereof.

[0019]

A semiconductor device of the present invention for achieving the above object is a semiconductor substrate comprising an active region and an element isolation region, and is located in the element isolation region of the semiconductor substrate, A first region having a surface lower than a surface of the semiconductor substrate; a second region located on both side surfaces of the first region and having a width narrower and a deeper depth than the first region; And an element isolation film formed by being embedded in the second region.

Further, in the method for manufacturing a semiconductor device of the present invention to achieve the above object, a step of forming a multi-layered insulating film on the semiconductor 11 and a step of selectively etching the laminated insulating film to form a laminated insulating film Forming a film pattern, etching a part of the semiconductor substrate exposed by the film pattern to a predetermined depth to form a primary recess region 17, and forming a sidewall insulating film 18 on a side surface of the laminated insulating film pattern. A step of forming a first oxide film on the primary recess region, a step of selectively removing the sidewall insulating film, and a step of removing the sidewall insulating film to expose an exposed semiconductor substrate. Etching a portion to a predetermined depth to form a secondary recess region 20, and
The method is characterized by including a step of forming a second oxide film 22 on the oxide film and the secondary recess region, and a step of selectively removing the laminated insulating film pattern.

[0021]

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. 7 to 14 show a method of manufacturing an element isolation film of a semiconductor device according to the present invention in process steps.

First, as shown in FIG. 7, a silicon substrate 1
1 is heat-treated in an oxidizing atmosphere at a temperature of about 950 ° C. for about 15 minutes to form a pad oxide film 12 having a thickness of about 200 Å, and then low pressure CVD (LPCVD: Lo
w Pressure Chemical Vapor
750 ° C. to 800 using the Deposition method.
A first nitride film 13 is formed on the pad oxide film 12 to a thickness of about 1500Å at a temperature of ℃. Then, as an etching stopper for the nitride film on the first nitride film 13,
For example, the oxide film 14 is formed to a thickness of about 500 Å by the CVD method or the PECVD method, and then the CVD film is formed thereon.
Of the second nitride film 15 using the PECVD method or the PECVD method.
It is formed to a thickness of about 0Å to 2500Å.

Next, as shown in FIG. 8, a photosensitive film is coated on the second nitride film 15, and then exposed and developed by a photolithographic etching process to form a photosensitive film pattern 16 on the active region of the substrate. Form. Next, the second nitride film 1 is formed using the photoresist film pattern 16 as a mask.
5, the oxide film 14, the first nitride film 13, and the pad oxide film 12 are removed by RIE (Reactive Ion Etch).
ing) and other anisotropic dry etching methods, and the exposed silicon substrate is etched to a depth of about 500 Å to 1000 Å to form a primary recess region 17. At this time, it is desirable to use a gas containing CHF ₃ or CF ₄ or the like for the nitride film and the oxide film and a gas containing HBr / Cl ₂ or the like for the silicon substrate as the etching gas in the etching process.

Next, as shown in FIG. 9, after the photoresist pattern is removed, the primary recess region 17 and the second recess region 17 are removed.
A third nitride film is formed on the entire surface of the nitride film 15 by the CVD method or the PEC.
After the VD method is used to deposit a film having a thickness of about 1000 Å to 1500 Å, the sidewall nitride film 18 is formed by etching back to a thickness not less than the thickness of the deposition.

Next, as shown in FIG. 10, a laminated pattern of insulating films consisting of the pad oxide film 12, the first nitride film 13, the oxide film 14, and the second nitride film 15 and the sidewall nitride film. 18 and O ₂ at temperatures above 850 ° C. using as oxidation mask, or H ₂ + O heat treated at ₂ oxidizing atmosphere, the exposed silicon substrate surface, i.e., about 500Å~ primary recess region 17 1 with a thickness of about 1000Å
Next field oxide film 19 is formed. At this time, the thickness of the primary field oxide film 19 is set so that the surface of the field oxide film is lower than the surface of the substrate in the element formation region or the active region.

Subsequently, as shown in FIG. 11, the sidewall of the nitride film and the second nitride film are selectively removed by anisotropic dry etching or the like to expose a predetermined portion of the surface of the silicon substrate.

Then, as shown in FIG. 12, a part of the exposed silicon substrate is covered with the insulating film laminated pattern 1.
Using the secondary field oxide film 19 as a mask, the secondary recess region 20 is formed by etching to about 1000 Å. Then, B ⁺ or BF ₂ ions are implanted into the surface of the exposed substrate of the secondary recess region 20 at a concentration of ² to 3 × 10 ¹³ / cm ² at an acceleration voltage of 40 to 80 KeV and the impurity diffusion layer 21. To form.

Continuing, as shown in FIG.
By performing thermal oxidation for 50 to 150 minutes in an oxidizing atmosphere containing O ₂ and H ₂ at a temperature of 00 ° C., the first
500 Å to 4000 in the secondary recess area and secondary recess area
A secondary field oxide film 22 having a thickness of about Å is formed.
At this time, in the secondary field oxide film 22, the thickest part of the field oxide film is about 1000 Å to 5000 Å by adding the thicknesses of the formed primary field oxide film 19 and the formed secondary field oxide film 22. By doing so, the thickness is set so that the surface of the field oxide film region, that is, the element isolation region does not become higher than the surface of the silicon substrate in the element region or the active region by 1000 Å or more.

On the other hand, as an embodiment of the present invention, the secondary field oxide film is not formed by a thermal oxidation process, and C
It is also possible to deposit the oxide film by the VD method or the LPCVD method and then etch back to form the secondary field oxide film filling the recess region.

Next, as shown in FIG. 14, the oxide film 1 is formed.
4, the nitride film 13 and the pad oxide film 12 are sequentially etched and removed to form the element isolation film 22 having a flat surface. In etching the oxide film 14, the nitride film 13 and the pad oxide film 12, a solution containing hydrofluoric acid (HF) is used in the case of an oxide film, and phosphoric acid (H ₃ PO ₄ ) is contained in the case of a nitride film. It is performed by a wet etching process using a solution.

[0031]

As described above, according to the present invention, the silicon substrate can be etched to have a constant width regardless of the pattern size when the element isolation film embedded in the substrate is formed. The process margin during substrate etching is improved, and the surface of the silicon substrate in the element region or active region and the surface of the element isolation region are flattened, ensuring focus merging during the subsequent photolithographic etching process. It is possible to suppress the generation of etching residue due to the step between the active region and the element isolation region.

[Brief description of drawings]

FIG. 1 is a process procedure diagram showing a conventional element isolation method for a semiconductor device.

FIG. 2 is a process procedure diagram showing a conventional element isolation method for a semiconductor device.

FIG. 3 is a process procedure diagram showing a conventional element isolation method for a semiconductor device.

FIG. 4 is a process procedure diagram showing a conventional element isolation method for a semiconductor device.

FIG. 5 is a process procedure diagram showing a conventional element isolation method for a semiconductor device.

FIG. 6 is a process flow chart showing a conventional element isolation method for a semiconductor device.

FIG. 7 is a process flow chart showing an element isolation method for a semiconductor device according to the present invention.

FIG. 8 is a process flow chart showing an element isolation method for a semiconductor device according to the present invention.

FIG. 9 is a process procedure diagram showing an element isolation method for a semiconductor device according to the present invention.

FIG. 10 is a process procedure diagram showing an element isolation method for a semiconductor device according to the present invention.

FIG. 11 is a process procedure diagram showing an element isolation method for a semiconductor device according to the present invention.

FIG. 12 is a process flow chart showing an element isolation method for a semiconductor device according to the present invention.

FIG. 13 is a process flow chart showing an element isolation method for a semiconductor device according to the present invention.

FIG. 14 is a process procedure diagram showing an element isolation method for a semiconductor device according to the present invention.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... Pad oxide film, 13 ... First nitride film, 14 ... Etching stopper, 15 ... Second nitride film, 16 ... Photosensitive film pattern, 17 ... Primary recess region, 1
8 ... Side wall insulating film, 19 ... First oxide film, 20 ... Secondary recess region, 21 ... Impurity diffusion layer, 22 ... Second oxide film.

Claims (16)

[Claims] 1. A semiconductor substrate comprising an active region and an element isolation region, a first region located in the element isolation region of the semiconductor substrate and having a surface lower than a surface of the semiconductor substrate, A second region that is located on both sides of the first region and has a width and a depth that is narrower than the first region; and an element isolation film formed by being embedded in the first region and the second region. A semiconductor device characterized by the above. 2. The impurity diffusion layer (21) formed on the surface of the second region is further included.
The semiconductor device according to. 3. The device isolation film comprises a first oxide film (19) formed on the first region, the first oxide film and a second oxide film (19).
The semiconductor device according to claim 1, wherein the semiconductor device comprises a second oxide film (22) formed on the region. 4. The semiconductor device according to claim 3, wherein the first oxide film is a thermal oxide film. 5. The semiconductor device according to claim 3, wherein the second oxide film is a thermal oxide film. 6. The second oxide film is formed by a CVD method or an LP method.
The semiconductor device according to claim 3, wherein the semiconductor device is an oxide film formed by a CVD method. 7. A step of forming a multi-layered laminated insulating film on a semiconductor (11), wherein the laminated insulating film is selectively etched to form a laminated insulating film pattern, and the exposed one of the semiconductor substrates. Part is etched to a predetermined depth and the primary recess area (1
7), forming a sidewall insulating film (18) on a side surface of the laminated insulating film pattern, and forming a first oxide film (19) on the primary recess region (17). Selectively removing the sidewall insulating film, and removing the sidewall insulating film to etch a portion of the exposed semiconductor to a predetermined depth to form a secondary recess region (20). And a second oxide layer (2) on the first oxide layer and the secondary recess region.
2. A method for manufacturing a semiconductor device, comprising the steps of forming 2) and the step of selectively removing the laminated insulating film pattern. 8. The laminated insulating film comprises a pad oxide film (12), a first nitride film (13), an etching stopper (14), and a second nitride film (15) in this order on the semiconductor substrate. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is formed by vapor deposition. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the sidewall insulating film is formed of a nitride film. 10. The first oxide film (19) according to claim 7, wherein a thickness of the first oxide film (19) is set so as to be lower than a surface of the semiconductor substrate. Manufacturing method of semiconductor device. 11. The secondary recess region is formed deeper than the primary recess region.
A method of manufacturing a semiconductor device according to item 1. 12. The first oxide film (19) is formed by a thermal oxidation process using the laminated insulating film pattern and the sidewall insulating film as an oxidation mask. Manufacturing method of semiconductor device. 13. The second oxide film is formed by being embedded in the primary recess region and the secondary recess region by a thermal oxidation process using the laminated insulating film pattern as an oxidation mask. The method of manufacturing a semiconductor device according to claim 7. 14. The second oxide film is formed by CVD or L
8. The method of manufacturing a semiconductor device according to claim 7, wherein an oxide film is formed by the PCVD method, and then the oxide film is etched back to be embedded in the primary recess region and the secondary recess region. . 15. The method of manufacturing a semiconductor device according to claim 7, wherein the second oxide film is formed flat without forming a step with the surface of the semiconductor substrate. 16. The method further comprising, after the step of forming the secondary recess region (20), implanting impurity ions into the secondary recess region (20) to form an impurity diffusion layer (21). The method of manufacturing a semiconductor device according to claim 7.