JPH07211067A - Memory controller - Google Patents

Abstract

(57) [Abstract] [Purpose] The memory refresh operation is omitted for the memory cells selected by the row address of the memory cells accessed within a fixed time, and access conflict with the data processing device is eliminated. Reduce. A refresh memory selection signal 27 obtained by decoding a refresh address of a memory by a refresh address decoder 8 and a CUP at the time of memory access.
The address output from 1 is decoded by the row address decoder 7, and the access history bit signal 26 obtained from the latch element 9 that holds the access history for the row (row) address of the memory cell accessed within a fixed time
When the CPU indicates the access history of the memory within a fixed time with respect to the memory address to be refreshed, the memory control device is configured to omit the refresh.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for a system using a memory requiring a memory holding operation (hereinafter referred to as refresh), such as a dynamic random access memory (hereinafter referred to as DRAM) or a video RAM (hereinafter referred to as VRAM). Regarding

[0002]

2. Description of the Related Art In recent years, with the advancement of semiconductor technology, the capacity of memories has increased, and DRAMs and VRAMs, which are advantageous in terms of downsizing and cost, have come to be used in various fields. In these memories, data "1" or "0" is stored by charging / discharging a minute charge to / from a memory cell, which is a constituent unit of the memory, and the data is stored for a certain period so that the data is not lost by self-discharge of the minute charge. It is necessary to rewrite (refresh) once. The refresh is performed by inputting a row address to the memory, selecting one word line, amplifying the memory cell data connected to the word line by a sense amplifier, and rewriting the data. .

In a system using DRAM or VRAM, in order to read and write data at a high speed in consideration of the refresh operation, a complicated memory control device corresponding to various operation cycles is required.

Here, a configuration example of a conventional memory control device is shown in FIG. In FIG. 5, 1 is a CPU as a component,
Reference numeral 2 is a refresh address generator for generating a memory address to be refreshed, 3 is a refresh timer for deciding when to perform refreshing, 4 is a multiplexer for switching between a memory address for reading and writing data and a refresh address, and 5 is timing for reading and writing data. Timing generator for generation, 6 for DRAM, 14
Is a memory address bus, 15 is a CPU data bus, 1
6 is an address bus of the CPU, 17 is a refresh address bus, 18 is a refresh address switching signal for outputting a refresh address to the memory address bus at the time of refresh, and 19 is a row address on the memory address bus when reading / writing data. Column
A row / column switching signal for switching and outputting addresses, 20 is an access request signal from the CPU to the memory, 21 is a refresh request signal indicating the refresh time, and 22 is for fetching a row address into the memory. / RAS signal, 23 is a / CAS signal for fetching a column address into the memory, 2
4 is a write enable (/
WE) signal.

The operation of the memory control device including the above-mentioned components will be described with reference to the flow chart of FIG. First, the refresh timer 3 determines whether or not it is the refresh time (step 1), and if the refresh time is reached, the refresh request signal 21 is set to "1" (true) (step 2-).
1). At this time, it is determined whether the DRAM 6 is not being used for access by the CPU 1 (step 2-2),
If the CPU 1 is in use, it waits until the access of the CPU 1 is completed without entering the refresh operation (step 2-3). C
When the access of PU1 is completed, the timing generator 5 outputs the / RAS signal 22 at a predetermined timing to refresh (step 2-4). When the refresh is completed, the refresh timer 3 sets the refresh request signal 21 to "0" (false) (step 2-5). on the other hand,
If it is not the refresh time, it is determined whether the access request is issued by the CPU 1 (step 3-1). If so, it is determined whether the DRAM 6 is in the refresh operation (step 3-2). At this time, if the refresh operation is in progress, the CPU 1 does not read or write the DRAM 6, and therefore waits until the refresh is completed (step 3-
3). After that, when the refresh is completed, the timing generator 5 outputs the / RAS signal 22, / CAS signal 23, / WE
The signal 24 is output at a predetermined timing, and the CPU 1 reads and writes the DRAM 6 (step 3-
4). In this way, the memory is controlled while arbitrating the conflict between the refresh operation and the access by the CPU.

Next, the operation of the conventional memory control device having the above configuration will be described with reference to the timing chart shown in FIG. In the figure, each control signal is described in negative logic (true is low level). The CPU 1 sends an access request signal to the DRAM 6 to read and write data.
Is set to true (time T1), the refresh request signal 21
Is false, the timing generator 5 permits the access and sets the / RAS signal 22 to true (time T2). At this time, the row address is being output to the memory address bus 14 by the row / column switching signal 19, and / RA
The row address is taken into the DRAM 6 at the falling edge of the S signal 22. Next, the row / column switching signal 19 is set to true (time T3) to set the memory address bus 14
When the column address is output to the timing generator 5,
Sets / CAS signal 23 to true (time T4). At this time, the column address is DR when the / CAS signal 23 falls.
The data is read into and read from the memory cell which is fetched inside the AM6 and designated by the row address and the column address. In the middle of the above operation cycle, at time T3, the refresh request signal 21 indicating that it is the refresh time is true, but since it conflicts with the CPU access, the timing generator 5 immediately starts the refresh operation. Without inserting the data, the data read / write cycle ends, and the RAS precharge time elapses before the refresh is performed. That is, after the CPU access ends at time T5, a predetermined RAS precharge time (T
After 5 to T7), the refresh operation is performed. Therefore, the timing generator 5, after detecting that the access request signal 20 from the CPU is false at time T6, sets the refresh address switching signal 18 to true, outputs the refresh address to the memory address bus 14, and enters the refresh preparation. . Further, at time T7, / R
By making the AS signal 22 true, the refresh address is taken into the memory and the refresh operation is performed (time T7 to T10).

On the other hand, during the refresh period, the access request signal 20 from the CPU is generated at time T7, but since the DRAM 6 is already ready for the refresh operation, the access request from the CPU is not issued until the refresh operation is completed. Not allowed. That is, the refresh operation ends at time T10, the RAS precharge time (T10 to T12) elapses, and then the access request signal 20 generated at time T7 is permitted only at time T12, and then the above-described data read / write is performed. Cycle (T2
Data is read and written by the CPU by the same operation as (~ T5).

[0008]

However, in the above-described conventional configuration, the refresh address is generated at a constant cycle based on the refresh request signal, and the memory address accessed by the CPU within the refresh cycle, which is originally unnecessary, is generated. The refresh operation of was also repeated. Therefore, when the CPU accesses another address, if the refresh operation as described above is being performed, the CPU cannot wait for the DRAM to read or write, and must wait until the refresh is completed. In the case of DMA transfer of a large amount of data or in a system in which block transfer of image data is repeated in a complicated manner, there is a problem that performance is significantly reduced.

It is an object of the present invention to provide a memory control device capable of accessing the DRAM without wasting time by avoiding access competition with the CPU by reducing the number of refresh times.

[0010]

In order to achieve the above object, the present invention provides a memory control device having means for omitting a refresh operation for a memory address accessed by a CPU within a refresh cycle.

[0011]

According to the present invention, with the above configuration, the refresh of the memory cell once accessed by the CPU can be omitted.
In a system that DMA-transfers a large amount of data in the memory area or a system that repeatedly repeats block transfer of image data, the CPU can access the memory without wasting time.

[0012]

1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a flow chart for explaining the operation of FIG. In FIG. 1, the same circuits and the like as those in FIG. 5 are given the same numbers and their explanations are omitted.

The feature of the present embodiment is that as a means for omitting the refresh operation for the memory address accessed by the CPU 1 within the refresh cycle, the row of the memory accessed by the address output from the CPU 1 as shown in FIG. A row address decoder 7 that outputs an access memory cell selection signal 25 that specifies (row), a refresh address decoder 8 that decodes a refresh address indicated by a refresh address generator, and a row (row) of a memory cell accessed within a fixed time. Latch element 9 for holding access memory cell selection signal 25 for storing access history for address, latch element 9
A logic gate 10 transmitting a refresh memory cell selection signal 27 to the next stage by an access history bit signal 26 output from the logic gate 10 and a logic gate controlling a refresh time signal 30 according to the refresh memory cell selection signal 27 output from the logic gate 10. It is equipped with 11.

The operation of the memory control device configured as described above will be described with reference to the flow chart shown in FIG. First, the refresh timer 3 determines whether it is the refresh time (step 1), and if it is the refresh time, it is determined whether the access history bit is 1 (true) (step 1-1). If the access history bit is 1, the access history bit is set to 0 (false) (step 1-
2) The refresh request signal 21 is set to false (step 1-3). If the access history bit is 0, the refresh request signal 21 is set to true (step 2-1). At this time, it is determined whether the DRAM 6 is not being used for access by the CPU 1 (step 2-2), and if it is being used, the CPU waits without entering the refresh operation until the access of the CPU 1 is completed (step 2-3). . When the access of the CPU 1 is completed, the timing generator 5 outputs the / RAS signal 22 at a predetermined timing to refresh (step 2-4). When the refresh is completed, the refresh timer 3 makes the refresh request 21 false (step 2-5). On the other hand, when it is not the refresh time, it is determined whether the access request is made by the CPU 1 (step 3-1), and if so, it is determined whether the DRAM 6 is in the refresh operation (step 3-).
2). At this time, if the refresh operation is in progress, the CPU 1 cannot read or write the DRAM 6, so the CPU waits until the refresh is completed (step 3-3). After that, when the refresh is finished, the timing generator 5 accepts the access from the CPU, / RAS signal 22, / CAS signal 23, /
The WE signal 24 is output at a predetermined timing, and the CPU 1 reads and writes the DRAM 6 (step 3-
4). DRAM accessed by CPU 1 at this time
The row address of 6 is decoded by the row address decoder 7, and the result is "1" in the access history bit.
Is held in the latch 9.

As described above, the memory control device of this embodiment is
The CPU 1 is characterized by performing processing for holding an access history and processing for determining whether or not there is an access history and omitting the refresh operation for one row designated by a row address of the DRAM 6. . Therefore, when the access history bit signal 26 is 1, the refresh operation of the target memory 1 row is omitted, and the CPU
Can access memory without wasting time.

The operation of the memory controller according to the present invention will now be described with reference to the conceptual diagram shown in FIG. CPU1 is D
If the row addresses 00 and 03 of the RAM 6 are accessed, the row address decoder 7
Memory cell selection signal 2 corresponding to addresses 0 and 03
5 becomes true, and "1" is stored in the latch element 9 corresponding to addresses 00 and 03. FIG. 3A shows a state in which “1” is stored in the access history bits 00 and 03 and the other bits are “0”.

Further, in this state, it is assumed that the row address 02 of the memory has reached the refresh time. Referring to FIG. 3A, the portion corresponding to the address 02 of the refresh address selection signal is "1", which indicates that the refresh time has come. Furthermore, referring to the access history bit corresponding to the address 02, "0"
Since (refreshing is required), the row address 02 of the memory is finally refreshed.

On the other hand, referring to FIG. 1, when the row address 02 of the memory reaches the refresh time, the refresh timer 3 causes the refresh time signal 30
Is output, and the refresh address generator 2 receiving this outputs the refresh address 02.
Then, the refresh address decoder 8 decodes the refresh address 02, and the refresh memory cell selection signal 27 corresponding to the address 02 becomes true. In this case, since the access history bit signal 26 corresponding to the address 02 stores "0", the refresh memory cell valid selection signal 28 corresponding to the address 02 output from the logic gate 10 becomes true. Therefore, the refresh enable signal 29 becomes true by the logic gate 11, and the refresh time signal 30 passes through the logic gate 12 and is input to the timing generator 5 as the refresh request signal 21. Upon receiving the refresh request signal 21, the timing generator 5 detects that it is the refresh time, sets the / RAS signal 22 to true at a predetermined timing,
Refresh.

Next, it is assumed that the row address 03 of the memory reaches the refresh time after a predetermined time has elapsed.
Referring to FIG. 3B, the refresh memory cell selection signal is "1" at a position corresponding to the address 03, indicating that the refresh time has come. Furthermore, 0
When the access history bit signal corresponding to the address 3 is referred to, it is "1" (refresh unnecessary), so the refresh is omitted for the row address 03 of the memory.

The above operation will be described with reference to FIG. When the row address 03 of the memory reaches the refresh time, the refresh time signal 30 is output again, and the refresh address generator 2 outputs the refresh address 03. Then, the refresh memory cell selection signal 27 corresponding to the address 03 becomes true. In this case, since "1" is stored in the access history bit at address 03, the refresh memory cell valid selection signal 28 corresponding to address 03 output from the logic gate 10 becomes false. Therefore, the refresh enable signal 29 becomes false by the logic gate 11, the refresh time signal 30 does not pass through the logic gate 12, and the refresh request signal 21 remains false. Therefore, refresh is not performed for the row address 03 of the memory.

The operation of the memory control device according to the embodiment of the present invention will now be described in more detail with reference to the timing chart of FIG. When the CPU 1 sets the access request signal 20 to the DRAM 6 to be true (time T1) for reading and writing data, the refresh request signal 21 is false, so the timing generator 5 permits the access and the operation of the memory device in the conventional example. Performs the same operation as. That is, the timing generator 5 outputs the / RAS signal 2 at the time T2.
2 is set to true and the row address is fetched in the DRAM 6, and then the row / column switching signal 19 is set to true at time T3 to output the column address to the memory address bus 14. Further, the timing generator 5 is / CA at time T4.
The S signal 23 is set to true, and data is read from and written to the memory cell of the DRAM 6 designated by the row address and the column address (time T1 to T5).

It is assumed that the refresh time signal 30 indicating that the address 03 is the refresh time becomes true at time T2 during the above operation cycle. At this time, the refresh address 03 is output to the refresh address bus 17. At time T3,
Refresh memory cell selection signal 2 corresponding to address 03
Although 7 is true, the access history bit signal 26 corresponding to the address 03 is also true. Therefore, refreshing the address 03 is unnecessary, the refresh request signal 21 does not become true at T3, and the refresh time signal 30 maintains false during the true period (T2 to T10). By this operation, the CPU1 causes the T7
Even if the access request signal 20 is output to the DRAM 6 again in, the data can be read and written to the memory as it is without any access conflict (the period of T7 to T11).

[0023]

As described above, since the memory control device of the present invention omits the refresh operation for the memory address accessed within the refresh cycle, the CP
Access conflict with U can be avoided with a high probability, and C
The PU can access the memory without wasting time. Therefore, the performance of the entire system can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a memory control device according to an embodiment of the present invention.

FIG. 2 is a flowchart explaining the operation of the memory control device.

FIG. 3 is a conceptual diagram illustrating an operation of the memory control device.

FIG. 4 is a timing chart explaining the operation of the memory control device.

FIG. 5 is a block diagram showing a configuration of a conventional memory control device.

FIG. 6 is a flowchart illustrating the operation of the memory control device.

FIG. 7 is a timing chart explaining the operation of the memory control device.

[Explanation of symbols]

 1 CPU 2 Refresh Address Generator 3 Refresh Timer 4 Multiplexer 5 Timing Generator 6 DRAM 7 Row Address Decoder 8 Refresh Address Decoder 9 Latch Element 10 Logic Gate 11 Logic Gate 12 Logic Gate 14 Memory Address Bus 15 Data Bus 16 Address Bus 17 Refresh Address 18 Refresh address switching signal 19 Row / column switching signal 20 Access request signal 21 Refresh request signal 22 / RAS signal 23 / CAS signal 24 / WE signal 25 Access memory cell selection signal 26 Access history bit signal 27 Refresh memory cell selection signal 28 Refresh memory cell selection enable signal 29 Refresh enable signal 30 Refresh time signal 31 Clear Issue

Claims (1)

[Claims] 1. A memory control device which requires a memory holding operation (refresh), wherein a refresh timer for notifying the memory of a refresh time at a constant cycle and a refresh time signal output from the refresh timer, , A refresh address decoder for decoding the refresh address indicated by the refresh address generator, and a row address decoder for outputting a row selection signal of a memory cell according to an address output from the data processing device. And a latch element that receives a row selection signal output from the row address decoder and holds an access history for a row address of a memory cell accessed within a fixed time. , The above A first logic gate that controls the refresh memory cell selection signal output from the refresh address decoder by the output of the latch element, and a second logic gate that controls the refresh time signal by the output of the first logic gate And a memory control device, wherein the target memory is not refreshed when the latch element corresponding to the refresh address indicates an access history within a fixed time.