JPH10233091A - Semiconductor storage device and data processing device - Google Patents

Abstract

(57) [Problem] In a conventional synchronous DRAM of a command control system, an interval (clock number) until a next command is input is defined depending on a type of a command.
The microprocessor cannot give a plurality of commands to the memory in succession, so that the bus control and the command input are complicated and the system throughput is reduced. SOLUTION: A command register (21) capable of holding a plurality of commands, an address register (22) capable of holding a plurality of addresses, and a command stored in the command register are decoded to determine a required number of clocks. A control circuit (20) for executing the next command after a predetermined time has elapsed is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory technology and a technology effective when applied to a command input method in a semiconductor memory device, for example, a technology effective for use in a clock synchronous semiconductor memory device.

[0002]

2. Description of the Related Art In a semiconductor memory device such as a synchronous dynamic RAM (hereinafter abbreviated as a synchronous DRAM), data reading and writing are performed by externally input commands (read command and write command). Some are configured. The commands referred to here are the chip select signal CS, the row address strobe signal RAS, and the column address strobe signal C
A command (code) supplied from a microprocessor to a peripheral device (such as a CRT controller) via a data bus in a general microcomputer system in an ordinary microcomputer system. Of different nature. However,
The present invention is applicable to a system using a general command in a microcomputer system. The synchronous DRAM is configured such that other commands such as the read command and the write command are also given by a combination of external control signals.

[0003]

In the synchronous DRAM of the command control system as described above, the interval (the number of clocks) until the next command is specified depending on the type of command. For example, as shown in FIG. 3A, a read command READ for data reading (or a write command WRT for writing) has passed three clocks after input of an active command ACTV for setting a word line to a selection level. Need to be entered at the time.

[0004] Therefore, the microprocessor cannot give a plurality of commands to the memory continuously, and the bus control and command input by the microprocessor are complicated, and a waiting time is required between execution of one command and execution of the next command. However, there is a problem that it is difficult to perform other processing during that time, and the system throughput is reduced. In particular, multiple synchronous DR
When it is desired to give different commands to a plurality of memories in a system using AM, bus control and command input become very complicated if a conventional synchronous DRAM is used.

An object of the present invention is to provide a semiconductor memory device capable of continuously giving commands from an external microprocessor or the like, thereby simplifying bus control and command input and improving the system throughput. It is in.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a command control type semiconductor memory device, a command register capable of holding a plurality of commands, an address register capable of holding a plurality of addresses, and the number of clocks required by decoding commands stored in the command register. And a control circuit for executing the next command after a predetermined time elapses.

Specifically, the control circuit is provided with a counter for counting a clock input from the outside, so that the execution timing of the command can be controlled.

According to the above-described means, even when the time until the next command execution differs depending on the command, the semiconductor memory device has a register capable of holding a plurality of commands, and the semiconductor memory device determines the command by itself and determines an appropriate command. Processing at the timing allows the external microprocessor to continuously input multiple commands and the addresses required for each command, which simplifies microprocessor bus control and command input, as well as system throughput. Can be improved.

In consideration of the case where a plurality of semiconductor memory devices of the same type are used in the same system, a terminal for outputting a signal indicating an operation state to the outside is provided. It is preferable that the control circuit has a function of determining whether or not the command is to be executed. As a result, the microprocessor can continuously give commands to a plurality of semiconductor memory devices, and even in a system using a plurality of semiconductor memory devices of the same type, bus control and command input by the microprocessor can be easily performed. As a result, the throughput of the system can be improved.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a synchronous dynamic RAM to which the present invention is applied.

In FIG. 1, reference numerals 10A and 10B denote memory arrays configured as two banks, and 11A and 11B take in row address signals and column address signals input from the outside in a time-division manner, and store them in predetermined internal circuits. An address input buffer circuit for supplying an address, 12 is a refresh counter for generating an address for refreshing a memory cell, and 13A and 13B decode an internal complementary address signal supplied from the address input buffer circuit 11A or the refresh counter 12. A row decoder 14 for selecting a corresponding word line in the memory arrays 10A and 10B, and a column for generating a continuous column address necessary for reading / writing a plurality of bytes of data based on a column address input from the outside. Address counter, 5A and 15B are column decoders for decoding internal address signals supplied from the column address counter 14 and selecting corresponding bit lines in the memory arrays 10A and 10B, and 16A and 16B are for reading data read to the bit lines. This is an I / O bus to which the sense amplifier to be amplified and a plurality of bit lines are commonly connected via a column switch.

A data input buffer circuit 17 receives a write data signal and supplies it to the memory arrays 10A and 10B via the sense amplifier & I / O bus 16. A reference numeral 18 denotes a data input buffer circuit via the sense amplifier & I / O bus 16. A data output buffer circuit for outputting data read from the memory arrays 10A and 10B to the outside, and a timing 19 for forming a timing signal to be supplied to the internal circuit based on various control signals and clock signals input from the outside. It is a control circuit.

As a control signal externally input to the memory of this embodiment, in addition to the clock signal CLK, for example, a clock for controlling not to supply an input clock to reduce internal power consumption to an internal circuit. An enable signal CKE, a chip select signal / CS for indicating that the memory is selected, and a row address strobe signal / for giving a row address fetch timing.
RAS, a column address strobe signal / CAS for giving a column address fetch timing, a write control signal / WE for indicating that writing is valid,
A control signal DQM for requesting that a predetermined bit of data be masked from being read or written.
Etc. Note that a control signal in which "/"("-" is shown above the symbol in the figure) before each symbol indicates that the low level is an effective level.

In the synchronous DRAM of this embodiment,
As shown in FIG. 1, the various control signals CKE,
A FIFO (first-in-first-out) for sequentially taking in and holding each of the above control signals (commands) between the input terminals of / CS, / RAS, / CAS, / WE, and DQM and the timing control circuit 19 based on the clock CLK. Out) type register 21 is provided. Further, the address input terminal and the address input buffer circuit 11A,
11B, there is provided an address register 22 for sequentially taking in and holding a plurality of address signals input in association with the control signals (commands) by the FIFO method.

Further, in the synchronous DRAM of this embodiment, the command stored in the command register 21 is decoded, the required number of clocks is determined, and the timing of the next command is controlled after a predetermined time has elapsed. A command control circuit 20 for transferring the data to the circuit 19 is provided.

Each of the registers 21 and 22 is configured to hold at least four or more commands, that is, four or more commands and addresses. There are a row address and a column address in the address fetched into the address register 22, which are specified according to the command, and are transferred to the address input buffer circuit 11A or 11B according to the result of decoding the command. The switching control signal Tc1 for that purpose is sent from the command control circuit 20 to the address input buffer circuits 11A and 11B.
It is configured to be supplied to

Further, the command control circuit 20 in this embodiment is provided with the clock CLK which is input from the outside.
And a command 23 which takes a time to decode a command first taken into the register 21 and execute the next command (for example, a command for raising a word line to a selected level). Active command or a precharge command for precharging the data line to Vcc / 2).
After counting the number of clocks required by the counter 23,
The next command is read from the register 21 and decoded to determine whether a clock interval is required, and is transferred to the timing control circuit 19 to form a corresponding control signal.

The following command is stored in the command register 2
The timing signal Tc2 for taking in from 1 is also supplied to the address register 22. At the same time as taking in the command, an address signal previously taken into the address register 22 is sent to the address input buffer circuit 11A or 11B accompanying the command. It is configured as follows.

In the memory of this embodiment, although not particularly limited, the number of address pins is 12 from A0 to A11, the row address signal is 12 bits from A0 to A11, and the column address signal is 9 bits from A0 to A8. Have been.

Since the synchronous DRAM of the above embodiment has a command register 21 capable of holding four or more commands, an external microprocessor instructs the DRAM as shown in FIG. Command can be continuously input. As a result, the bus control and command input by the microprocessor are simplified, and the microprocessor can also give commands to the DRAM and then shift to processing other than DRAM access.

FIG. 2 shows an example of a system using the synchronous DRAM of the above embodiment. The microprocessor (CPU) 100 and the synchronous DRAM 110 are connected via a bus 120. In this embodiment, the synchronous DRAM 110 is configured to be used as a main memory for storing programs and data. OS
(Operating system) and application software are read from the hard disk device 180 by the hard disk
It is transferred to 110 and executed.

In addition to the main memory, the display 1
Video RAM for storing image data displayed on 40
A CRT controller 160 having a read / write operation 150 is connected to the system bus 120.
The video RAM 150 has a configuration similar to, for example, the synchronous DRAM of the above-described embodiment, and has a command control type synchronous DRAM (synchronous graphic RAM) having a block write function of writing data to one block of memory cells. Can be configured. Note that 170
Is a clock generation circuit, 190 is a microprocessor 10
It is a keyboard as an input device for giving an external command to 0.

In the above system, the main memory 11
0 may be composed of a plurality of synchronous DRAMs. In such a case, if the synchronous DRAM of the above embodiment having the command register 21 and the address register 22 is used, the microprocessor 100 can continuously input commands to a plurality of DRAMs.
Further, the throughput is improved.

However, since a conflict occurs between memories depending on the command, in such a case (for example, when a read command is issued to a plurality of DRAMs), a method of inserting the command may be devised, or a command may be applied to another memory. The command control circuit 20 has a function of providing a terminal for outputting a signal indicating an operation state (for example, completion of a read operation), and determining whether or not the command is for itself when the command register has sufficient capacity. You may have it. in this case,
The command for the other memory is also taken into the command register 21 together with the information specifying the memory, and the command control circuit 20 counts the number of clocks required to execute the command of the other memory and executes the command addressed to itself at an appropriate timing. It is good to configure.

In the above embodiment, the command control circuit 20 for decoding the command and determining the start timing of the next command is provided separately from the timing control circuit 19, but these circuits are formed as an integrated control circuit. It is also possible to configure.

As described above, in the above embodiment, in the synchronous DRAM of the command control system, a command register capable of holding a plurality of commands, an address register capable of holding a plurality of addresses, and the command register are stored in the command register. A control circuit that decodes the command, determines the required number of clocks and executes the next command after a predetermined time has elapsed is provided, so that even if the time until the next command execution differs depending on the command, the semiconductor Since the storage device has a register capable of holding a plurality of commands and determines the command itself and performs processing at an appropriate timing, an external microprocessor continuously stores a plurality of commands and addresses necessary for each command. Input, which allows the microprocessor to control buses and commands. There is an effect that can be improved system throughput for with de input becomes simple can perform other processing after entering a command.

Further, by providing a terminal for outputting a signal indicating an operation state to the outside, or by providing the control circuit with a function of determining whether or not the command is for itself and executing the command, the microprocessor can be provided with a plurality of microprocessors. A command can be continuously given to a semiconductor memory device, and even in a system using a plurality of semiconductor memory devices of the same type, bus control and command input by a microprocessor can be simplified, and the system throughput can be improved. There is an effect that it can be achieved.

Although the invention made by the present inventors has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, in the above-described embodiment, the command register 21 and the address register 22 are provided, but in addition to the above two registers, between the data input / output terminal and the data input buffer circuit 16 and the data output buffer circuit 17, A data register capable of holding a plurality of data in a FIFO manner may be provided. In this case, the data register may be provided separately for input and output, or a register having a configuration capable of transferring data bidirectionally may be used. Further, the data register and the address register can have a smaller number of stages than the command register.
This is because some commands have no address or data. Further, the number of data registers may be larger than the number of command registers.
This is because a synchronous DRAM has a data serial output function and can continuously input / output a plurality of data in response to one READ WRITE command. The device that gives commands to the DRAM is not limited to the microprocessor, but may be another device that can be a bus master.

In the above description, the case where the invention made by the present inventor is mainly applied to a synchronous DRAM which is a field of application as a background has been described. However, the present invention is not limited to this, and is not limited thereto. The present invention can be generally used for semiconductor memories and semiconductor integrated circuits of a command control system.

[0032]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, commands can be continuously given from an external microprocessor or the like, thereby realizing a semiconductor memory device in which the bus control and command input are simple and the system throughput can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous dynamic RAM as an example of a semiconductor memory device suitable for applying the present invention.

FIG. 2 is a block diagram illustrating an example of a system including a synchronous dynamic RAM according to the embodiment;

FIG. 3 is a timing chart showing a difference between a conventional command input timing and a command input timing in the present invention.

[Explanation of symbols]

 10A, 10B Memory array 11A, 11B Address input buffer circuit 12 Refresh counter 13A, 13B Row decoder 14 Column address counter 15A, 15B Column decoder 16A, 16B Sense amplifier & I / O bus 17 Data input buffer circuit 18 Data output buffer circuit 19 Timing Control circuit 20 Command control circuit 21 Command register 22 Address register 23 Clock counter 100 Microprocessor 110 Main memory (synchronous DRAM) 120 System bus 130 Hard disk controller 140 Display 150 Video RAM 160 CRT controller 170 Clock generation circuit 180 Hard disk device 190 Keyboard

Claims (5)

[Claims] In a semiconductor memory device of a command control method for controlling the operation of an internal circuit according to a command input from the outside, a command register capable of holding a plurality of commands, an address register capable of holding a plurality of addresses, A semiconductor memory device comprising: a control circuit that decodes a command stored in the command register, determines a required number of clocks, and executes a next command after a predetermined time has elapsed. 2. The control circuit according to claim 1, wherein the control circuit is configured to operate in synchronization with a clock signal input from the outside, and the control circuit includes a counter for counting the clock signal. 13. The semiconductor memory device according to claim 1. 3. The method according to claim 2, wherein the command is a combination of a plurality of control signals input from the outside, and the command register is configured to sequentially receive commands in synchronization with the clock signal. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, wherein said command control circuit has a function of determining whether or not the command is issued to itself. 5. A data processing device, comprising: the semiconductor memory device according to claim 1; and a microprocessor for giving a command to the semiconductor memory device to control the semiconductor memory device.