JPH07201967A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE:To form a field shielding electrode with dimensions smaller than the fine processing limit by a method wherein the side surfaces of a polycrystalline silicon film are subjected to thermal oxidation to form insulating side walls. CONSTITUTION:After a silicon oxide film 2 is formed over the whole surface of a silicon substrate 1 by a thermal oxidation method, a polycrystalline silicon film 3 is formed over the whole surface by a CVD method. Further, after a silicon oxide film 4 is formed over the whole surface by a thermal oxidation method, a silicon nitride film 5 is formed over the whole surface by a CVD method. After a part to be an element isolation region is covered with a resist film by a photolithography technology, the silicon nitride film 5, the silicon oxide film 4 and the polycrystalline silicon film 3 are etched by an etching method such as an RIE method so as to leave a field region. At that time, the width of the polycrystalline silicon film 3 after etching can be as small as a fine processing limit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which elements are isolated by a field shield element isolation structure.

[0002]

2. Description of the Related Art In recent years, element isolation by a field shield element isolation structure has attracted attention in place of element isolation by the LOCOS method. The element isolation by the field shield element isolation structure is advantageous for miniaturization of the element because bird's beak unlike the LOCOS method does not occur.

9 to 17 show steps of forming a conventional field shield element isolation structure.

First, as shown in FIG. 9, a silicon oxide film 2 is formed on a silicon substrate 1 by a thermal oxidation method, and CV is used.
The polycrystalline silicon film 3 and the silicon oxide film 4 are sequentially formed by the D method.

Next, as shown in FIG. 10, a portion of the element isolation region is covered with a resist by a lithography technique, and then the silicon oxide film 4 and the polycrystalline silicon film 3 are etched by a method such as RIE. The field shield electrode 3 is formed.

Next, as shown in FIG. 11, a silicon oxide film 11 is formed on the entire surface by a CVD method or the like.

Next, as shown in FIG. 12, anisotropic etching is performed by the RIE method or the like so that the silicon oxide film 11 remains only on the side wall portion of the field shield electrode 3 so that the field shield electrode 3 is formed. The side surface is covered with the sidewall insulating film 11.

Next, as shown in FIG. 13, after removing the thin silicon oxide film 2 on the element region, a silicon oxide film 6 to be a gate oxide film is formed on the silicon substrate 1 by a thermal oxidation method.

Next, a polycrystalline silicon film 7 and a silicon oxide film 8 are formed on the entire surface by a CVD method or the like.

Next, as shown in FIG. 14, after a portion to be a gate electrode is covered with a resist by a lithography technique, the silicon oxide film 8 and the polycrystalline silicon film 7 are respectively etched by a method such as RIE to form a gate. Electrode 7
To form.

Next, ion implantation is performed using the gate electrode 7, the field shield electrode 3, etc. as a mask to form a low-concentration impurity diffusion layer 12 in the silicon substrate 1.

Next, as shown in FIG. 15, a silicon oxide film 9 is formed on the entire surface by the CVD method or the like.

Then, as shown in FIG. 16, anisotropic etching is performed by RIE or the like so that the silicon oxide film 9 is left only on the side walls of the gate electrode 7 and the field shield electrode 3, and the gate is removed. A sidewall insulating film 9 is formed on the sidewalls of the electrode 7 and the field shield electrode 3. At this time, the silicon oxide film 6 on the silicon substrate 1 is also removed by etching, and the silicon substrate 1 is exposed. After that, ion implantation is performed using the gate electrode 7 and the field shield electrode 3 and their side wall insulating films 9 as a mask to form a high-concentration impurity diffusion layer 13 in the silicon substrate 1.

Next, as shown in FIG. 17, after the polycrystalline silicon film 10 is formed on the entire surface by the CVD method or the like,
By patterning this, the source / drain electrodes are extracted.

In the field shield element isolation structure formed as described above, the field shield electrode 3 is fixed to, for example, the ground potential, and the surface potential of the silicon substrate 1 in the element isolation region is changed by the electric field from the field shield electrode 3. Fix it. As a result, the conductivity type of the surface of the silicon substrate 1 in the element isolation region is reversed, and the parasitic MO
It prevents S and the like from being formed.

[0016]

However, according to the conventional method of forming the field shield element isolation structure as described above, the width w of the element isolation region is equal to the width of the field shield electrode 3 and the side wall insulating film 11. It is a value obtained by adding the width (a + b) of 9.

Therefore, the element isolation region w has a width of the field shield electrode 3 which is determined by the processing limit in fine processing, even if it is estimated to be the minimum, and the side wall insulating film 11,
Therefore, there is a problem in that a region having a length obtained by adding the width (a + b) of 9 is occupied, which becomes a hindrance in higher integration of the semiconductor device. For example, the width (a + b) of the sidewall insulating films 11 and 9 is at least 0.
Assuming that 1 μm is required, and the fine processing limit is 0.5 μm, the width w of the element isolation region is 0.7 μm.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing the width of an element isolation region by a field shield element isolation structure.

[0019]

In order to solve the above-mentioned problems, in the present invention, a conductive film is provided on an element isolation region of a semiconductor substrate via an insulating film and the potential of the conductive film is fixed. According to the method of manufacturing a semiconductor device in which the surface potential of the semiconductor substrate in the element isolation region is fixed, a polycrystalline or amorphous silicon film and a silicon nitride film are sequentially formed on the semiconductor substrate via the insulating film. A step of forming, a step of removing the silicon nitride film and the polycrystalline or amorphous silicon film other than the element isolation region, respectively, thereafter, the side surface of the polycrystalline or amorphous silicon film using the silicon nitride film as a mask And a step of thermally oxidizing.

In one aspect of the present invention, after forming the polycrystalline or amorphous silicon film, a silicon oxide film is formed thereon, and then the silicon nitride film is formed on the silicon oxide film.

[0021]

According to the present invention, the side surface of the polycrystalline or amorphous silicon film to be the field shield electrode is thermally oxidized to form the side wall for insulation. Therefore, the field shield electrode can be formed below the microfabrication limit, and the width of the entire element isolation region can be reduced.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS.

First, as shown in FIG. 1, a silicon oxide film 2 having a thickness of 30 nm is formed on the entire surface of a silicon substrate 1 by a thermal oxidation method, and then a polycrystalline silicon film 3 having a thickness of 200 nm is entirely formed by a CVD method. To form. further,
After a silicon oxide film 4 having a thickness of 10 nm is formed on the entire surface by a thermal oxidation method, a silicon nitride film 5 having a thickness of 300 nm is formed on the entire surface by a CVD method.

Next, as shown in FIG. 2, after a portion to be an element isolation region is covered with a resist by a lithographic technique, the silicon nitride film 5, the silicon oxide film 4 and the polycrystalline silicon film 3 are respectively formed by RIE or the like. Etch by method, leaving these only in the field areas. At this time, the width of the polycrystalline silicon film 3 after etching can be reduced to the fine processing limit, and is formed here to be 0 to 5 μm.

Next, thermal oxidation is performed using the silicon nitride film 5 as an oxidation resistant film to form a silicon oxide film 4'having a thickness a of about 0.2 μm on the side wall of the polycrystalline silicon film 3. At this time, the width of about 0.1 μm of the polycrystalline silicon film 3 having a width of 0, 5 μm is used to form the silicon oxide film 4 ′ having a thickness of about 0.2 μm. The width c of 3 is reduced to about 0.3 μm, and the width c of the field shield electrode 3 made of this polycrystalline silicon film can be made smaller than the fine processing limit. At this time, the total width (c + 2a) of the field shield electrode 3 and the silicon oxide films 4'on both sides thereof is about 0.7 μm.

The condition of the thermal oxidation at this time is that the temperature is 9
00 ° C., time is set to 90 minutes, and flow rate ratio is O ₂ : H ₂ =
Perform a 2: 1 pyrogenic oxidation. Although illustration is omitted, when the side wall of the polycrystalline silicon film 3 is thermally oxidized, a silicon oxide film having a thickness of about 100 nm also grows on the silicon substrate 1.

Then, the silicon oxide film 2 (not shown) on the element region is removed by etching by RIE or the like so as to have a film thickness of 50 nm, and then the polycrystalline silicon film 3 is wet-etched with a hydrogen fluoride solution. The silicon oxide film 4'on the side wall of is removed by etching by about 0.15 .mu.m and, at the same time, the silicon oxide film 2 on the element region is substantially completely removed. FIG. 3 shows the state at this time.
At this time, the thickness a of the silicon oxide film 4'is about 0.05 μm.
Therefore, the total width (c + 2a) of the field shield electrode 3 and the silicon oxide films 4'on both sides thereof is about 0.4.
μm.

Here, the silicon nitride film 5 may be removed.

Next, as shown in FIG. 4, a silicon oxide film 6 having a thickness of 10 nm is formed as a gate oxide film on the silicon substrate 1 by a thermal oxidation method.

Next, by a CVD method or the like, 200 nm
Then, a polycrystalline silicon film 7 having a thickness of 2 and a silicon oxide film 8 having a thickness of 200 nm are formed on the entire surface.

Next, as shown in FIG. 5, after the portion to be the gate electrode is covered with a resist by a lithography technique, the silicon oxide film 8 and the polycrystalline silicon film 7 are etched by a method such as RIE to form a gate. The electrode 7 is formed.

Next, ion implantation is performed using the gate electrode 7, the field shield electrode 3 and the like as a mask to form a low concentration impurity diffusion layer 12 in the silicon substrate 1.

Next, as shown in FIG. 6, a silicon oxide film 9 having a thickness of 50 nm is formed on the entire surface by the CVD method or the like.

Next, as shown in FIG. 7, anisotropic etching is performed by the RIE method or the like, so that only the side wall portions of the gate electrode 7 and the field shield electrode 3 are exposed to 0.0.
A sidewall insulating film 9 is formed on the sidewalls of the gate electrode 7 and the field shield electrode 3 so that the silicon oxide film 8 having a thickness of 5 μm remains. At this time, the width of the element isolation region is w = c + 2a + 2b, and the value is 0.5 μm.
Becomes

Next, the silicon substrate 1 exposed by the above anisotropic etching is ion-implanted by using the gate electrode 7, the field shield electrode 3 and the sidewall insulating film 9 thereof as a mask, and the silicon substrate 1 is highly implanted. The impurity diffusion layer 13 having a high concentration is formed.

Next, as shown in FIG. 8, a polycrystalline silicon film 10 having a thickness of 200 nm is formed on the entire surface by the CVD method or the like, and then this is patterned to extract the source / drain electrodes.

Through the above steps, it is possible to form the field shield element isolation structure in which the width of the field shield electrode 3 is below the fine processing limit.

Although the embodiments of the present invention have been described above, the present invention is not limited to the above-mentioned embodiments, and the above-mentioned embodiments are variously effective modifications and applications based on the technical idea of the present invention. Is possible. For example, an amorphous silicon film may be used instead of the polycrystalline silicon film 3. The silicon oxide film 2 is an ONO film (silicon oxide film-
It may be replaced with a three-layer film composed of a silicon nitride film and a silicon oxide film.

Further, in the above-described embodiment, the thickness a of the silicon oxide film 4'on the side wall of the field shield electrode 3 is 0.
Although thermal oxidation was performed so as to have a thickness of 2 μm, the thickness a may be 0.2 μm or more, which allows the width w of the element isolation region to be further reduced. That is, after the silicon oxide film 4'is formed on the side wall of the field shield electrode 3, the thickness of the silicon oxide film 4'is thinned by wet etching using a hydrogen fluoride solution to further reduce the width w of the element isolation region. it can. At this time, since the silicon nitride film 5 is insoluble in the hydrogen fluoride solution, the silicon oxide film 4 on the field shield electrode 3 is not reduced. As a result, if the width of the field shield electrode 3 is within an effective range, the width w of the element isolation region can be reduced without being affected by the fine processing limit.

Further, in the above-mentioned embodiment, the silicon oxide film 4 is formed as the cap insulating film of the polycrystalline silicon film 3, and the silicon nitride film 5 is further formed thereon. Silicon nitride film 5 directly on top
And the silicon nitride film 5 may be used as a cap insulating film of the polycrystalline silicon film 3, whereby the silicon oxide film 4 on the polycrystalline silicon film 3 can be omitted.

[0041]

According to the present invention, the width of the element isolation region formed by the field shield element isolation structure can be made smaller than in the prior art, and the semiconductor device can be further highly integrated.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a field shield element isolation structure according to an embodiment of the present invention.

FIG. 9 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 10 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 11 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 12 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 13 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 14 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 15 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

FIG. 16 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device having the conventional field shield element isolation structure.

FIG. 17 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device having a conventional field shield element isolation structure.

[Explanation of symbols]

 1 silicon substrate 3 polycrystalline silicon film (field shield electrode) 4, 4'silicon oxide film 5 silicon nitride film 6 silicon oxide film (gate insulating film) 7 polycrystalline silicon film (gate electrode) 9 silicon oxide film (sidewall insulation) Membrane) 12 Low concentration diffusion layer 13 High concentration diffusion layer

Claims (2)

[Claims] 1. A conductive film is provided on an element isolation region of a semiconductor substrate via an insulating film, and the potential of the conductive film is fixed to fix the surface potential of the semiconductor substrate in the element isolation region. In the method for manufacturing a semiconductor device described above, a step of sequentially forming a polycrystalline or amorphous silicon film and a silicon nitride film on the semiconductor substrate via the insulating film, the silicon nitride film and the silicon nitride film other than the element isolation region, and A method of manufacturing a semiconductor device, comprising: a step of removing the polycrystalline or amorphous silicon film, respectively, and a step of thereafter thermally oxidizing the side surfaces of the polycrystalline or amorphous silicon film with the silicon nitride film as a mask. . 2. The method according to claim 1, wherein after forming the polycrystalline or amorphous silicon film, a silicon oxide film is formed thereon, and then the silicon nitride film is formed on the silicon oxide film. Item 2. A method of manufacturing a semiconductor device according to item 1.