JPH07201731A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JPH07201731A JPH07201731A JP5334434A JP33443493A JPH07201731A JP H07201731 A JPH07201731 A JP H07201731A JP 5334434 A JP5334434 A JP 5334434A JP 33443493 A JP33443493 A JP 33443493A JP H07201731 A JPH07201731 A JP H07201731A
- Authority
- JP
- Japan
- Prior art keywords
- sealing
- sealing material
- base substrate
- semiconductor device
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000000034 method Methods 0.000 title claims description 17
- 238000007789 sealing Methods 0.000 claims abstract description 100
- 239000003566 sealing material Substances 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 239000008188 pellet Substances 0.000 claims abstract description 50
- 239000011261 inert gas Substances 0.000 claims abstract description 21
- 238000002844 melting Methods 0.000 claims abstract description 9
- 230000008018 melting Effects 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000010953 base metal Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910020220 Pb—Sn Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Die Bonding (AREA)
Abstract
(57)【要約】
【目的】 半導体装置１の気密性を高める。
【構成】 ベース基板２のペレット塔載面の封止領域２
Ａと封止用キャップ３の封止領域３Ａとを封止材で固着
し、このベース基板２及び封止用キャップ３で形成され
るキャビティ４内に半導体ペレット５及び不活性ガスを
気密封止する半導体装置１の製造方法において、ベース
基板２のペレット塔載面上に半導体ペレット５を塔載す
る工程と、ベース基板２のペレット塔載面の封止領域２
Ａに第１封止材７Ａ及びこの第１封止材７Ａに比べて融
点が高い第２封止材７Ｂを介在して封止用キャップ３の
封止領域３Ａを不活性ガスの雰囲気中で載置し、その
後、第１封止材７Ａが溶融するまで熱処理を施す工程
と、第１封止材７Ａを凝固し、この第１封止材７Ａでベ
ース基板２の封止領域２Ａと封止用キャップ３の封止領
域３Ａとを固着する工程とを備える。
(57) [Abstract] [Purpose] To improve the airtightness of the semiconductor device 1. [Structure] Sealing region 2 on the surface of the base substrate 2 on which the pellets are mounted
A and the sealing region 3A of the sealing cap 3 are fixed by a sealing material, and the semiconductor pellet 5 and the inert gas are hermetically sealed in the cavity 4 formed by the base substrate 2 and the sealing cap 3. In the manufacturing method of the semiconductor device 1, the step of mounting the semiconductor pellets 5 on the pellet mounting surface of the base substrate 2, and the sealing region 2 of the pellet mounting surface of the base substrate 2.
The first sealing material 7A and the second sealing material 7B having a melting point higher than that of the first sealing material 7A are interposed in A and the sealing region 3A of the sealing cap 3 is placed in an atmosphere of an inert gas. The step of placing and then heat-treating the first sealing material 7A until the first sealing material 7A is melted, and the first sealing material 7A is solidified and sealed with the sealing region 2A of the base substrate 2 by the first sealing material 7A. And a step of fixing the sealing region 3A of the stopper cap 3 to each other.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に、ベース基板のペレット塔載面の封止領域と封止用キ
ャップの封止領域とを封止材で固着し、このベース基板
及び封止用キャップで形成されるキャビティ内に半導体
ペレット及び不活性ガスを気密封止する半導体装置に適
用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a base substrate and a sealing region of a pellet mounting surface of a base substrate, which are fixed to each other by a sealing material. The present invention relates to a technique effectively applied to a semiconductor device in which a semiconductor pellet and an inert gas are hermetically sealed in a cavity formed by a sealing cap.
【０００２】[0002]
【従来の技術】ベース基板のペレット塔載面上に塔載さ
れた半導体ペレットを封止用キャップで封止する半導体
装置がある。この種の半導体装置は、ベース基板のペレ
ット塔載面の封止領域と封止用キャップの封止領域とを
封止材(例えばろう材)で固着し、このベース基板及び封
止用キャップで形成されるキャビティ内に半導体ペレッ
ト及び不活性ガスを気密封止する。この半導体装置の一
般的な組立プロセスは下記の通りである。2. Description of the Related Art There is a semiconductor device in which a semiconductor pellet mounted on a pellet mounting surface of a base substrate is sealed with a sealing cap. In this type of semiconductor device, the sealing region of the pellet mounting surface of the base substrate and the sealing region of the sealing cap are fixed with a sealing material (for example, a brazing material), and the base substrate and the sealing cap are used. The semiconductor pellet and the inert gas are hermetically sealed in the formed cavity. The general assembly process of this semiconductor device is as follows.
【０００３】まず、ベース基板のペレット塔載面上に半
導体ペレットを塔載する。この半導体ペレットの塔載
は、フェースダウン方式若しくはワイヤボンディング方
式で行なわれる。次に、不活性ガス(例えば窒素ガス)の
雰囲気中において、ベース基板のペレット塔載面の封止
領域に封止材を介在して封止用キャップの封止領域を載
置し、その後、前記封止材が溶融するまで熱処理を施
す。次に、前記封止材を凝固し、この封止材でベース基
板の封止領域と封止用キャップの封止領域とを固着す
る。これにより、ベース基板及び封止用キャップで形成
されるキャビティ内に半導体ペレット及び不活性ガスが
気密封止される。First, semiconductor pellets are mounted on the pellet mounting surface of the base substrate. The mounting of the semiconductor pellets is performed by a face-down method or a wire bonding method. Next, in an atmosphere of an inert gas (for example, nitrogen gas), the sealing region of the sealing cap is placed with the sealing material interposed in the sealing region of the pellet tower mounting surface of the base substrate, and thereafter, Heat treatment is performed until the sealing material is melted. Next, the sealing material is solidified, and the sealing area of the base substrate and the sealing area of the sealing cap are fixed to each other with this sealing material. As a result, the semiconductor pellet and the inert gas are hermetically sealed in the cavity formed by the base substrate and the sealing cap.
【０００４】なお、前記半導体装置については、例えば
特開昭６２−２４９４２９号公報に記載されている。The semiconductor device is described, for example, in Japanese Patent Laid-Open No. 62-249429.
【０００５】[0005]
【発明が解決しようとする課題】本発明者は、前述の半
導体装置について以下の問題点を見出した。The present inventor has found the following problems with the above-mentioned semiconductor device.
【０００６】前記半導体装置の組立プロセスにおいて、
ベース基板の封止領域と封止用キャップの封止領域との
間に介在された封止材を熱処理で溶融する際、溶融によ
る封止材の形状変化で封止用キャップがベース基板側に
向って沈み込み、キャビティ内の内圧がキャビティ外の
外圧に比べて高くなる。このため、キャビティ内の不活
性ガスがキャビティ外に向って移動し(流れ出し)、この
不活性ガスの移動により封止材にボイドが発生する。こ
の封止材に発生するボイドは半導体装置の気密性を低下
させる。In the process of assembling the semiconductor device,
When the encapsulating material interposed between the encapsulating area of the base substrate and the encapsulating area of the encapsulation is melted by heat treatment, the encapsulating cap moves to the base substrate side due to the shape change of the encapsulating material due to the melting. It sinks inward, and the internal pressure inside the cavity becomes higher than the external pressure outside the cavity. Therefore, the inert gas inside the cavity moves (flows out) toward the outside of the cavity, and the movement of the inert gas causes voids in the sealing material. The voids generated in this sealing material reduce the airtightness of the semiconductor device.
【０００７】本発明の目的は、半導体装置の気密性を高
めることが可能な技術を提供することにある。An object of the present invention is to provide a technique capable of increasing the airtightness of a semiconductor device.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【００１０】ベース基板のペレット塔載面の封止領域と
封止用キャップの封止領域とを封止材で固着し、このベ
ース基板及び封止用キャップで形成されるキャビティ内
に半導体ペレット及び不活性ガスを気密封止する半導体
装置の製造方法において、前記ベース基板のペレット塔
載面上に半導体ペレットを塔載する工程と、前記ベース
基板のペレット塔載面の封止領域に第１封止材及びこの
第１封止材に比べて融点が高い第２封止材を介在して前
記封止用キャップの封止領域を不活性ガスの雰囲気中で
載置し、その後、前記第１封止材が溶融するまで熱処理
を施す工程と、前記第１封止材を凝固し、この第１封止
材で前記ベース基板の封止領域と封止用キャップの封止
領域とを固着する工程とを備える。The sealing area of the pellet tower mounting surface of the base substrate and the sealing area of the sealing cap are fixed with a sealing material, and the semiconductor pellets and the semiconductor pellets are formed in the cavity formed by the base substrate and the sealing cap. In a method of manufacturing a semiconductor device in which an inert gas is hermetically sealed, a step of mounting semiconductor pellets on a pellet mounting surface of the base substrate, and a first sealing in a sealing region of the pellet mounting surface of the base substrate. The sealing region of the sealing cap is placed in an atmosphere of an inert gas with a stopper and a second sealing material having a melting point higher than that of the first sealing material, and then the first sealing material is used. A step of performing heat treatment until the sealing material melts, and solidifying the first sealing material, and fixing the sealing area of the base substrate and the sealing area of the sealing cap with the first sealing material. And a process.
【００１１】[0011]
【作用】上述した手段によれば、ベース基板の封止部と
封止用キャップの封止部との間の間隙を第２封止材で保
持しながらベース基板の封止領域と封止用キャップの封
止領域とを第１封止材で固着することができるので、封
止用キャップのベース基板側への沈み込みによるキャビ
ティ内とキャビティ外との圧力差の発生を防止すること
ができる。この結果、圧力差による不活性ガスの移動
（キャビティ内からキャビティ外に向う不活性ガスの流
れ）が生じないので、封止材に生じるボイドの発生を防
止でき、半導体装置の気密性を高めることができる。According to the above-described means, the second sealing material holds the gap between the sealing portion of the base substrate and the sealing portion of the sealing cap, and the sealing region of the base substrate and the sealing portion. Since the sealing region of the cap can be fixed with the first sealing material, it is possible to prevent a pressure difference between the inside and the outside of the cavity due to the sinking of the sealing cap toward the base substrate. . As a result, since the inert gas does not move due to the pressure difference (the flow of the inert gas from the inside of the cavity to the outside of the cavity), it is possible to prevent the generation of voids in the encapsulating material and improve the airtightness of the semiconductor device. You can
【００１２】[0012]
【実施例】以下、本発明の構成について、フェースダウ
ン方式を採用する半導体装置に本発明を適用した一実施
例とともに説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below together with an embodiment in which the present invention is applied to a semiconductor device adopting a face-down method.
【００１３】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１４】本発明の一実施例であるフェースダウン方
式を採用する半導体装置の概略構成を図１(斜視図)及び
図２(図１に示すＡ−Ａ切断線で切った断面図)に示す。A schematic structure of a semiconductor device adopting a face-down method which is an embodiment of the present invention is shown in FIG. 1 (perspective view) and FIG. 2 (cross-sectional view taken along the line AA shown in FIG. 1). .
【００１５】図１及び図２に示すように、本実施例のフ
ェースダウン方式を採用する半導体装置１は、ベース基
板２のペレット塔載面の封止領域２Ａと封止用キャップ
３の封止領域３Ａとを封止材７で固着し、このベース基
板２及び封止用キャップ３で形成されるキャビティ４内
に半導体ペレット５及び不活性ガスを気密封止する。As shown in FIGS. 1 and 2, in the semiconductor device 1 adopting the face-down method of this embodiment, the sealing region 2A on the pellet tower mounting surface of the base substrate 2 and the sealing cap 3 are sealed. The region 3A is fixed to the region 3A with the sealing material 7, and the semiconductor pellet 5 and the inert gas are hermetically sealed in the cavity 4 formed by the base substrate 2 and the sealing cap 3.
【００１６】前記ベース基板２は、例えばムライトで形
成され、図示していないが、多層配線構造で構成され
る。ベース基板２のペレット塔載面には電極２Ｂが複数
配列され、ベース基板２のペレット塔載面と対向する裏
面には電極２Ｃが複数配列される。この電極２Ｂ、電極
２Ｃの夫々は前記多層配線構造の配線を介して電気的に
接続される。The base substrate 2 is formed of, for example, mullite and has a multilayer wiring structure (not shown). A plurality of electrodes 2B are arranged on the pellet tower mounting surface of the base substrate 2, and a plurality of electrodes 2C are arranged on the back surface of the base substrate 2 facing the pellet tower mounting surface. The electrodes 2B and 2C are electrically connected to each other through the wiring of the multilayer wiring structure.
【００１７】前記半導体ペレット５はベース基板２のペ
レット塔載面上に塔載される。この半導体ペレット５の
素子形成面(図２中、下面)には論理回路システム、記憶
回路システム或はそれらの混合回路システムが塔載され
る。また、半導体ペレット５の素子形成面上には複数の
外部端子(ボンディングパッド)５Ａが配列される。The semiconductor pellets 5 are mounted on the pellet mounting surface of the base substrate 2. A logic circuit system, a memory circuit system or a mixed circuit system thereof is mounted on the element forming surface (lower surface in FIG. 2) of the semiconductor pellet 5. A plurality of external terminals (bonding pads) 5A are arranged on the element forming surface of the semiconductor pellet 5.
【００１８】前記ベース基板２の電極２Ｂ、半導体ペレ
ット５の電極５Ａの夫々は半田電極(バンプ電極、ＣＣ
Ｂ電極又は突起電極)６を介在して電気的及び機械的に
接続される。つまり、半導体ペレット５はベース基板２
のペレット塔載面上にフェースダウン方式で塔載され
る。Each of the electrode 2B of the base substrate 2 and the electrode 5A of the semiconductor pellet 5 is a solder electrode (bump electrode, CC
Electrically and mechanically connected via a B electrode or a protruding electrode 6). That is, the semiconductor pellet 5 is the base substrate 2
The pellets are mounted face down on the pellet mounting surface.
【００１９】前記封止用キャップ３は、断面形状がコの
字形状に形成され、ベース基板２とで半導体ペレット５
及び不活性ガスを気密封止するキャビティ４を構成す
る。封止用キャップ３は例えば窒化アルミニウムで形成
される。The sealing cap 3 has a U-shaped cross section, and the semiconductor pellet 5 together with the base substrate 2.
And a cavity 4 for hermetically sealing the inert gas. The sealing cap 3 is made of, for example, aluminum nitride.
【００２０】前記ベース基板２の封止領域２Ａと封止用
キャップ３の封止領域３Ａとは封止材７で固着される。
この封止材７は、キャビティ４内からキャビティ４外に
向って順次配置された封止材(第１封止材)７Ａ及びこの
封止材７Ａに比べて融点が高い封止材(第２封止材)７Ｂ
で構成される。キャビティ４の内側に配置された封止材
７Ａは例えばＰｂ−Ｓｎ系合金(４０［重量％］Ｐｂ−
６０［重量％］Ｓｎ)で形成される。このＰｂ−Ｓｎ系
合金は、１８５〜１９０［℃］程度の融点を有する。キ
ャビティ４の外側に配置された封止材７Ｂは例えばＰｂ
−Ｓｎ系合金（９５［重量％］Ｐｂ−５［重量％］Ｓ
ｎ）で形成される。このＰｂ−Ｓｎ系合金は３１０〜３
１５［℃］程度の融点を有する。The sealing region 2A of the base substrate 2 and the sealing region 3A of the sealing cap 3 are fixed to each other with a sealing material 7.
The sealing material 7 includes a sealing material (first sealing material) 7A sequentially arranged from the inside of the cavity 4 to the outside of the cavity 4 and a sealing material (second sealing material) having a higher melting point than the sealing material 7A. Sealing material) 7B
Composed of. The sealing material 7A arranged inside the cavity 4 is made of, for example, Pb-Sn alloy (40 [wt%] Pb-
60 [wt%] Sn). This Pb-Sn alloy has a melting point of about 185 to 190 [° C]. The sealing material 7B arranged outside the cavity 4 is, for example, Pb.
-Sn alloy (95 [wt%] Pb-5 [wt%] S
n). This Pb-Sn alloy is 310-3
It has a melting point of about 15 [° C.].
【００２１】前記ベース基板２の封止領域２Ａ、封止用
キャップ３の封止領域３Ａの夫々には、封止材７のぬれ
性を確保する目的として下地金属層２Ｄ、下地金属層３
Ｂの夫々が形成される。この下地金属層２Ｄ、下地金属
層３Ｂの夫々は、例えばＴｉ膜、Ｎｉ膜、Ａｕ膜の夫々
を順次蒸着した複合膜で形成される。In each of the sealing region 2A of the base substrate 2 and the sealing region 3A of the sealing cap 3, the base metal layer 2D and the base metal layer 3 are provided for the purpose of ensuring the wettability of the sealing material 7.
Each of B is formed. Each of the base metal layer 2D and the base metal layer 3B is formed of a composite film in which, for example, a Ti film, a Ni film, and an Au film are sequentially deposited.
【００２２】次に、前記半導体装置の組立プロセスにつ
いて、図３（組立プロセスの所定の工程での要部断面
図）及び図３(封止材の斜視図)を用いて簡単に説明す
る。Next, the assembling process of the semiconductor device will be briefly described with reference to FIG. 3 (a cross-sectional view of a main part in a predetermined step of the assembling process) and FIG. 3 (a perspective view of a sealing material).
【００２３】まず、ベース基板２のペレット塔載面上に
フェースダウン方式で半導体ペレット３を塔載する。First, the semiconductor pellets 3 are mounted on the pellet mounting surface of the base substrate 2 by a face-down method.
【００２４】次に、図３に示すように、不活性ガス(例
えば窒素ガス若しくはアルゴンガス)の雰囲気中におい
て、前記ベース基板２のペレット塔載面の封止領域２Ａ
に封止材７を介在して封止用キャップ３の封止領域３Ａ
を載置する。封止材７は、図４に示すように、封止用キ
ャップ３の封止領域３Ａの形状に沿って平面形状がリン
グ形状で形成される。この封止材７は、そのリング形状
の内側から外側に向って封止材７Ａ及び封止材７Ｂを順
次配置した構成になっている。この後、封止材７の封止
材７Ａが溶融するまで熱処理を施す。この時、封止材７
は融点の異なる封止材７Ａ及び封止材７Ｂで構成されて
いるので、ベース基板２の封止領域２Ａと封止用キャッ
プ３の封止領域３Ａとの間隙を封止材７Ｂで保持でき、
封止用キャップ３のベース基板２側への沈み込みを防止
することができる。Next, as shown in FIG. 3, in the atmosphere of an inert gas (for example, nitrogen gas or argon gas), the sealing region 2A on the pellet tower mounting surface of the base substrate 2 is sealed.
The sealing region 3A of the sealing cap 3 with the sealing material 7 interposed therebetween.
To place. As shown in FIG. 4, the sealing material 7 is formed in a ring shape in a plan view along the shape of the sealing region 3A of the sealing cap 3. The sealing material 7 has a structure in which a sealing material 7A and a sealing material 7B are sequentially arranged from the inside to the outside of the ring shape. After that, heat treatment is performed until the sealing material 7A of the sealing material 7 is melted. At this time, the sealing material 7
Is composed of the sealing material 7A and the sealing material 7B having different melting points, the gap between the sealing area 2A of the base substrate 2 and the sealing area 3A of the sealing cap 3 can be held by the sealing material 7B. ,
It is possible to prevent the sealing cap 3 from sinking to the base substrate 2 side.
【００２５】次に、前記封止材７Ａを凝固し、この封止
材７Ａでベース基板２の封止領域２Ａと封止用キャップ
３の封止領域３Ａとを固着する。これにより、ベース基
板２及び封止用キャップ３で形成されるキャビティ４内
に半導体ペレット５及び不活性ガスが気密封止される。Next, the sealing material 7A is solidified, and the sealing area 2A of the base substrate 2 and the sealing area 3A of the sealing cap 3 are fixed by this sealing material 7A. As a result, the semiconductor pellet 5 and the inert gas are hermetically sealed in the cavity 4 formed by the base substrate 2 and the sealing cap 3.
【００２６】このように、半導体装置１の製造方法にお
いて、ベース基板２のペレット塔載面上に半導体ペレッ
ト５を塔載する工程と、前記ベース基板２のペレット塔
載面の封止領域２Ａに封止材７Ａ及びこの封止材７Ａに
比べて融点が高い封止材７Ｂを介在して前記封止用キャ
ップ３の封止領域３Ａを不活性ガスの雰囲気中で載置
し、その後、前記封止材７Ａが溶融するまで熱処理を施
す工程と、前記封止材７Ａを凝固し、この封止材７Ａで
前記ベース基板２の封止領域２Ａと封止用キャップ３の
封止領域３Ａとを固着する工程とを備える。これによ
り、ベース基板２の封止領域２Ａと封止用キャップ３の
封止領域３Ａとの間の間隙を封止材７Ｂで保持しながら
ベース基板２の封止領域２Ａと封止用キャップ３の封止
領域３Ａとを封止材７Ａで固着することができるので、
封止用キャップ３のベース基板２側への沈み込みによる
キャビティ４内とキャビティ４外との圧力差の発生を防
止することができる。この結果、圧力差による不活性ガ
スの移動（キャビティ内からキャビティ外に向う不活性
ガスの流れ）が生じないので、封止材７に生じるボイド
の発生を防止でき、半導体装置の気密性を高めることが
できる。As described above, in the method of manufacturing the semiconductor device 1, the step of mounting the semiconductor pellets 5 on the pellet mounting surface of the base substrate 2 and the sealing region 2A on the pellet mounting surface of the base substrate 2 are described. The sealing region 3A of the sealing cap 3 is placed in an inert gas atmosphere with the sealing material 7A and the sealing material 7B having a melting point higher than that of the sealing material 7A interposed, and then A step of performing a heat treatment until the sealing material 7A is melted, the sealing material 7A is solidified, and the sealing area 7A of the base substrate 2 and the sealing area 3A of the sealing cap 3 are solidified by the sealing material 7A. And a step of fixing. As a result, the sealing region 2A of the base substrate 2 and the sealing cap 3 are held while the gap between the sealing region 2A of the base substrate 2 and the sealing region 3A of the sealing cap 3 is held by the sealing material 7B. Since the sealing area 3A can be fixed with the sealing material 7A,
It is possible to prevent a pressure difference between the inside of the cavity 4 and the outside of the cavity 4 due to the sinking of the sealing cap 3 toward the base substrate 2 side. As a result, the movement of the inert gas due to the pressure difference (the flow of the inert gas from the inside of the cavity to the outside of the cavity) does not occur, so that the generation of voids in the sealing material 7 can be prevented and the airtightness of the semiconductor device is improved. be able to.
【００２７】なお、封止材７は、封止材７Ａ、封止材７
Ｂの夫々をキャビティ４外からキャビティ４内に向って
順次配置した構成にしてもよい。The sealing material 7 includes the sealing material 7A and the sealing material 7
Each of B may be sequentially arranged from the outside of the cavity 4 toward the inside of the cavity 4.
【００２８】また、封止材７は、図５(封止用キャップ
の背面図)及び図６（図５に示すＢ−Ｂ切断線で切った
断面図）に示すように、封止用キャップ３の各辺毎の封
止領域３Ａの一部に封止材７Ｂを設け、この封止材７Ｂ
上を含む封止用キャップ３の封止領域３Ｂの他部上に封
止材７Ａを設けた構成(一部２層構造)にしてもよい。As shown in FIG. 5 (rear view of the sealing cap) and FIG. 6 (cross-sectional view taken along the line B--B shown in FIG. 5), the sealing material 7 is a sealing cap. The sealing material 7B is provided in a part of the sealing area 3A for each side of the sealing material 7B.
The sealing material 3A may be provided on the other part of the sealing region 3B of the sealing cap 3 including the above (partial two-layer structure).
【００２９】また、前記封止材７Ｂは、図示していない
が、封止用キャップ３の４つの角部の夫々の封止領域３
Ａに設けてもよい。Although not shown, the sealing material 7B has sealing regions 3 at each of the four corners of the sealing cap 3.
It may be provided in A.
【００３０】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３１】例えば、本発明は、ベース基板のペレット
塔載面上にボンディングワイヤ方式で半導体ペレットを
塔載する半導体装置に適用できる。For example, the present invention can be applied to a semiconductor device in which semiconductor pellets are mounted on the pellet mounting surface of a base substrate by a bonding wire method.
【００３２】[0032]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３３】半導体装置の気密性を高めることができ
る。The airtightness of the semiconductor device can be improved.
【図１】 本発明の一実施例である半導体装置の斜視
図。FIG. 1 is a perspective view of a semiconductor device that is an embodiment of the present invention.
【図２】 図１に示すＡ−Ａ切断線で切った断面図。FIG. 2 is a cross-sectional view taken along the line AA shown in FIG.
【図３】 前記半導体装置の組立プロセスを説明する所
定の工程での要部断面図。FIG. 3 is a sectional view of an essential part in a predetermined step, for explaining the assembly process of the semiconductor device.
【図４】 封止材の斜視図。FIG. 4 is a perspective view of a sealing material.
【図５】 本発明の変形例を示す封止用キャップの背面
図。FIG. 5 is a rear view of a sealing cap showing a modified example of the present invention.
【図６】 図５に示すＢ−Ｂ切断線で切った断面図。6 is a cross-sectional view taken along the line BB shown in FIG.
１…半導体装置、２…ベース基板、２Ａ…封止領域、３
…封止用キャップ、３Ａ…封止領域、４…キャビティ、
５…半導体ペレット、６…半田電極、７…封止材、７Ａ
…封止材、７Ｂ…封止材。1 ... Semiconductor device, 2 ... Base substrate, 2A ... Sealing region, 3
... sealing cap, 3A ... sealing region, 4 ... cavity,
5 ... Semiconductor pellet, 6 ... Solder electrode, 7 ... Sealing material, 7A
... Sealing material, 7B ... Sealing material.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 細江 英之 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hideyuki Hosoe 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center
Claims (2)
と封止用キャップの封止領域とを封止材で固着し、この
ベース基板及び封止用キャップで形成されるキャビティ
内に半導体ペレット及び不活性ガスを気密封止する半導
体装置の製造方法において、前記ベース基板のペレット
塔載面上に半導体ペレットを塔載する工程と、前記ベー
ス基板のペレット塔載面の封止領域に第１封止材及びこ
の第１封止材に比べて融点が高い第２封止材を介在して
前記封止用キャップの封止領域を不活性ガスの雰囲気中
で載置し、その後、前記第１封止材が溶融するまで熱処
理を施す工程と、前記第１封止材を凝固し、この第１封
止材で前記ベース基板の封止領域と封止用キャップの封
止領域とを固着する工程とを備えたことを特徴とする半
導体装置の製造方法。1. A sealing region of a base substrate on which a pellet is mounted and a sealing region of a sealing cap are fixed by a sealing material, and a semiconductor is placed in a cavity formed by the base substrate and the sealing cap. In a method of manufacturing a semiconductor device in which a pellet and an inert gas are hermetically sealed, a step of mounting a semiconductor pellet on a pellet tower mounting surface of the base substrate, and a step of sealing the pellet tower mounting surface of the base substrate in a sealing region 1 sealing material and the 2nd sealing material whose melting point is higher than this 1st sealing material are interposed, and the sealing area | region of the said cap is mounted in the atmosphere of inert gas, Then, the said A step of performing a heat treatment until the first sealing material is melted, solidifying the first sealing material, and using the first sealing material to form a sealing region of the base substrate and a sealing region of the sealing cap. A method for manufacturing a semiconductor device, which comprises a step of fixing the semiconductor device. .
前記キャビティ内からキャビティ外に向って、若しくは
キャビティ外からキャビティ内に向って順次配置される
ことを特徴とする請求項１に記載の半導体装置の製造方
法。2. Each of the first sealing material and the second sealing material,
The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is sequentially arranged from inside the cavity to outside the cavity or from outside the cavity to inside the cavity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5334434A JPH07201731A (en) | 1993-12-28 | 1993-12-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5334434A JPH07201731A (en) | 1993-12-28 | 1993-12-28 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07201731A true JPH07201731A (en) | 1995-08-04 |
Family
ID=18277343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5334434A Withdrawn JPH07201731A (en) | 1993-12-28 | 1993-12-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07201731A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154173B2 (en) * | 2003-06-06 | 2006-12-26 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
-
1993
- 1993-12-28 JP JP5334434A patent/JPH07201731A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7154173B2 (en) * | 2003-06-06 | 2006-12-26 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method of the same |
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