JPH07193488A - Level shifter circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To speed up signal processing. In a level shifter circuit including inverters 1 and 2, P channel MOS transistors 7 and 8 connected to a high power supply voltage source 4, N channel MOS transistors 5 and 6 and an inverter 3, an N channel MOS is provided. Transistors 13 and 14 are provided, the high power supply voltage source 4 is connected to the drains of the N-channel MOS transistors 13 and 14, and the gate of the N-channel MOS transistor 13 has an output of the inverter 2 and the gate of the N-channel MOS transistor 14 has a gate. The outputs of the inverters 1 are connected to each other, and the source of the N-channel MOS transistor 13 is connected to the P-channel MOS transistor 7
N-channel MOS transistor 1 connected to the gate of
The gate of the P-channel MOS transistor 8 and the input of the inverter 3 were connected to the source of 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit which is indispensable when connecting circuits having different power supply voltages.

[0002]

2. Description of the Related Art A conventional level shifter circuit will be described.

FIG. 2 shows a conventional level shifter circuit,
Reference numerals 1 and 2 are low power supply voltage operated inverters, 3 is a high power supply voltage operated inverter, 4 is a high power supply voltage source, 5 and 6 are N channel (hereinafter referred to as Nch) MOS transistors, and 7 and 8 are P channel (hereinafter referred to as Pch). MOS transistor, 9 is an input signal terminal from the low power supply voltage operating circuit, 10
Is an output terminal to the high power supply voltage operating circuit, and 11 is NchMO
A node in which the drain of the S transistor 5 and the drain of the PchMOS transistor 7 are connected, and 12 is an NchMO
This is a node to which the drain of the S transistor 6 and the drain of the PchMOS transistor 8 are connected.

The operation of the level shifter circuit configured as described above will be described below.

Input signal terminal 9 from the low power supply voltage operating circuit
When a signal that changes from a lower level to a higher level is input, the output signal of the low power supply voltage operating inverter 1 changes from a high level to a low level. At that time, the ON resistance of the NchMOS transistor 6 is gradually increased, and
The voltage between the source and drain of the S transistor 6 rises. Almost at the same time, the output signal from the low power supply voltage operating inverter 2 changes from low level to high level, and NchMOS
The transistor 5 becomes conductive and the on-resistance gradually decreases,
The source-drain voltage of the NchMOS transistor 5 decreases.

By the operation of the NchMOS transistors 5 and 6 as described above, the gate voltage of the PchMOS transistor 8 drops and the drain voltage of the PchMOS transistor 8 rises. As a result, the gate voltage of the PchMOS transistor 7 rises, and finally the signal at the input signal terminal 9 from the low power supply voltage operating circuit becomes high level,
The NchMOS transistor 5 becomes completely conductive, and the node 1
The voltage of 1 becomes 0V. NchMOS transistor 6 is completely turned off, and the voltage of node 12 becomes equal to that of high power supply voltage source 4. At that time, the PchMOS transistor 7 becomes non-conductive, and the PchMOS transistor 8
Are conducted, and the high power supply voltage operating inverter 3 makes the potential of the output terminal to the high power supply voltage operating circuit equal to the high power supply voltage.

On the other hand, when a signal that changes from a high level to a low level is input from the input signal terminal 9 from the low power supply voltage operating circuit, the output signal of the low power supply voltage operating inverter 1 changes from a low level to a high level. To do. At that time, Nch
The MOS transistor 6 becomes conductive, and the on-resistance gradually decreases, so that the voltage between the source and drain of the NchMOS transistor 6 decreases. Almost at the same time, the output signal from the low power supply voltage operating inverter 2 changes from high level to low level, the on-resistance of the NchMOS transistor 5 gradually increases, and the source-drain voltage of the NchMOS transistor 5 increases.

By the operation of the NchMOS transistors 5 and 6 as described above, the gate voltage of the PchMOS transistor 7 decreases and the drain voltage of the PchMOS transistor 7 increases. As a result, the gate voltage of the PchMOS transistor 8 rises. Finally, when the signal at the input signal terminal 9 from the low power supply voltage operating circuit becomes low level, the NchMOS transistor 5 becomes completely non-conductive, and the voltage of the node 11 becomes equal to that of the high power supply voltage source 4.
Further, the NchMOS transistor 6 is brought into full conduction, and the voltage of the node 12 becomes 0V. At that time, PchMOS
The transistor 7 becomes conductive, and the PchMOS transistor 8
Is non-conductive, and the potential of the output terminal to the high power supply voltage operating circuit becomes 0V by the high power supply voltage operating inverter 3.

[0009]

With the conventional level shifter circuit, the output signal from the low power supply voltage operating circuit can be input to the high power supply voltage operating circuit.

However, in the above-described conventional configuration, for example, when the input signal to the input signal terminal 9 changes from the high level to the low level, the NchMOS transistor 6 is turned on.
Is turned on, the PchMOS transistor 7 becomes conductive, and the node 11 changes from the low level to the high level, which requires two steps for the operation. On the other hand, when the input signal of the input signal terminal 9 changes from the low level to the high level, similarly, two steps are required for the node 12 to change from the low level to the high level, which makes high-speed operation difficult.

In the present invention, the above-mentioned conventional problems are solved, and the NchMOS transistors 6 and 7 are used to make the node 1
It is an object of the present invention to provide a level shifter circuit in which the potential of the node 1 or the node 12 can be changed in one step so that the signal level conversion from the low power supply voltage operating circuit to the high power supply voltage operating circuit is accelerated. .

[0012]

To achieve this object, a level shifter circuit of the present invention has a drain connected to a high power supply voltage source, a gate connected to the output of a low power supply voltage operating inverter, and a source connected to two sources. Of the PchMOS transistors, the drain of the first PchMOS transistor, the gate of the second PchMOS transistor, and the second NchM
An NchMOS transistor connected to the drain of the OS transistor and an NchMOS transistor whose source is connected to the gate of the first PchMOS transistor, the drain of the second PchMOS transistor and the drain of the first NchMOS transistor are added to the conventional level shifter circuit. It becomes a circuit configuration.

[0013]

Operation: NchMO with drain connected to high power supply voltage source
The S-transistor allows the PchMOS transistor to start turning off directly without waiting for the other PchMOS transistor to turn on, so that the drain voltage of the PchMOS transistor can be reduced at a high speed. The conversion of the signal level to the operating circuit becomes faster.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a level shifter circuit according to an embodiment of the present invention. 1, 2 are low power supply voltage operated inverters, 3 are high power supply voltage operated inverters, 4 are high power supply voltage sources, 5, 6, 13 and 14 are NchMOS transistors,
Reference numerals 7 and 8 are PchMOS transistors, 9 is an input signal terminal from the low power supply voltage operating circuit, 10 is an output terminal to the high power supply voltage operating circuit, 11 is a node connecting the drain of the NchMOS transistor 5 and the PchMOS transistor 7, and 12 Is the drain of the NchMOS transistor 6 and P
It is a node to which the drain of the chMOS transistor 8 is connected.

The operation of the level shifter circuit configured as described above will be described below.

Input signal terminal 9 from the low power supply voltage operating circuit
When a signal that changes from a lower level to a higher level is input, the output signal of the low power supply voltage operating inverter 1 changes from a high level to a low level. At that time, NchMOS
The on resistances of the transistors 6 and 14 gradually increase to Nc.
The source-drain voltage of the hMOS transistors 6 and 14 rises. Almost at the same time, the output signal from the low power supply voltage operating inverter 2 changes from low level to high level, and N
The on-resistances of the n-channel MOS transistors 5 and 13 gradually decrease and the N-ch MOS transistors 5 and 13 are reduced.
The source-drain voltage of No. 3 decreases. NchMOS
When the transistor 13 is turned on, the gate potential of the PchMOS transistor 7 rises to the intermediate potential and the on resistance increases. As a result, the potential of the node 11 is lowered by the NchMOS transistor 5. At the same time, the on-resistance of the PchMOS transistor 8 decreases due to the decrease in the potential of the node 11, and the potential of the node 12 rises. When the input signal terminal from the completely low power supply voltage operating circuit becomes high level, NchMOS transistors 5 and 13
Is on, NchMOS transistors 6 and 14 are off, P
The chMOS transistor 7 is turned off and the PchMOS transistor 8 is turned on, and the potential of the high power supply voltage operation circuit output terminal 10 becomes equal to the high power supply voltage and becomes stable.

On the other hand, when a signal changing from a high level to a low level is input from the input signal terminal 9 from the low power supply voltage operating circuit, the output signal of the low power supply voltage operating inverter 1 changes from a low level to a high level. . At that time, NchM
The on-resistances of the OS transistors 6 and 14 gradually decrease, and the source-drain voltage of the NchMOS transistors 6 and 14 decreases. Almost at the same time, the output signal from the low power supply voltage operating inverter 2 changes from the high level to the low level, the NchMOS transistors 5 and 13 become conductive and their on-resistance gradually decreases, and the source / drain of the NchMOS transistors 5 and 13 are reduced. Voltage rises. Nc
When the hMOS transistor 14 is turned on, PchM
The gate potential of the OS transistor 8 rises to the intermediate potential and its on-resistance increases. As a result, NchM
The potential of the node 12 is lowered by the OS transistor 6. At the same time, due to the decrease in the potential of the node 12, Pc
The on resistance of the hMOS transistor 7 decreases, and the node 1
The potential of 1 rises. When the input signal terminal from the completely low power supply voltage operating circuit becomes low level, the NchMOS transistors 5 and 13 are turned off, and the NchMOS transistor 6 is turned off.
14 is on, PchMOS transistor 7 is on, Pc
The hMOS transistor 8 is turned off, and the potential of the high power supply voltage operation circuit output terminal 10 stabilizes at 0V.

[0019]

According to the present invention, by providing the NchMOS transistor, the P state that holds (turns on) the previous state is achieved.
Since it has the effect of turning off the chMOS transistor quickly, the transition time of operation (the time during which the through current flows) is shortened, and the level shifter circuit, which is indispensable when a different power supply operation circuit is integrated into one chip with a MOS integrated circuit, is speeded up. It is possible to provide an electronic circuit / system that can achieve low power consumption, high speed, and high performance.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a level shifter circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a conventional level shifter circuit.

[Explanation of symbols]

1, 2 Low power supply voltage operation inverter 3 High power supply voltage operation inverter 4 High power supply voltage source 5, 6 N channel MOS transistor 7, 8 P channel MOS transistor 9 Input signal terminal (input signal terminal of low power supply voltage operating circuit) 10 High Output terminal to power supply voltage operating circuit 11, 12 node 13, 14 N-channel MOS transistor

Claims (1)

[Claims] 1. Two Ps having a high power supply voltage connected to their sources.
A channel MOS transistor, the output signal of the low power supply voltage operating circuit is connected to the gate of the first N-channel MOS transistor, and the drain of the first N-channel MOS transistor is connected to the gate of the first P-channel MOS transistor. The second N-channel M-channel transistor is connected to the drain of the second P-channel MOS transistor, and the signal of the opposite phase of the output signal of the low power supply voltage operating circuit is connected to the gate of the second N-channel MOS transistor.
The drain of the OS transistor is the first P-channel MO
In addition to the configuration in which the gate of the S transistor and the drain of the second P channel MOS transistor are connected, the drains of the third and fourth N channel MOS transistors are connected to a high power supply voltage source, and the third N channel MOS transistor is connected. Is connected to the gate of the first N-channel MOS transistor, the source of the third N-channel MOS transistor is connected to the drain of the first P-channel MOS transistor and the gate of the second P-channel MOS transistor, and The gate of the fourth N-channel MOS transistor is connected to the gate of the second N-channel MOS transistor, and the source of the fourth N-channel MOS transistor is connected to the gate of the first P-channel MOS transistor and the second P-channel MOS transistor. Drain and high power Connected to the input of the pressure operation inverter,
A level shifter circuit that uses the output of a high power supply voltage operating inverter as the output to a high power supply voltage operating circuit.