JP2009171084A - Level shifter circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shifter circuit where an operation is fast even when the number of elements is small. <P>SOLUTION: When an input voltage Vin becomes a grounding voltage Vss and the gate voltage (voltage of the input terminal of a level shifter part) of a PMOS 31 and an NMOS 21 becomes a power supply voltage Vdd, an NMOS 23 is turned on. Thus, the drain voltage (voltage of the output terminal of the level shifter part) of a PMOS 33 and an NMOS 22 tends to become a power supply voltage Vpp, and an output voltage Vout tends to become the grounding voltage Vss. That is, the operation of the level shifter circuit becomes fast. Also, since the number of inverters becomes smaller compared to a conventional level shifter circuit, the number of elements is reduced. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a level shifter circuit.

  A conventional level shifter circuit will be described. FIG. 2 is a diagram showing a conventional level shifter circuit.

  When the input terminal of the level shifter circuit goes low, the gates of PMOS M5 and NMOS M2 go high, PMOS M5 turns off, NMOS M2 turns on, and node P1 goes low. Then, the PMOS M3 is turned on. Further, the gate of the PMOS M6 becomes low, and the PMOS M6 is turned on. Therefore, the node P2 becomes high and the output terminal of the level shifter circuit becomes low. This signal path is defined as path B.

  When the input terminal of the level shifter circuit goes low, the gates of PMOS M5 and NMOS M2 go high, PMOS M5 turns off, NMOS M2 turns on, and node P1 goes low. Then, the node P3 becomes high, and the output terminal of the level shifter circuit becomes low. This signal path is referred to as path A.

As described above, routes A to B exist, and route A is faster than route B. This path A speeds up the operation of the level shifter circuit (see, for example, Patent Document 1).
Japanese Patent Laying-Open No. 2007-329818 (FIG. 5)

  However, in the technique disclosed in Patent Document 1, inverters I1 to I5 are necessary, and the number of elements increases.

  The present invention has been made in view of the above problems, and provides a level shifter circuit that operates quickly even when the number of elements is small.

  In order to solve the above problems, the present invention provides a level shifter unit that level-shifts an input voltage to a predetermined voltage in a level shifter circuit, a source is provided at an output terminal of the level shifter unit, and a power supply voltage is supplied to a drain. There is provided a level shifter circuit comprising an NMOS that is turned on when an input terminal of the level shifter portion becomes high.

  In the present invention, when the input terminal of the level shifter unit becomes high, the NMOS is turned on, so that the output terminal of the level shifter unit easily becomes high. That is, the operation of the level shifter circuit becomes faster.

  Further, since the number of inverters is reduced as compared with the conventional level shifter circuit, the number of elements is reduced.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, the configuration of the level shifter circuit will be described. FIG. 1 is a diagram illustrating a level shifter circuit.

  The level shifter circuit includes inverters 11 to 13, NMOSs 21 to 23, and PMOSs 31 to 34.

  The inverter 11 is supplied with the power supply voltage Vdd and the ground voltage Vss, the input terminal is connected to the input terminal of the level shifter circuit, and the output terminal is connected to the gates of the NMOS 21, PMOS 31, and NMOS 23. The inverter 12 is supplied with the power supply voltage Vdd and the ground voltage Vss, the input terminal is connected to the output terminal of the inverter 11, and the output terminal is connected to the gates of the NMOS 22 and the PMOS 33. The inverter 13 is supplied with the power supply voltage Vpp and the ground voltage Vss, the input terminal is connected to the gate of the PMOS 32, the drain of the PMOS 33, the drain of the NMOS 22 and the source of the NMOS 23, and the output terminal is connected to the output terminal of the level shifter circuit. Yes. In the PMOS 32, the power supply voltage Vpp is supplied to the source, and the drain is connected to the source of the PMOS 31. The drain of the PMOS 31 is connected to the drain of the NMOS 21 and the gate of the PMOS 34. The NMOS 21 is supplied with the ground voltage Vss at its source. In the PMOS 34, the power supply voltage Vpp is supplied to the source, and the drain is connected to the source of the PMOS 33. The NMOS 22 is supplied with the ground voltage Vss at the source. The NMOS 23 is supplied with the power supply voltage Vpp at its drain. The PMOSs 31 to 34 are supplied with a power supply terminal Vpp at their back gates. The NMOSs 21 to 23 are supplied with the ground terminal Vss at their back gates.

  Here, since the threshold voltage of the NMOS 23 is lower than the threshold voltages of the NMOSs 21 to 22, the NMOS 23 is more likely to be turned on than the NMOSs 21 to 22. The power supply voltage Vpp is higher than the power supply voltage Vdd.

  The inverter 12, the NMOSs 21 to 22, and the PMOSs 31 to 34 constitute a level shift unit. The level shift unit inputs a voltage to the gates of the PMOS 31 and the NMOS 21 (input terminals of the level shifter unit), shifts the input voltage to a predetermined voltage, and transfers the predetermined voltage to the drains of the PMOS 33 and the NMOS 22 (output of the level shifter unit). Terminal).

  Next, the operation of the level shifter circuit will be described.

  When the input voltage Vin becomes the ground voltage Vss, the inverter 11 causes the gate voltages of the PMOS 31 and the NMOS 21 (the voltage at the input terminal of the level shifter) to become the power supply voltage Vdd, the PMOS 31 is turned off, and the NMOS 21 is turned on. Then, the drain voltage of the NMOS 21 becomes the ground voltage Vss, and the PMOS 34 is turned on. Further, the inverter 12 causes the gate voltages of the PMOS 33 and the NMOS 22 to become the ground voltage Vss, the PMOS 33 is turned on, and the NMOS 22 is turned off. Therefore, the drain voltage of the PMOS 33 and NMOS 22 (the voltage at the output terminal of the level shifter) becomes the power supply voltage Vpp, and the output voltage Vout becomes the ground voltage Vss by the inverter 13.

  When the input voltage Vin becomes the ground voltage Vss, the inverter 11 causes the gate voltage of the PMOS 31 and the NMOS 21 (the voltage at the input terminal of the level shifter) to become the power supply voltage Vdd, and the gate voltage of the NMOS 23 becomes the power supply voltage Vdd. , NMOS 23 is turned on. Then, there are two paths between the drains of the PMOS 33 and the NMOS 22 and the power supply terminal to which the power supply voltage Vpp is applied, a path through the PMOSs 33 to 34 and a path through the NMOS 23.

  During standby, the level shifter circuit is controlled so that the PMOSs 33 to 34 and the NMOS 23 are turned on, and the source voltage and drain voltage of the NMOS 23 become the power supply voltage Vpp. Then, it becomes difficult for the NMOS 23 to flow a leak current.

  In this way, when the input voltage Vin becomes the ground voltage Vss and the gate voltage of the PMOS 31 and NMOS 21 (the voltage at the input terminal of the level shifter section) becomes the power supply voltage Vdd, the NMOS 23 is turned on, and the drains of the PMOS 33 and NMOS 22 Between the power supply terminal to which the power supply voltage Vpp is applied, there are two paths, a path through the PMOSs 33 to 34 and a path through the NMOS 23, and the drains of the PMOS 33 and the NMOS 22 and the ground terminal to which the ground voltage Vss is applied. In between, there is one path through the NMOS 22. Therefore, the drain voltage of the PMOS 33 and NMOS 22 (the voltage at the output terminal of the level shifter unit) is likely to be the power supply voltage Vpp, and the output voltage Vout is likely to be the ground voltage Vss. That is, the operation of the level shifter circuit becomes faster.

  Further, since the number of inverters is reduced as compared with the conventional level shifter circuit, the number of elements is reduced. Therefore, the power consumption of the level shifter circuit is reduced. Further, the area of the level shifter circuit is reduced, and the cost is reduced.

It is a figure which shows a level shifter circuit. It is a figure which shows the conventional level shifter circuit.

Explanation of symbols

11-13 …… Inverters 21-23 …… NMOS 31-34 …… PMOS

Claims (3)

In the level shifter circuit,
A level shifter for level shifting the input voltage to a predetermined voltage;
A source provided at the output terminal of the level shifter unit, a power supply voltage is supplied to the drain, and an NMOS that is turned on when the input terminal of the level shifter unit is high;
A level shifter circuit comprising:   2. The level shifter circuit according to claim 1, wherein the threshold voltage of the NMOS is lower than the threshold voltage of the NMOS of the level shifter unit.   2. The level shifter circuit according to claim 1, wherein a gate of the NMOS is provided at an input terminal of the level shifter unit, and a ground voltage is supplied to a back gate.

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