JPH07184141A - Tuning device - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] Even if the received frequency has a large amount of offset with respect to the regular specified frequency, frequency correction can be performed in the minimum time,
It is possible to obtain regular tuning. A heterodyne receiver 6 that mixes and outputs a broadcast signal and a signal of an oscillation circuit 3 having a predetermined frequency difference, and demodulation circuit means 8 that demodulates the output signal 7 and outputs it as a baseband signal. And measuring circuit means 23 connected to its output terminal for measuring the frequency of the heterodyne signal and outputting it as frequency measurement data, and connected to the oscillating circuit to detect the frequency difference between the oscillating signal and the broadcast signal. The PLL circuit 20 that generates and supplies the control voltage 17 based on the result to change the oscillation frequency of the oscillation circuit, and the frequency measurement data whose frequency is measured by the measurement circuit means are input and the PLL circuit that changes the oscillation frequency of the oscillation circuit. And a microprocessor 21 for controlling the.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel selection device used in electronic equipment such as a color television receiver, and more particularly, when a broadcast signal which is not transmitted at a regular frequency is received, a time for frequency correction is set. The present invention relates to a tuning device that can be shortened to perform normal tuning.

[0002]

2. Description of the Related Art Generally, an electronic tuner using a variable diode is used as a channel selecting device in an electronic device such as a color television receiver, and a mainstream channel selecting device operates by driving the electronic tuner. Has become.

A channel selecting device constructed by using such an electronic tuner is, for example, a voltage synthesizer type, or a PLL (Phase Look Loop).
Abbreviation of phase-locked loop) There is a synthesizer type.

The above-mentioned PLL synthesizer type channel selecting device generally divides a local oscillation frequency to obtain a reference frequency and a CP.
The data from U is used for phase comparison with a prescaler output that is further divided, and the error output voltage drives the electronic tuner to perform tuning. In comparison, it has the great advantage of not requiring any presets.

Therefore, a conventional channel selecting apparatus using such a PLL synthesizer system is shown in FIG.

FIG. 5 is a block diagram showing an example of a conventional channel selecting device.

As shown in FIG. 5, the television receiver signal received by the antenna 1 for receiving the television signal is supplied to the RF amplifier 2 and this RF amplifier 2 is supplied.
After being amplified by, it is output to the mixer 4. Here, the mixer 4 is a separately provided oscillator (Voltage controlled Oscillator) capable of varying the oscillation frequency.
It is called a “lator” and is abbreviated as VOC hereinafter) 3. The number of oscillation frequencies supplied from 3 and the frequency of the supplied television signal are mixed to generate a beat signal as a beat frequency equal to the difference between the two original frequencies. Then, it is supplied to the IF amplifier 5 and is amplified by the IF amplifier 5 and output to the IF circuit 8.

That is, the received television signal is
After being amplified by the RF amplifier 2, the signal from the VCO 3 and the mixer 4 are heterodyned and output.
The RF amplifier 2, the VCO 3, the mixer 4, and the IF amplifier 5 together form a so-called superheterodyne tuner 6
Are configured.

The role of the tuner 6 is to select a specific signal from a large number of radio waves output from the antenna 1,
The oscillation frequency of the VCO 3 is controlled so as to output it as the IF signal 7, and the beat signal obtained by the mixer 4 is adjusted.

The relationship between the frequencies of the input signal and the output signal at this stage is, for example, fIF is an intermediate frequency and fVCO is
Is the oscillation frequency and fRF is the input signal frequency, then fIF = fVCO−fRF (1), and there is such a frequency relationship.

The output of the tuner 6 is guided to an IF circuit 8 connected to the tuner 6 for signal processing, amplified by an IF amplifier 9 constituting the IF circuit 8, and then detected by a video signal detector 10. Is demodulated as a baseband video signal by the output terminal 30 and output to a video amplification stage (not shown).

The AFT signal detector 11 connected to the output terminal of the IF amplifier 9 is not described in the circuit form, but the frequency of the IF signal input to the IF circuit 8 is higher than the normal frequency. A signal (AFT signal) for determining whether the frequency is such a frequency, that is, the frequency is higher or lower than the normal frequency is output. Therefore, in the receiver, by detecting this AFT signal by the AFT signal detection circuit 22, it is possible to recognize the current status of the received signal frequency.
This AFT signal is supplied to the microprocessor 21.

On the other hand, the VCO 3 of the tuner 6 has P
The prescaler 12 that constitutes the LL circuit is connected. That is, this is connected to the PLL circuit 20 in order to determine the oscillation frequency of the VCO 3, and the operation is VC
After detecting the O3 signal and dividing by the prescaler 12,
Signal divided by variable frequency divider 13 and fixed oscillator 1 with high precision
The signal from 4 is phase-compared by the phase comparator 16, and the control voltage 17 of the VCO 3 is obtained using the loop filter 18 according to the phase comparison result.
7 operates so as to change the oscillation frequency of the VCO 3.

The data latch 19 is for taking in the frequency division ratio of the variable frequency divider 13 from the microprocessor 21.

As described above, the prescaler 12, the variable frequency divider 13, the fixed oscillator 14, the fixed frequency divider 15, the phase comparator 16, the control voltage 17, the loop filter 18, and the data latch 19 form one circuit. PLL as a block
It constitutes the circuit 20, and the oscillation frequency of the VCO 3 is controlled by using the PLL circuit 20.

Here, for example, when the frequency division ratio of the prescaler 12 is 1/8, the frequency division ratio of the variable frequency divider 13 is N, and the comparison frequency of the phase comparator 16 is 7.8125 Khz, the PLL circuit 20. The oscillating frequency (fVCO) of the VCO 3 when is locked can be expressed as fVCO = N × 7.8125 × 8 = N × 62.5 (Khz) (2).

By the way, in the circuit configured as described above,
The operation of receiving the desired channel will be described below.

First, when the microprocessor 21 receives one of a plurality of broadcasting channels in Japan as a desired channel, the reception frequency (fRF) of this one channel is 91.25.
Since the intermediate frequency (fIF) is 58.75 Mhz when tuning to this reception frequency (fRF), fVCO = fIF + fRF = 150 (Mhz) is obtained from the equation (1).

Therefore, according to the equation (2), N = 150,000, 62.5 = 2400 (3), that is, this data is stored in the microprocessor 21.
If an operation is performed by using and to supply and set to the data latch 19, as a result, the oscillation frequency of the VCO 3 can be changed, that is, it can be tuned to the reception frequency (fRF) of one channel.

Therefore, in the channel selection device having such a circuit configuration, the broadcast signal is not, for example, the regular fRF frequency,
If it is offset arbitrarily, the broadcast frequency fSIG of this arbitrarily offset signal is set to 91.5M.
hz, and when tuning the broadcasting frequency of 91.5 Mhz of the fSIG from the broadcasting frequency of 91.25 Mhz of one channel currently tuned as described above, based on the data (N = 2400) of the formula (3). Reception, and guides the output of the AFT signal detector 11 to the microprocessor 21 via the detection circuit 22 to detect the current reception frequency,
In other words, it is detected whether the frequency is high or low by comparing with the frequency defined by the frequency number of one channel (91.25 Mhz), and naturally the frequency lower than that of fSIG is received. Is increased and reception is performed again, and thereafter, the frequency is exactly repeated, that is, the broadcast frequency f.
Operates to receive SIG.

Further, when the broadcast signal receives, for example, a broadcast frequency of 2 channels from a broadcast frequency of 1 channel, the broadcast signal of 2 channels is not a predetermined constant frequency (set to f0) but is arbitrarily set. In the case of being offset, the broadcast frequency of this arbitrarily offset signal is fSIG, and both signal frequencies are, for example, f0 = 97.25Mhz, fSIG = 97.25Mh.
If z, the receiver cannot recognize the signal frequency of channel 2 = fSIG. Therefore, first, the frequency division ratio is calculated and set in the data latch 19 to receive the specified frequency of channel 2 = f0. . When the lock frequency of the PLL circuit 20 changes and the tuner 6 is tuned to the specified frequency f0, the AFT signal detector 11 recognizes that the tuner frequency is tuned to a frequency lower than the signal frequency in this state. The signal is output. This signal is detected by the microprocessor 21, the frequency division ratio is gradually increased at arbitrary time intervals, and the lock frequency of the PLL circuit 20 is changed. Then, the tuner 6 outputs the broadcast signal from the output of the AFT signal detector 11. A signal notifying that tuning is being performed in a normal state is output to the microprocessor 21. Based on this signal, the microprocessor 21 detects and stops changing the division ratio, that is, the offset broadcast frequency (fSIG) is normally received. To work as you can.

However, in such a conventional channel selecting apparatus, for example, the specified frequency f0 is changed to the broadcast frequency of the two channels from the broadcast frequency of the one channel, and the broadcast frequency fSIG desired to be received is higher than the broadcast frequency of the f0. When the distances are far apart from each other, for example, as shown in FIG. 2, it takes time to receive the specified frequency f0 of the second channel from the state where the broadcast frequency number of the first channel is received, that is, the time between t0 and t1. However, in order to receive the desired fSIG frequency from the frequency f0 of these two channels, there are many calibration times, and as a result, a long time between t1 and t3 is required as shown in the figure. With regard to the channel selection device using such a system, such a problem is currently solved. Do proposal has not been made.

[0023]

As described above, in the conventional channel selecting device, when the broadcast signal frequency to be received has a large offset amount with respect to the regular specified frequency,
As compared with the variable frequency divider that adjusts the oscillation frequency of the VCO, the frequency of correcting the frequency division ratio of the variable frequency divider increases.
There is a problem that a long tuning period is required to obtain normal tuning.

Therefore, the present invention has been made in view of the above problems, and frequency correction can be performed in a minimum time even when the broadcast signal frequency to be received has a large amount of offset with respect to the regular specified frequency. An object of the present invention is to provide a tuning device capable of obtaining regular tuning.

[0025]

According to a first aspect of the present invention, there is provided a channel selecting device for receiving a broadcast signal, which is a companion signal to a broadcast signal and a signal of an oscillation circuit having a predetermined frequency difference. To obtain a beat component by mixing, a heterodyne receiver for outputting as a heterodyne signal, a demodulation circuit means for demodulating an output signal from the heterodyne receiver, and outputting as a baseband signal, and an output terminal of the heterodyne receiver. Connected to the measuring circuit means for measuring the frequency of the heterodyne signal and outputting it as frequency measurement data, and to the oscillation circuit of the heterodyne receiver, and detecting the frequency difference between the oscillation signal of this oscillation circuit and the broadcast signal. At the same time, the control voltage is generated and supplied based on the detection result to change the oscillation frequency of the oscillation circuit. An L circuit and a microprocessor for inputting the frequency measurement data whose frequency is measured by the measuring circuit means and controlling the PLL circuit to change the oscillation frequency of the oscillation circuit based on the frequency measurement data. Characterize.

According to a second aspect of the present invention, there is provided a channel selection device,
A heterodyne receiver that mixes a signal opposite to the signal of the first oscillating circuit having a predetermined frequency difference to receive the broadcast signal to obtain a beat component, and outputs the beat component as a heterodyne signal, The demodulation circuit means for demodulating the output signal from the heterodyne receiver and outputting it as a baseband signal is connected to the oscillation circuit of the heterodyne receiver and detects the frequency difference between the oscillation signal of this oscillation circuit and the broadcast signal. At the same time, a first PLL circuit for arbitrarily changing the oscillation frequency of the oscillation circuit so as to generate and supply a control voltage based on the detection result, and a second PLL circuit connected to the output terminal of the heterodyne receiver And a frequency of the heterodyne signal from the output terminal of the heterodyne receiver and a second oscillator circuit. A second PLL circuit that outputs by changing the oscillation frequency of the second oscillation circuit so that the frequency becomes a signal frequency of the same phase, and the second PLL circuit is connected to the second PLL circuit and Measuring circuit means for measuring the frequency of the output signal of the PLL circuit, and frequency measurement data measured by the measuring circuit means as input,
A microprocessor for controlling the first PLL circuit to change the oscillation frequency of the oscillation circuit based on the frequency measurement data is provided.

According to a third aspect of the present invention, there is provided a channel selection device,
3. The channel selection device according to claim 2, wherein the second PLL circuit is connected to demodulation circuit means for demodulating an IF signal as an output signal of the heterodyne receiver.

[0028]

In the present invention, the frequency of the signal can be clearly measured by using the measuring circuit means from the frequency of the signal tuned by the heterodyne receiver. Further, in the case of receiving a broadcast signal which is arbitrarily offset, the frequency of the broadcast signal is measured using the measuring circuit means, and the microprocessor and the PLL circuit are used based on the measured frequency measurement data. , The arbitrarily offset frequency can be compared with a specified frequency or the frequency of the previously tuned signal to obtain a frequency difference, and the oscillation circuit of the heterodyne receiver can be adapted to the frequency difference. Since the oscillating frequency can be controlled, it is possible to make a correction at once to tune to a signal of an arbitrary frequency.

[0029]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the channel selection device according to the present invention, and the same reference numerals are given to the constituent requirements of the same elements as in FIG.

As shown in FIG. 1, the television receiver signal received by the antenna 1 for receiving the television signal is supplied to the RF amplifier 2 and this RF amplifier 2 is supplied.
After being amplified by, it is output to the mixer 4. Here, the mixer 4 mixes the number of oscillation frequencies supplied from a separately provided oscillator (VCO) 3 capable of varying the oscillation frequency with the frequency of the supplied television signal to restore the original two. A beat signal having a beat frequency equal to the difference between the two frequencies is generated, supplied to the IF amplifier 5, amplified by the IF amplifier 5, and output to the IF circuit 8.

That is, the received television signal is
After being amplified by the RF amplifier 2, the signal from the VCO 3 and the mixer 4 are heterodyned and output.
The RF amplifier 2, the VCO 3, the mixer 4, and the IF amplifier 5 together form a so-called superheterodyne tuner 6
Are configured.

The role of the tuner 6 is to select a specific signal from a large number of radio waves output from the antenna 1,
The oscillation frequency of the VCO 3 is controlled so as to output it as the IF signal 7, and the beat signal obtained by the mixer 4 is adjusted.

The output of the tuner 6 is guided to an IF circuit 8 connected to the tuner 6 for signal processing, amplified by an IF amplifier 9 constituting the IF circuit 8, and then, a video signal detector 10 is outputted. Is demodulated as a baseband video signal by the output terminal 30 and output to a video amplification stage (not shown).

Therefore, in the present embodiment, the frequency counter 23 is connected to the output end of the tuner 6, and the frequency counter 23 and the microprocessor 21 are used based on the signal frequency of the output signal of the tuner 6, so that the conventional technique is used. It is characterized in that the frequency division ratio of the variable frequency divider is set similarly to the above.

The frequency counter 23 measures the output signal of the tuner 6, that is, the signal frequency of the IF signal as described above, and outputs the measurement result as signal data. The frequency counter 23 inputs the input signal. By measuring the signal frequency of the (IF signal), the current status of the received signal frequency can be recognized, and this measurement signal data is supplied to the microprocessor 21.

On the other hand, the VCO 3 of the tuner 6 has a prescaler 12 which constitutes a PLL circuit as in the prior art.
Are connected. That is, this is connected to the PLL circuit 20 in order to determine the oscillation frequency of the VCO 3, and the operation is to detect the signal of the VCO 3 and divide it by the prescaler 12 and then divide it by the variable frequency divider 13. And the signal from the high-precision fixed oscillator 14 are phase-compared by the phase comparator 16, and the control voltage 17 of the VCO 3 is obtained using the loop filter 18 based on the phase comparison result.
The control voltage 17 operates so as to change the oscillation frequency of the VCO 3.

The data latch 19 is for taking in the frequency division ratio of the variable frequency divider 13 from the microprocessor 21.

As described above, the prescaler 12, the variable frequency divider 13, the fixed oscillator 14, the fixed frequency divider 15, the phase comparator 16, the control voltage 17, the loop filter 18, and the data latch 19 form one circuit. PLL as a block
It constitutes the circuit 20, and the oscillation frequency of the VCO 3 is controlled by using the PLL circuit 20.

Next, the operation of the channel selection apparatus in this embodiment will be described in detail with reference to FIG.

From the state where the signal frequency of channel 1 is tuned, for example, the offset arbitrary broadcast frequency fSIG is set to 91.5 Mhz, and this broadcast frequency fSI is set.
The case of synchronizing with G will be described.

First, by using the microprocessor 21, the broadcast signal frequency of 1 channel, 91.25 Mhz.
Tune in to. In this case, the oscillation frequency of VCO3 is 15
In order to oscillate a frequency of 0 Mhz, the data launch 19 is set by the control of the microprocessor 21 so that the frequency division ratio N of the variable frequency divider 13 becomes 2400. As a result, the signal frequency of 1 channel, 91.25 Mhz
Can be tuned about.

Therefore, when tuning to the broadcast signal frequency fSIG, 91.5 Mhz, which is arbitrarily offset from the state of receiving the signal frequency of this 1 channel, the broadcast signal frequency of 1 channel is currently tuned. Therefore, the VCO 3 oscillates at an oscillation frequency of 150 Mhz. Here, the broadcast signal frequency fSIG being transmitted
Is 91.5 Mhz, the frequency of the output signal (IF signal) of the tuner 6 is fIF = 150−91,5 = 58.5 Mhz.

Therefore, the intermediate frequency (fI
When compared with F), there is a frequency difference of ΔfIF = 58.75−58.5 = 0.25 Mhz (3) from the frequency at which the broadcast signal of channel 1 is currently received.

Therefore, the difference for this frequency is set to VCO3.
By shifting with respect to, it becomes possible to satisfactorily and appropriately receive the signal of the offset broadcast signal frequency fSIG that is currently transmitted.

That is, the reception frequency of one channel is 9
At 1.25 Mhz, the oscillation frequency fVCO of the VCO 3 is 150 Mhz, so the frequency division ratio N of the variable frequency divider is 24.
In this state, the frequency division ratio N corresponding to the frequency difference (0.25 Mhz) from the broadcast signal frequency fSIG calculated by the equation (3), that is, ΔN = 4 is set. The variable frequency divider 13 may be controlled so as to calculate and correct the ΔN, that is, the frequency division ratio data of ΔN as described above may be set in the data launch 19 using the microprocessor 21.

As a result, for example, as shown in FIG. 2, the broadcast signal frequency of the channel 2 is received from the reception state of the broadcast signal frequency of the channel 1 and then the broadcast signal frequency fSIG which is arbitrarily offset is received and tuned. The time required to do so can be significantly reduced compared to the prior art. That is, according to the present embodiment, the specified frequency f0
(See FIG. 6) It is possible to omit the tuning time from the tuning time t1 of the two channels to the tuning time t3 of the broadcast signal frequency fSIG, and it is possible to obtain good offset tuning of the broadcast signal frequency. At the same time, it is clear that the performance of the tuning device can be improved.

FIG. 3 is a block diagram showing a second embodiment of the channel selection apparatus according to the present invention. The same components as those of the apparatus shown in FIG. 1 are designated by the same reference numerals and their description is omitted. , Only different parts will be described.

As shown in FIG. 3, in this embodiment, for example, a frequency counter 23 for measuring the signal frequency of the output signal of the tuner 6 is provided as in the above-mentioned embodiment, and the signal counter is used for count measurement of the signal frequency. In order to perform the operation favorably, the IF-PLL circuit 27 for pulling in the output signal of the tuner 6 is provided between the frequency count 23 and the tuner 6.

Here, in the above-described embodiment, as shown in FIG. 1, the frequency of the output signal of the tuner 6 is directly measured by using the frequency counter 23. However, in the case where the broadcast signal is, for example, overmodulated. May affect the frequency counting operation of the frequency counter 23.

Therefore, in the present embodiment, in order to solve such a problem, the signal frequency of the output signal of the tuner 6 is changed to
An IF-VCO 24 that operates by pulling in the output signal of the tuner 6 instead of directly measuring using the frequency counter 23
Is provided so that the output of the oscillation frequency circuit of the IFVCO 24 is connected to the frequency counter 23 and the frequency is reliably measured.

As shown in FIG. 3, the IF-PLL circuit 2
7 is the frequency of the output signal of the tuner 6 and the IFVCO 24
The IF comparator 25 that compares the phase difference with the oscillating frequency, the voltage generation circuit 26 that generates and outputs the oscillation frequency control voltage based on the phase comparison result by the IF comparator 25, and the voltage generation circuit The IF-VCO 24 is capable of oscillating a frequency corresponding to the oscillation frequency control voltage supplied from the control unit 26 and varying the oscillating frequency.

The frequency counter 23 uses the IF-P.
The frequency of the output signal of the LL circuit 27 is counted, and this frequency count data is supplied to the microprocessor 21 as in the above-described embodiment.

Next, the operation of this embodiment will be described in detail with reference to FIG. The operation of the tuner, the IF circuit, and the PLL circuit in this embodiment operates in the same manner as in the above-mentioned embodiment, and the description thereof will be omitted and the operation of the IF-PLL circuit as a main part will be described.

For example, when the signal frequency of the output signal of the tuner 6 shown in FIG. 3 is a normal frequency,
The IF phase comparator 25 using the output signal of the tuner 6 as an input signal performs a phase comparison between the frequency of the input signal from the tuner 6 and the signal frequency oscillated by the IFVCO 24 which oscillates a specified frequency in advance. , That is,
Because of the same phase, the voltage generator 26 supplies a constant oscillation frequency control voltage to the IFVCO 24 based on the phase comparison result of the IF phase comparator 25.

As a result, the IFVCO 24 oscillates a frequency corresponding to the constant oscillation frequency control voltage,
That is, it oscillates at a normal frequency. Then, the IFVC0
The signal oscillated at a regular frequency by 24 is frequency-counted (measured) by the frequency counter 23, that is, the frequency measurement data of the signal whose frequency is reliably measured can be supplied to the microprocessor 21.

When the output signal of the tuner 6 has an arbitrary frequency, for example, the IF phase comparator 24 determines the frequency of the input signal of the tuner 6 and the frequency of the signal oscillated from the IFVCO 24. And the frequency of the output signal of the tuner 6 are compared with the frequency of the output signal of the IFVCO 24 in this case. Are compared, and the oscillation frequency control voltage from the voltage generation circuit 26 changes according to the result of the phase comparison, that is, the IF-VCO 24
The oscillation frequency of the signal is output so that it has the same phase as the output frequency of the tuner 6.

As a result, even if the frequency of the output signal of the tuner 6 is an arbitrary frequency, the frequency of the output signal of the tuner 6 can be ensured with the frequency counter 23.
It is possible to supply the frequency count data of the broadcast signal to the microprocessor 21 in the same manner as described above.

Therefore, according to the present embodiment, even when the frequency of the output signal of the tuner 6 is the specified frequency or an arbitrary frequency, by using the IF-PLL circuit 27 and the frequency counter 23, the tuner 6 can be used.
It is possible to reliably measure the frequency according to the frequency of the output signal, and it is possible to perform the stable frequency measurement even when a minute input signal, that is, a weak electric field input or a signal having a high degree of modulation is received.

Further, it is possible to supply the frequency count data whose frequency is measured very reliably to the microprocessor 21. As a result, by using the microprocessor 21 based on this frequency count data, the frequency division ratio of the variable frequency divider 13, that is, the correction data for ΔN can be supplied to the data launch 19 as in the first embodiment. The frequency division ratio of the variable frequency divider 13 is changed, and as a result, the VCO 3 of the tuner 6 can oscillate the oscillation frequency based on the frequency count data, so that good broadcast signal tuning can be obtained.

FIG. 4 is a block diagram showing a third embodiment of the channel selection device according to the present invention. The same components as those of the device shown in FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. Only explained.

As shown in FIG. 4, in the present embodiment, for example, the IF-PLL circuit 27 (see FIG. 3) used in the second embodiment is used as a reference IF signal for the synchronous demodulation of the IF signal. Is provided in the oscillation circuit 8 (see FIG. 3) that generates the signal, that is, it is also used.

This is because the output signal of the tuner 6 is not directly measured as the input signal from the output signal of the tuner 6 which is the feature of the first and second embodiments, and the output signal of the tuner 6 is fed to the IF circuit and the I circuit.
The signal is supplied to the circuit section 80 composed of an F-PLL circuit to perform frequency measurement, that is, the output signal of the tuner 6 is supplied to the IF amplifier 9, and the IF amplifier 9
The signal amplified at a predetermined level in
It can be supplied to the phase comparator 25, and an accurate signal frequency can be obtained by using the voltage generator 26 and the IFVCO 24 as in the above embodiment, that is, an accurate frequency measurement data can be obtained by using the frequency counter 23. Further, it goes without saying that the operation thereafter is the same as that of the above-described embodiment and the same effect can be obtained.

[0063]

As described above, according to the present invention, even when receiving a broadcast signal which is not transmitted at the regular frequency, the time until tuning is not increased and the regular signal is surely obtained. It becomes possible to tune, which makes it possible to satisfactorily tune to a wide range of broadcast channels, as well as to improve tuning or tuning.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of a channel selection device according to the present invention.

FIG. 2 is an explanatory diagram explaining an operation of the apparatus shown in FIG.

FIG. 3 is a block diagram showing a second embodiment of the channel selection device according to the present invention.

FIG. 4 is a block diagram showing a third embodiment of the channel selection device according to the present invention.

FIG. 5 is a block diagram showing a conventional channel selecting device.

FIG. 6 is an explanatory diagram explaining an operation of the channel selection device shown in FIG.

[Explanation of symbols]

 1 ... Antenna 2 ... RF amplifier 3 ... VCO (oscillation frequency) 4 ... Frequency mixer 5 ... IF amplifier 6 ... Tuner 7 ... Tuner output signal 8 ... IF circuit 9 ... IF amplifier 10 ... Video signal detector 11 ... AFT signal generation Device 12 ... Prescaler 13 ... Variable frequency divider 14 ... Fixed oscillator 15 ... Fixed frequency divider 16 ... Phase comparator 17 ... VCO control voltage 18 ... Loop filter 19 ... Data clutch 20 ... PLL circuit 21 ... Microprocessor 22 ... AFT signal Detection circuit 23 ... Frequency counter 24 ... IF-VCO 25 ... IF phase comparator 26 ... IF-VCP filter

Claims (3)

[Claims] 1. A heterodyne receiver for mixing a broadcast signal and a signal of an oscillation circuit having a predetermined frequency difference for receiving a broadcast signal to obtain a beat component and outputting the beat component as a heterodyne signal. A demodulation circuit means for demodulating the output signal from the heterodyne receiver and outputting it as a baseband signal, and being connected to the output terminal of the heterodyne receiver, measuring the frequency of the heterodyne signal as frequency measurement data. The measuring circuit means for outputting and the oscillation circuit of the heterodyne receiver are connected to detect the frequency difference between the oscillation signal of the oscillation circuit and the broadcast signal and generate and supply the control voltage based on the detection result. A PLL circuit for changing the oscillation frequency of the oscillation circuit, and the frequency is measured by the measuring circuit means. A channel selection device comprising: a microprocessor that receives frequency measurement data and controls the PLL circuit to change the oscillation frequency of the oscillation circuit based on the frequency measurement data. 2. A broadcast signal for receiving the broadcast signal is mixed with a signal opposite to the signal of the first oscillating circuit having a predetermined frequency difference to obtain a beat component and output as a heterodyne signal. Heterodyne receiver, demodulating the output signal from the heterodyne receiver, demodulation circuit means for outputting as a baseband signal, connected to the oscillation circuit of the heterodyne receiver, the oscillation signal of the oscillation circuit and the broadcast signal Connected to a first PLL circuit that detects a frequency difference and generates and supplies a control voltage based on the detection result to arbitrarily change the oscillation frequency of the oscillation circuit; and an output terminal of the heterodyne receiver And a second oscillating circuit is provided to configure the frequency of the heterodyne signal from the output terminal of the heterodyne receiver and the second oscillator. A second PLL circuit that outputs by changing the oscillation frequency of the second oscillation circuit so that the oscillation frequency of the circuit becomes a signal frequency of the same phase; and, while being connected to the second PLL circuit, Second
Measuring circuit means for measuring the frequency of the output signal of the PLL circuit, and frequency measurement data whose frequency is measured by the measuring circuit means as an input, and based on this frequency measurement data, the oscillation frequency of the oscillating circuit is changed. 1 PLL
A channel selection device comprising: a microprocessor that controls a circuit. 3. The channel selection apparatus according to claim 2, wherein the second PLL circuit is connected to demodulation circuit means for demodulating an IF signal as an output signal of the heterodyne receiver.