JPH07162288A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit capable of holding high speed operation even when internal power supply voltage is reduced independently of the 'H' and 'L' values of a node in an LSI and suppressing a stand-by current to a low level. CONSTITUTION:The semiconductor integrated circuit constitutes a logic circuit by arranging three stages consisting of three pairs of 1st and 2nd CMOS circuits 1, 2 each of which is constituted of connecting a pMOS transistor(TR) Qp and an nMOS TR Qn in series and using their connection node as an output point. The same input is applied to the CMOS circuits 1, 2 on the 1st stage, the output of the CMOS circuit 1 on the 1st stage is inputted to the gates of the pMOSTRs Qp21, Qp23 of the circuits 1, 2 on the 2nd stage and the output of the CMOS circuit 2 on the 2nd stage is inputted to the gates of respective nMOSTRs Qn21, Qn23 on the circuits 1, 2 on the 2nd stage. The 2nd stage and the 3rd stage are similarly connected.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit using a CMOS circuit.

[0002]

2. Description of the Related Art In recent years, in order to achieve high integration of various general-purpose LSIs and battery drive, reduction in power consumption and reduction in voltage of the power supply Vcc have been promoted. Internal power supply Vcc for each generation
Is on the decline. Specifically, in a 1 G and 4 G bit DRAM, Vcc drops to 1.5 to 1.0V. Also, in a battery-driven (battery-driven) LSI, Vcc is required to operate at 1.5V to 0.8V.

However, in the LSI, the threshold voltage Vt of the MOS transistor exists, and Vth is in the vicinity of Vt.
There is a problem that the operating speed (gate delay time) decreases sharply as cc approaches. If the threshold voltage Vt is reduced in order to prevent this, a problem that the standby current sharply increases occurs.

As a conventional example, FIG. 12 shows a part of the circuit in the memory. This is an example of a three-stage inverter,
(A) shows an equivalent circuit and (b) shows a concrete circuit configuration. During standby, the nodes N1 and N3 are at "L" level and the nodes N2 and N4 are at "H" level.
At this time, looking at the front two inverters, a leak current Ileak flows through the transistors Q1 and Q4. Similarly, this condition exists in the entire memory, and if the threshold value of the transistor is lowered, the leak current increases significantly.

On the other hand, the present inventors set the threshold value of the transistor in the OFF state, in which leakage occurs during standby, higher than that in the ON state, or set the power supply potential of the transistor in the OFF state to Vcc. By lowering Vss and raising Vss, we proposed a method to reduce the leak current during standby and operate at high speed during active (Japanese Patent Application No. 5-
No. 3011). This is because most of the internal circuit node potentials of the memory LSI during standby are “H”, “L”,
It is determined to be "1/2 Vcc" or the like, and the fact that the ON / OFF state of the transistor during standby is determined is used.

However, even in this method, it is difficult to apply to a general-purpose LSI other than the memory in which the values of the internal nodes, that is, "H" and "L" are not determined at the time of standby.

[0007]

As described above, in the conventional semiconductor integrated circuit, when the internal power supply Vcc of the LSI is lowered, Vcc approaches the threshold value Vt of the transistor and the operation speed becomes slow. Yes, threshold Vt
There was a problem that the standby current increased when the value was lowered.

The present invention has been made in consideration of the above circumstances, and its purpose is to reduce the internal power supply voltage regardless of the "H" and "L" values of the nodes inside the LSI. Even in such a case, it is an object of the present invention to provide a semiconductor integrated circuit capable of maintaining a high-speed operation and suppressing a standby current to be low.

[0009]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention (Claim 1) provides a first and a second CMOS circuit that outputs one or more combinations of one or more pMOS transistors and one or more combinations of nMOS transistors in series and outputs the connection node. A first CMO of the i-th stage (i <n), which is a semiconductor integrated circuit in which a logic circuit is formed by arranging the CMOS circuit sets in n stages (n ≧ 2).
The output of the S circuit is input to the gates of the pMOS transistors of the first and second CMOS circuits of the next stage, and the output of the second CMOS circuit of the i-th stage is the first and second CMs of the next stage.
It is characterized in that it is inputted to the gate of each nMOS transistor of the OS circuit.

According to the present invention (claim 2), one or more combinations of pMOS transistors and one or more combinations of nMOS transistors are connected in series, and the connection node is used as an output, and one or more pMOS transistors are connected. A first CMOS circuit in which one end of the combination is set to the first Vcc and one end of one or more combinations of nMOS transistors is set to the first Vss, and an equivalent circuit similar to the first CMOS circuit is provided. A second Vcc at one end of one or more combinations of the two and a second Vss at one end of the one or more combinations of nMOS transistors;
A first CMOS circuit of the i-th stage (i <n), which is a semiconductor integrated circuit in which a logic circuit is formed by arranging the CMOS circuit of FIG. Is output from each pMOS of the first and second CMOS circuits of the next stage.
It is input to the gate of the transistor and the second C of the i-th stage
The output of the MOS circuit is input to the gates of the nMOS transistors of the first and second CMOS circuits of the next stage, and the potential of the first Vss is raised above the potential of the second Vss during standby, The potential of Vcc is lower than the potential of the first Vcc.

According to the present invention (claim 3), one or more combinations of pMOS transistors and one or more combinations of nMOS transistors are connected in series, and the connection node is used as an output, and one or more pMOS transistors are connected. A first CMOS circuit in which one end of the combination is set to the first Vcc and one end of one or more combinations of nMOS transistors is set to the first Vss, and an equivalent circuit similar to the first CMOS circuit is provided. A second Vcc at one end of one or more combinations of the two and a second Vss at one end of the one or more combinations of nMOS transistors;
A first CMOS circuit of the i-th stage (i <n), which is a semiconductor integrated circuit in which a logic circuit is formed by arranging the CMOS circuit of FIG. Is output from each pMOS of the first and second CMOS circuits of the next stage.
It is input to the gate of the transistor and the second C of the i-th stage
The output of the MOS circuit is input to the gates of the nMOS transistors of the first and second CMOS circuits of the next stage, and the first Vss and the second Vcc are connected.

The following are preferred embodiments of the present invention. (1) The second CMOS circuit operates faster than the first CMOS circuit when the output rises, and the first CMOS circuit operates when the output falls.
The CMOS circuit of 1. operates faster than the second CMOS circuit. (2) In the first stage of the set of the first and second CMOS circuits, the gate input of each transistor in the first CMOS circuit and the gate input of each transistor in the second CMOS circuit are common. . (3) A third CMOS circuit in which a pMOS transistor and an nMOS transistor are connected in series is provided next to the nth stage of the set of the first and second CMOS circuits, and the first CMOS circuit of the nth stage is provided. Is the pM of the third CMOS circuit
It is input to the gate of the OS transistor and the second of the nth stage
The output of the CMOS circuit is the nMOS of the third CMOS circuit.
Must be input to the gate of a transistor. (4) The equivalent drive capability of the pMOS transistor in the first CMOS circuit is lower than the equivalent drive capability of the nMOS transistor, and the equivalent drive capability of the pMOS transistor in the second CMOS circuit is higher than the equivalent drive capability of the nMOS transistor. (5) The channel width of all transistors of the first CMOS circuit is larger than the channel width of all transistors of the second CMOS circuit. (6) Include a circuit in which the first and second CMOS circuits are combined in three or more stages. (7) As each transistor forming the CMOS circuit, S
Use a transistor of OI (silicon on insulator) structure. (8) The pMOS of the second CMOS circuit according to claim 2.
The threshold voltage of the transistor is p of the first CMOS circuit.
Lower than that of the MOS transistor (small negative value), and lower than the threshold voltage of the nMOS transistor of the first CMOS circuit (small positive value) of the nMOS transistor of the second CMOS circuit. . (9) In claim 2, the first Vss is connected to the second Vss via the transistor, and the second Vcc is connected to the first Vcc via the transistor.

[0013]

According to the present invention (claims 1 to 3), since the input signal of the pMOS transistor and the input signal of the nMOS transistor are separated, when the input changes from "L" to "H" level, the nMOS transistor OFF to ON
Therefore, the depletion layer under the gate channel expands from the OFF state until the gate potential rises to about the threshold voltage, and the gate capacitance is small until the inversion region is reached. On the other hand, the pMOS transistor has a large gate capacitance until the input signal starts rising, that is, while the gate is inverted, until the pMOS transistor changes from ON to OFF.

As a result, the nMOS transistor input rises faster than the pMOS transistor input signal. Therefore, when the voltage is low, Vcc is close to the threshold voltage, and the dependency of the threshold voltage is large with respect to the speed. When the voltage is low, the nMOS transistor operates before the pMOS transistor operation. The wasted time up to (threshold voltage) can be reduced, and as a result, the speed is improved.

Further, until the input reaches from Vcc-Vt to Vcc, the nMOS transistor has an inverting function and the gate capacitance is large, and the pMOS transistor is in a depletion state, and p
The MOS transistor rises faster, works to suppress the common current, and each gate voltage is Vcc.
Will be reached almost at the same time.

On the contrary, when the input goes from "H" to "L" level, the pMOS capacitance is small from Vcc to Vcc-Vt.
Since the nMOS capacity is large, the nMOS capacity is small from Vt to Vss, and the pMOS capacity is large, the input of the pMOS transistor starts earlier and the nMOS capacity becomes larger when the input decreases.
The speed is lower than the input of the transistor and decreases as it approaches Vss.

Therefore, the time when the pMOS starts to turn on from OFF is reduced, and as a result, the speed is improved. Further, the equivalent drive capability of the pMOS transistor in the first CMOS circuit is lower than the equivalent drive capability of the nMOS transistor, and the equivalent drive capability of the pMOS transistor in the second CMOS circuit is set higher than the equivalent drive capability of the nMOS transistor. As a result, the speed on the side of turning on from OFF to ON is more than OFF
It is faster than the nMOS or pMOS on the working side, and the speed is further improved. Further, the larger the difference in capacitance between depletion and inversion is, the more effective it is. Therefore, it is effective to use a transistor having an SOI structure.

When the Vss of the CMOS circuit driving the pMOS transistor and the Vcc of the CMOS circuit driving the nMOS transistor are raised (lowered) during standby as in claim 2, the pMOS driving side is increased. Of the nMOS transistor in the CMOS circuit and the pMOS transistor in the CMOS circuit on the nMOS driving side, the transistor that is turned off has a gate-source voltage difference that advances in the direction in which the transistor turns off. this is,
It does not depend on the value of any node in the circuit. Therefore, by raising (lowering) Vss (Vcc) during standby, it is possible to greatly reduce the leakage of these OFF transistors, which are the leakage sources.

Further, the threshold voltage of the nMOS transistor on the pMOS driving side and the pMOS transistor on the pMOS driving side are made lower than others to achieve higher speed, and Vss on the pMOS driving side is increased during standby to increase Vs on the nMOS driving side.
By lowering cc, both speedup and reduction of leakage during standby can be achieved.

Further, by utilizing the circuit divided into the pMOS side and the nMOS side to connect and operate Vss on the pMOS side and Vcc on the nMOS side, the external voltage cannot be lowered constantly for each generation, and the transistor When it is necessary to lower the internal power supply in order to improve reliability due to miniaturization, the pMO
By utilizing the fact that the CMOS circuits on the S and nMOS sides operate in the same manner, the internal voltage can be stepped down without wasting power.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit configuration diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. This is a 4-stage commercial
It is an example of configuring an OS inverter.

The conventional inverter is composed of one each of an nMOS transistor and a pMOS transistor, but in the present embodiment, one inverter is divided into two, for example, Qp11,
It is divided into a first inverter (first CMOS circuit) 1 composed of Qn11 and a second inverter (second CMOS circuit) 2 composed of Qp13 and Qn13. However, Qp11, Qn11, Q
The total dimensions of p13 and Qn13 can be made the same as before, and the total number of dimensions need not be increased. This division is the second stage (Qp21, Qn21, Qp23,
Qn23) and the third stage (Qp31, Qn31, Qp33, Qn33) are divided. However, the fourth stage has the same inverter configuration of Qp4 and Qn4 as the conventional one.

Next, the first stage Qp11, Qn11 and Qp13, Qn1
The output P1 of the first inverter 1 of 3 sets is input only to the pMOS side of the next set, and the output N1 of the second inverter 2 is input only to the nMOS side of the same set of the next stage. Then, this is repeated to form a logic circuit.

In this embodiment, each signal line is input in this way,
Both outputs are configured separately for the pMOS side and the nMOS side. However, the first stage of the first stage can be made one for one signal, and the fourth stage of the final stage is received by normal logic (however, although there are two types of inputs), it becomes one signal. On the other hand, it is possible to return to one signal line.

A logic circuit group is constructed by forming a set in this way, and two signals are used in the logic circuit group. The input and output of the group can be returned to one. The methods may be combined.

Although the number of elements is doubled as compared with the conventional one, the total channel width in the set can be made the same as the conventional one. Because
This is because, for example, connecting P1 and N1, P2 and N2, and P3 and N3 results in a conventional CMOS inverter, so that the conventional channel width is simply divided.

With respect to the effect in such a case, looking at, for example, the nodes P1 and N1, the signals of the input P1 of the pMOS and the input N1 of the nMOS are separated, so that the input is "L" to "H" level. NMO of the input when changing to
Since S changes from OFF to ON, the depletion layer under the gate channel expands from the OFF state until the gate potential rises to about the threshold voltage, and the gate capacitance is small until the inversion region is reached. FIG. 3 shows this state, and the capacitance is small from the gate-source voltage of 0 V to Vt. On the other hand, the gate capacitance of the pMOS is large until the input signal starts rising, that is, while the gate is inverted, until it changes from ON to OFF.

As a result, the nMOS input rises faster than the pMOS input signal. This is shown in FIG. 2A. Therefore, at low voltage, when Vcc is close to the threshold value and the threshold voltage dependency is large with respect to the speed, at the low voltage, the input of the nMOS starts to turn on 0V. To Vt
Since the wasteful time until (threshold voltage) is operated before the pMOS operation in this embodiment, the speed is improved as a result.

Further, until the input reaches from Vcc-Vt to Vcc (at B in FIG. 2), the nMOS is in the inverted state, the gate capacitance is large, the pMOS is in the depleted state, and the pMOS is depleted.
In this case, the rising speed becomes faster, the through current is suppressed, and the respective gate voltages reach Vcc almost at the same time.

On the contrary, when the input is lowered from "H" to "L" level, the pMOS capacitance is small, n from Vcc to Vcc-Vt.
Since the MOS capacitance becomes large, the nMOS capacitance becomes small from Vt to Vss, and the pMOS capacitance becomes large, so when the input falls, pM
The input of the OS is faster at the beginning and lower than the input of the nMOS, and the speed of the input is opposite when approaching Vss (C in FIG. 2). (D of FIG. 2) Therefore, the time when the pMOS starts to turn from OFF to ON is reduced, and as a result, the speed is improved. Therefore, if a plurality of stages of this embodiment are combined, the speed is increased for each stage, and the effect is expected as shown in FIG. 4 especially when the voltage is low.

Further, the present embodiment is more effective as the gate capacitance when the MOS is depleted is reduced. S as shown in FIG.
The OI (Silicon on Insulator) structure has a large ratio of the maximum capacity value Cmax / the minimum capacity value Cmin as shown in FIG. 5B. Therefore, by using the SOI structure, OF
The speed on the side from F to ON becomes faster than that on the side from OFF to ON, and the speed is further improved.

The principle of speeding up according to this embodiment is shown in FIG.
Will be described in more detail with reference to. In order to simplify the explanation, here, the power supply Vcc is set to 1.5V, the threshold Vt of the nMOS transistor is set to 1.0V, and the threshold Vt of the pMOS transistor is set to -1,0V.

In a normal inverter, when the gate input changes from "L" level to "H" level as shown in FIG. 6 (a), the gate input becomes 0 → (Vcc-Vt) → Vt →
It changes with Vcc. Then, at the time of (Vcc-Vt), pM
The OS transistor changes from ON to OFF, and the nMOS transistor changes from OFF to ON at the time of Vt. Therefore, the time from turning off the pMOS transistor to turning on the nMOS transistor becomes a dead time.

On the other hand, when the gate input is divided as in the present embodiment, as shown in FIG. 6B, the rising of the gate input of the nMOS transistor becomes faster from 0 to Vt and from Vt to Vcc. Will be late. On the other hand, pMOS
The rise of the gate input of the transistor is 0 → (Vcc
It becomes slower until -Vt) and becomes faster from (Vcc-Vt) to Vcc. Therefore, the dead time as shown in FIG. 6A is shortened, and if the gate input of the nMOS transistor reaches Vt and the gate input of the pMOS transistor reaches (Vcc-Vt) at the same time, You can also eliminate dead time.

The same is true when the gate input changes from "H" level to "L" level, whereby C
It is possible to speed up the operation of the MOS inverter.

FIG. 7 is a circuit configuration diagram showing a semiconductor integrated circuit according to the second embodiment of the present invention. Although an example of an inverter is shown in the first embodiment, this embodiment shows a case where the present invention is applied to other logic circuits NAND and NOR.

The same NAND gate and NOR gate as in the prior art are each divided into two, and two types of signals are used for pMOS input and nMOS input to form a logic. As described above, the present invention can be applied to all logics.

Specifically, one NAND gate is divided into two, and the first stage is composed of a first NAND gate (first CMOS circuit) 3 composed of Qp11, Qp12 and Qn11, Qn12, and Qp1.
It is divided into a second NAND gate (second CMOS circuit) 4 composed of 3, Qp14 and Qn13, Qn14. The second stage is a NOR gate, but similarly, a first NOR gate (first CMOS circuit) 5 composed of Qp21, Qp22 and Qn21, Qn22,
It is divided into a second NOR gate (second CMOS circuit) 6 composed of Qp23, Qp24 and Qn23, Qn24. The output of the first NAND gate of the first stage is input to the pMOS transistors Qp21 and Qp23 of the second stage, and the output of the second NAND gate is input to the nMOS transistors Qn21 and Qn23 of the second stage.

Even with such a structure, it is possible to obtain the effect that high-speed operation can be achieved as in the first embodiment. That is, it can be applied to various logics using a CMOS circuit composed of a pMOS transistor and an nMOS transistor.

FIG. 8 is a circuit configuration diagram showing a semiconductor integrated circuit according to the third embodiment of the present invention. This embodiment is different from the first embodiment in that firstly, the nM on the pMOS driving side is
The threshold voltage of the OS transistor (Qn11 in the first stage) is made lower than the threshold voltage of the nMOS transistor on the nMOS drive side (Qn13 in the first stage), and the pMOS transistor on the nMOS drive side (in the first stage is This is because the threshold voltage of Qp13) has been made lower than the threshold voltage of the pMOS transistor on the pMOS driving side (Qp11 in the first stage).

As a result, the present invention further speeds up as the threshold value is lowered. Of course, the one with the higher threshold value has the same depletion effect as in the first embodiment. Further, it is more preferable that the driving capability of the one having the lower threshold value and the higher speed is increased, and the speed from the OFF side to the ON side coincides with the direction in which the speed from the ON side to the OFF side is increased.

However, if Vt is simply lowered as described above,
For example, as shown in the drawing, the leakage currents L2, L of other transistors whose leakage potentials L1, L3, L5 are turned off.
Since Vt is lower than 4, L6 and L7, it becomes large.
On the other hand, the Vss side of the CMOS circuit on the pMOS driving side,
Transistor Q on the side of CMOS circuit Vcc on the nMOS drive side
Connect to Vss and Vcc via p5 and Qn5. In this way, it is turned on at the time of action, the leak current is loosened to operate at high speed, and the transistor Q is turned on at the time of standby.
P5 and Qn5 are turned off. In such a case, the potentials of the nodes Vss1 and Vcc1 in the drawing are Vss1 and Vss due to the leakage current.
It goes up from ss, and Vcc1 goes down with time after Vcc.

Therefore, for example, the leak transistor Qn31
Despite the rise of the source, that is, Vss1, Qn23 of the node N2 remains ON, so that the potential is connected to Vss and kept at Vss, so that the cutoff characteristic of the transistor is improved.

Looking at the transistor Qn21 which is turned on, the gate-source potential decreases from the potential of N1 to Vcc.
1-Vss, but the value of the node is held as long as the value is Vt <Vcc2-Vss.

This means that in this embodiment, the leakage current is greatly reduced regardless of the value of the node. That is,
It can be applied to general-purpose LSIs in general. In other words, the present embodiment can be applied to LSI in a wide range, not limited to the case where the value of the node is known in advance. Note that this operation is shown in FIG.

FIG. 10 is a circuit diagram showing a semiconductor integrated circuit according to the fourth embodiment of the present invention. This is the second
This is an example in which the present invention is applied to other logic such as NAND and NOR as in the embodiment. Make 4 kinds of power source (Vcc1,
Vcc2, Vss1, Vss2) and by operating in the same manner as in FIG. 8, both high speed and low leakage can be achieved.

FIG. 11 is a circuit configuration diagram showing a semiconductor integrated circuit according to the fifth embodiment of the present invention. In this embodiment, the circuit is divided into the pMOS side and the nMOS side, and Vss on the pMOS side and Vcc on the nMOS side are connected to operate.

With such a structure, pMOS, nM
Since the CMOS circuit on the OS side operates in the same manner, the internal voltage can be reduced without wasting power. This is effective when it is necessary to lower the internal power supply because the external voltage cannot be lowered for each generation and the reliability is improved by miniaturizing the transistor. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0049]

As described in detail above, according to the present invention, C
The MOS circuit is divided into two parts to form a pMOS and an nMOS.
By making the inputs independent, the high speed operation can be maintained and the standby current can be kept low regardless of the "H" and "L" values of the nodes inside the LSI even when the internal power supply is lowered in voltage. It is possible to realize a semiconductor integrated circuit that can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a schematic diagram for explaining the operation principle of the first embodiment.

FIG. 3 is a characteristic diagram showing the relationship between gate-source voltage and gate capacitance.

FIG. 4 is a characteristic diagram showing the relationship between Vcc and gate delay in the present invention and the conventional example.

FIG. 5 is a diagram showing changes in an SOI structure and a gate capacitance.

FIG. 6 is a diagram for explaining the principle of speeding up in the first embodiment.

FIG. 7 is a circuit configuration diagram showing a semiconductor integrated circuit according to a second embodiment.

FIG. 8 is a circuit configuration diagram showing a semiconductor integrated circuit according to a third embodiment.

FIG. 9 is a signal waveform diagram for explaining the operation of the third embodiment.

FIG. 10 is a circuit configuration diagram showing a semiconductor integrated circuit according to a fourth embodiment.

FIG. 12 is a circuit configuration diagram showing an example of a conventional three-stage inverter.

[Explanation of symbols]

1 ... 1st inverter (1st CMOS circuit) 2 ... 2nd inverter (2nd CMOS circuit) 3 ... 1st NAND gate (1st CMOS circuit) 4 ... 2nd NAND gate (2nd) CMOS circuit 5 ... First NOR gate (first CMOS circuit) 6 ... Second NOR gate (second CMOS circuit) Qp (Qp11, Qp14, ..., Qp33, Qp4, Qp5) ... pMOS
Transistors Qn (Qn11, Qn14, ~, Qn33, Qn4, Qn5) ... nMOS
Transistor

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[Procedure amendment]

[Submission date] June 2, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a schematic diagram for explaining the operation principle of the first embodiment.

FIG. 3 is a characteristic diagram showing the relationship between gate-source voltage and gate capacitance.

FIG. 4 is a characteristic diagram showing the relationship between Vcc and gate delay in the present invention and the conventional example.

FIG. 5 is a diagram showing changes in an SOI structure and a gate capacitance.

FIG. 6 is a diagram for explaining the principle of speeding up in the first embodiment.

FIG. 7 is a circuit configuration diagram showing a semiconductor integrated circuit according to a second embodiment.

FIG. 8 is a circuit configuration diagram showing a semiconductor integrated circuit according to a third embodiment.

FIG. 9 is a signal waveform diagram for explaining the operation of the third embodiment.

FIG. 10 is a circuit configuration diagram showing a semiconductor integrated circuit according to a fourth embodiment.

FIG. 11 is a circuit configuration diagram showing a semiconductor integrated circuit according to a fifth embodiment.

FIG. 12 is a circuit configuration diagram showing an example of a conventional three-stage inverter.

[Description of Reference Signs] 1 ... First inverter (first CMOS circuit) 2 ... Second inverter (second CMOS circuit) 3 ... First NAND gate (first CMOS circuit) 4 ... Second NAND gate (second CMOS circuit) 5 ... First NOR gate (first CMOS circuit) 6 ... Second NOR gate (second CMOS circuit) Qp (Qp11, Qp14, ..., Qp33, Qp4, Qp5) ) ... pMOS
Transistors Qn (Qn11, Qn14, ~, Qn33, Qn4, Qn5) ... nMOS
Transistor

Claims (7)

[Claims] 1. A CMOS circuit comprising a combination of at least one combination of pMOS transistors and at least one combination of nMOS transistors connected in series, and a pair of first and second CMOS circuits which output the connection node. In a semiconductor integrated circuit in which sets are arranged in n stages (n ≧ 2) to form a logic circuit, the output of the first CMOS circuit at the i-th stage (i <n) is the first and second stages of the next stage. Input to the gate of each pMOS transistor of the CMOS circuit, and the output of the second CMOS circuit of the i-th stage is the nMO of each of the first and second CMOS circuits of the next stage.
A semiconductor integrated circuit characterized by being input to the gate of an S-transistor. 2. One or more combinations of pMOS transistors and one or more combinations of nMOS transistors are connected in series, and this connection node is used as an output, and one end of one or more combinations of pMOS transistors is connected to a first Vcc.
And has a first CMOS circuit in which one end of one or more combinations of nMOS transistors is the first Vss and an equivalent circuit similar to the first CMOS circuit, and one end of one or more combinations of pMOS transistors is A second CMOS circuit in which one end of one or more combinations of nMOS transistors is set to the second Vss is set as a second Vcc
In a semiconductor integrated circuit in which a logic circuit is configured by arranging this CMOS circuit set in n stages (n ≧ 2), the output of the first CMOS circuit in the i-th stage (i <n) is the first in the next stage. And the gate of each pMOS transistor of the second CMOS circuit, and the output of the second CMOS circuit of the i-th stage is the nMO of each of the first and second CMOS circuits of the next stage.
It is input to the gate of the S-transistor, and during standby, the potential of the first Vss is raised above the potential of the second Vss and the potential of the second Vcc is lowered below the potential of the first Vcc. Semiconductor integrated circuit. 3. One or more combinations of pMOS transistors and one or more combinations of nMOS transistors are connected in series, and the connection node is used as an output, and one end of one or more combinations of pMOS transistors is connected to a first Vcc.
And has a first CMOS circuit in which one end of one or more combinations of nMOS transistors is the first Vss and an equivalent circuit similar to the first CMOS circuit, and one end of one or more combinations of pMOS transistors is A second CMOS circuit in which one end of one or more combinations of nMOS transistors is set to the second Vss is set as a second Vcc
In a semiconductor integrated circuit in which a logic circuit is configured by arranging this CMOS circuit set in n stages (n ≧ 2), the output of the first CMOS circuit in the i-th stage (i <n) is the first in the next stage. And the gate of each pMOS transistor of the second CMOS circuit, and the output of the second CMOS circuit of the i-th stage is the nMO of each of the first and second CMOS circuits of the next stage.
A semiconductor integrated circuit, characterized in that the first Vss and the second Vcc are input to the gate of an S-transistor. 4. In the first stage of the set of the first and second CMOS circuits, the gate input of each transistor in the first CMOS circuit and the gate input of each transistor in the second CMOS circuit are common. 4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided. 5. A third CMOS circuit in which a pMOS transistor and an nMOS transistor are connected in series is provided next to the nth stage of the set of the first and second CMOS circuits, and the nth stage is provided.
The output of the first CMOS circuit of the third stage is input to the gate of the pMOS transistor of the third CMOS circuit, and the output of the second CMOS circuit of the nth stage is n of the third CMOS circuit.
4. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is input to the gate of a MOS transistor. 6. The equivalent drive capability of the pMOS transistor in the first CMOS circuit is lower than the equivalent drive capability of the nMOS transistor, and the pMO in the second CMOS circuit is reduced.
3. The equivalent drive capability of the S transistor is higher than the equivalent drive capability of the nMOS transistor.
Or the semiconductor integrated circuit described in 3. 7. The threshold voltage of the pMOS transistor of the second CMOS circuit is lower (smaller negative value) than that of the pMOS transistor of the first CMOS circuit,
3. The semiconductor integrated circuit according to claim 2, wherein the threshold voltage of the nMOS transistor of the first CMOS circuit is lower (smaller plus value) than that of the nMOS transistor of the second CMOS circuit.