JP3227946B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit for converting an input voltage level to another voltage level.

[0002]

2. Description of the Related Art Semiconductor nonvolatile memory devices such as EE
In a PROM or the like, for example, from a power supply voltage V _{CC of} 5 V,
For example, a booster circuit that performs level conversion to a high voltage V _PP of 12 V or 20 V is used, and the boosted voltage V
_{It is configured} to generate the _PP and supply it to the write / erase control system. For such level conversion, for example, U
As disclosed in SP467829, a device using a charge pump has been used.
A device using an OS circuit has come to be used.

FIG. 7 is a circuit diagram showing a first configuration example of a conventional level conversion circuit using a CMOS circuit usually used in an EPROM or the like. In FIG. 7, NT ₁₁ , NT
₃₁ is an NMOS transistor, PT ₂₁ and PT ₃₁ are PMOS
Each transistor is shown. Drain and gate of the PMOS transistor PT ₃₁ and the NMOS transistor NT ₃₁ are connected, the PMOS transistor PT
The source of ₃₁ is connected to the supply line of high voltage V _PP and NM
The source of the OS transistor NT ₃₁ is grounded CMOS
An inverter is configured. Then, the output node ND ₃₁ by a connection point of the drains of both transistors are configured. The gate of the NMOS transistor NT ₁₁ is connected to the supply line of the power supply voltage V _CC, the source is connected to the supply line of the input voltage V _IN, the drain PM
It is connected to the drain of the OS transistor PT _21.
Node ND ₂₁ is configured by the connection midpoint between the drains of the NMOS transistors NT ₁₁ and the PMOS transistor PT _21. The node ND ₂₁ is CMOS
It is connected to a connection point of the gate of the PMOS transistor PT ₃₁ and the NMOS transistor NT ₃₁ constituting the inverter. Further, a PMOS transistor PT
₂₁ source connected to the supply line of the high voltage V _PP, the gate is connected to the output node ND _31.

In such a configuration, the input voltage V _IN supplied at the power supply voltage V _CC level, for example, 5 V, is NM
Via the OS transistor NT _11, it is applied to the gate of the PMOS transistor PT ₃₁ and the NMOS transistor NT _31. Accordingly, the PMOS transistor PT ₃₁
There turned off, NMOS transistor NT ₃₁ is turned on. Thus, the output node ND ₃₁ is pulled to the ground level. That is, the input voltage V _{IN of} 5 V is 0
It is converted to V and output as V _OUT . The ground level of the output node ND ₃₁ is a PMOS transistor PT ₂₁
Is supplied to the gate. Accordingly, PMOS transistor PT ₂₁ is turned on, the high voltage V _PP is the node ND
₂₁ , ie, PMOS transistor PT ₃₁ and NMO
It is applied to the gate of the S transistor NT _31. Therefore, the off-state and NM of the PMOS transistor PT ₃₁
ON state of the OS transistor NT ₃₁ is held stably.

On the other hand, when the input voltage V _IN is inputted at the ground level of 0 V, the PMOS transistor PT ₃₁ is turned on and the NMOS transistor NT ₃₁ is turned off. Thus, the output node ND ₃₁ is raised to a high voltage V _PP level. That is, the input voltage V _{IN of} 0 V
Is converted to a high voltage of 20 V and output as V _OUT . Also, V _PP level of the output node ND ₃₁ is supplied to the gate of the PMOS transistor PT _21. This allows
PMOS transistor PT ₂₁ is turned off, the input voltage V _IN is stably PMOS transistors PT ₃₁ and NM
It is applied to the gate of the OS transistor NT _31. Accordingly, the PMOS transistor PT ₃₁ turned on and N
Off state of the MOS transistor NT ₃₁ is held stably.

FIG. 8 is a circuit diagram showing a second configuration example of a conventional level conversion circuit. This circuit, in addition to the circuit components of FIG. 7, to connect the NMOS transistor NT ₂₁ between ground and the node ND _21, the NMOS transistor NT
A gate connected to ₂₁ the connection point between the gate and the output node ND ₃₁ of the PMOS transistor PT _21, and node N
The D ₂₁ is the gate of the NMOS transistor NT ₃₁ is connected only to the gate of the PMOS transistor PT ₃₁ not connected,
Connecting the gate of the NMOS transistor NT ₃₁ to the supply line of the input voltage V _IN.

In this circuit, the same level conversion operation as that of the circuit of FIG. 7 is performed. However, when the input voltage V _{IN of} 0 V is converted to the high voltage V _PP and output, the NMOS transistor NT ₂₁ is turned on. state, and the node ND ₂₁ is pulled to the ground level, the on state of the PMOS transistor PT ₃₁ is held stably.

FIG. 9 is a circuit diagram showing a third configuration example of a conventional level conversion circuit. This circuit connects the gate of the node ND ₂₁ and the PMOS transistor PT _31, constitute a cross-coupled by connecting the gate of the output node ND ₃₁ and the PMOS transistor PT _21, NMOS transistors N
Directly connected to the gate of T ₂₁ to the supply line of the input voltage V _IN, is connected to the gate of the NMOS transistor NT ₃₂ to the output of the inverter INV _11, the gate and the input voltage V _IN of the input of the NMOS transistor NT ₂₁ of the inverter INV ₁₁ Connected to the midpoint of connection with the supply line.

In this circuit, the power supply voltage V_CClevel,
For example, input voltage V supplied at 5V or 3V
_INIs the NMOS transistor NT_{twenty one}Applied to the gate of
And the inverter INV₁₁Receives level reversal action
The NMOS transistor NT at the ground level₃₁Gate of
Is applied to Accordingly, the NMOS transistor NT
_{twenty one}Is turned on, and the NMOS transistor NT₃₁But
State. Thereby, the node ND_{twenty one}Is the ground level
Drawn into. Node ND_{twenty one}Ground level is PMOS
Transistor PT₃₁Is applied to the gate of the PMOS transistor.
Transistor PT₃₁Is turned on. As a result, the output noise
ND₃₁Is the high voltage V_PPLevel up. sand
Word V_CCLevel input voltage V_INChanges to a high voltage of 20V
And V_OUTIs output as Also, the output node N
D₃₁V_PPLevel is PMOS transistor PT_{twenty one}Game
Supplied to Thereby, the PMOS transistor P
T_{twenty one}Is turned off and the node ND_{twenty one}Level is stable
Held at the ground level, the PMOS transistor PT ₃₁of
The ON state is stably maintained.

On the other hand, when the input voltage V _IN is inputted at 0 V, the NMOS transistor NT ₂₁ is turned off and the NMOS transistor NT ₃₁ is turned on. Thus, the output node ND ₃₁ is pulled to the ground level. That is, the input voltage V _{IN of} 0 V is output as V _OUT with the ground level _maintained . The output node ND ₃₁
The ground level is supplied to the gate of the PMOS transistor PT _21. Thereby, the PMOS transistor PT ₂₁
Is turned on, and the high voltage V _PP is applied to the node ND ₂₁ , that is, the gate of the PMOS transistor PT ₃₁ .
Accordingly, PMOS off state of the transistor PT ₃₁ is held stably, the output voltage V _OUT is output stably at the ground level.

FIG. 10 shows a fourth example of a conventional level conversion circuit.
FIG. 10 is a circuit diagram showing a configuration example, and this circuit is a circuit shown in FIG.
Is a circuit for a negative voltage corresponding to. In this circuit, NM
OS transistor NT_21aAnd NT_31aSource
For example, negative high voltage V such as -10V_BBConnect to supply line
And the node ND_{twenty one}And NMOS transistor NT_31aNo
And the output node ND₃₁And NMOS transistor
NT_21aCross-connects by connecting the gates of
S transistor PT _{twenty one}Input voltage V_INSupply la
To the PMOS transistor PT₃₂Game
To inverter INV₁₂Connected to the output of the inverter I
NV₁₂Input of the PMOS transistor PT_{twenty one}The gate and
Input voltage V_INTo the midpoint of the connection with the supply line of
PMOS transistor PT_{twenty one}And PT₃₁Power source
Source voltage V_CCConnected to the supply line.

In this circuit, an input voltage V _IN supplied at a power supply voltage V _CC level is applied to a PMOS transistor PT.
₂₁ and the inverter INV ₁₁
In receiving the level inversion effect is applied to the gate of the PMOS transistor PT ₃₁ at V _CC level. Along with this, PM
OS transistor PT ₂₁ is turned off, PMOS transistor PT ₃₁ is turned on. Thus, the output node ND ₃₁ is pulled up to V _CC level. That is, the input voltage V _IN of the V _CC level remains V _CC level,
Output as V _OUT . Also, V of the output node ND _{31
The CC} level is supplied to the gate of the NMOS transistor _NT21a . Thereby, the NMOS transistor NT _21a
Is turned on, and a negative high voltage V _BB is applied to the node ND ₂₁ , that is, the gate of the NMOS transistor NT _31a . Therefore, the NMOS transistor _NT31a is stably held in the off state, and the output voltage V _OUT is stably output at the V _CC level.

On the other hand, the input voltage V_INInput at 0V
And the PMOS transistor PT_{twenty one}Is turned on
The PMOS transistor PT₃₁Is turned off. This
As a result, the node ND_{twenty one}Is V_CCRaised to the level
You. Node ND_{twenty one}V_CCLevel is NMOS transistor
NT_31aOf the NMOS transistor N
T_31aIs turned on. Thereby, output node ND
₃₁Is the negative high voltage V_BBReduced to level. Sand
The input voltage V of 0V _INConverts to negative -10V high voltage
And V_OUTIs output as Also, the output node ND
₃₁V_BBLevel is NMOS transistor NT_21aGame
Supplied to Thereby, the NMOS transistor N
T_21aIs turned off and the node ND_{twenty one}Level is stable
To V_CCLevel and the NMOS transistor NT
_31aIs kept stable, and the output voltage V_OUTIs V
_BBOutput is stable at the level.

[0014]

As described above, various types of level conversion circuits are conventionally known, but the circuits shown in FIGS. 7 to 10 have the following problems. Was.

In the circuit shown in FIG. 7 which is usually used in an EPROM or the like, since there is an external power supply for V _PP , a problem arises in a through current at the time of switching of the PMOS transistor PT ₃₁ and the NMOS transistor NT _{31 in} the output stage. However, with the recent reduction in voltage, the voltage source voltage is lower than 5V, for example if it becomes 3V and 2V, by the threshold voltage is increased by the back bias effect of the NMOS transistor NT ₁₁ is not, There is a problem that it does not work.

On the other hand, in the circuits shown in FIGS.
Although low voltage operation is possible, shoot-through current becomes a problem. Hereinafter, the problem of the through current will be described in detail. This problem becomes a serious problem when the output of the booster circuit is used as a "power supply". Level conversion circuits and inverters included in the circuit,
If there are many logic circuits such as a NOR circuit and a NAND circuit, a through current flowing in the transition state becomes a problem. The through current is on the order of mA even if the size of the transistor is small, causing a large drop in the boosted voltage. This is because the time for the through current to flow is 0.1 to 1 ns, while the time for carrying the charge in the booster circuit is every several tens of ns. In particular, when the level conversion circuit switches 6 V at 3 V, for example, the switching time is slower than when switching 6 V at 6 V, so that the time during which the through current flows is longer.

Further, since the buffer connected to the subsequent stage of the level conversion circuit is generally a buffer for driving a larger capacity, the through current is small, and
Most is the charge / discharge current of the load capacity. Therefore,
In order not to waste the output of the booster circuit, it is important to reduce the through current of the level conversion circuit.

The present invention has been made in view of the above circumstances, and has as its object not only the capability of operating at a low voltage, but also the reduction of the through current, and the excessive consumption current output of the booster circuit. It is an object of the present invention to provide a level conversion circuit that can prevent the level conversion.

[0019]

In order to achieve the above object, according to the present invention, a first power supply is connected in series between a first power supply and a second power supply, and a connection point therebetween constitutes an output node . opposite polarity transistors and the first transistor
A second transistor, and a third transistor connected in parallel with the first and second transistors to the first power supply, at least the first and third transistors being cross-coupled, and A level conversion circuit for converting a voltage to a first or second power supply level, wherein a fourth transistor having the same polarity as the first transistor is connected in series between the first power supply and the output node. And above
The gate of the first transistor and the input voltage supply line
And a fifth transistor having a polarity opposite to that of the first transistor.
The source and drain of the transistor are connected in series,
At least the second and the gate of the fourth transistor is connected to the supply line of the input voltage.

[0020]

According to the present invention, for example, the output level is set to the first level.
When switching from the power level to the second power level,
The first and fourth transistors are controlled to be off, and the second transistor is controlled to be on. At the time of this level switching, the through current is reduced to a small value by the presence of the fourth transistor.

[0021]

Embodiment 1 FIG. 1 is a circuit diagram showing a first embodiment of a level conversion circuit according to the present invention. The same components as those in FIG. 8 showing a conventional example are denoted by the same reference numerals. That is, NT
₁₁ , NT ₂₁ , NT ₃₁ are NMOS transistors, PT ₂₁ ,
PT _31, PT ₃₂ is a PMOS transistor, ND ₃₁ output node, V _IN is the input voltage, the V _{OU T} indicates the output voltages, respectively.

[0022] Conventional circuit differs as shown in the circuit 8 connects the PMOS transistor PT ₃₂ between the drain and the output node ND ₃₁ of the PMOS transistor PT _31, the input gate of the PMOS transistor PT ₃₂ Voltage V
In that connected to the _IN connection point between the gate of the supply line and the NMOS transistor NT ₃₁ of the.

Next, the operation of the above configuration will be described. For example, the input voltage V _IN switched from the ground level (0 V) and supplied at the power supply voltage V _CC level is applied to the gate of the PMOS transistor PT ₃₁ via the NMOS transistor NT ₁₁ and directly to the NMOS transistor NT _31. and applied to the gate of the PMOS transistor PT _32. Accordingly, the PMOS transistor PT ₃₁
And PT ₃₂ are substantially turned off (because V _CC −V _PP <V _thp , they are not completely turned off) and the NMOS
Transistor NT ₃₁ is turned on. Thus, the output node ND ₃₁ is pulled to the ground level. That is, the input voltage V _IN at the V _CC level is converted to the ground level 0 V and output as V _OUT . At this time, the through current is narrowed smaller by the presence of the PMOS transistor PT _32.

Output node ND₃₁Ground level is P
MOS transistor PT_{twenty one}And NMOS transistors
NT_{twenty one}Is supplied to the gate. As a result, the PMOS transistor
Lanista PT_{twenty one}Turns on and the NMOS transistor
Star NT_{twenty one}Is turned off. Accordingly, the high voltage V_PP
Is the node ND_{twenty one}That is, the PMOS transistor PT ₃₁
Is applied to the gates. Therefore, the PMOS transistor
Star PT₃₁Are kept off.

On the other hand, when the input voltage V _IN is equal to the power supply voltage V
_When the input is switched from the _CC level to 0 V, PM
OS transistors PT ₃₁ and PT ₃₂ is turned on, NMOS transistor NT ₃₁ is turned off. Thus, the output node ND ₃₁ is raised to a high voltage V _PP level. That is, the input voltage V _{IN of} 0 V is converted into a high voltage of 20 V and output as V _OUT . Also, V _PP level of the output node ND ₃₁ is a PMOS transistor P
It is supplied to the gate of T ₂₁ and the NMOS transistor NT _21. Thus, PMOS transistor PT ₂₁ is turned off, NMOS transistor NT ₂₁ is turned on. Thus, the node ND ₂₁ is pulled to the ground level, the on state of the PMOS transistor PT ₃₁ is held stably.

[0026] In this case, NMOS transistor NT ₃₁ is switched to the quick-off state, transition of the amount that was inserted PMOS transistor PT _32, by an increase in the level of the output node ND ₃₁ is delayed, the OFF state of the PMOS transistor PT ₂₁ Is delayed, the PMOS transistor PT
_Although the through current flowing through ₂₁ is likely to be large, the following two points have a greater effect of reducing the through current when obtaining an output of 0 V described above. First point, the partial to than the size of the PMOS transistor PT ₂₁ and the NMOS transistor NT _21, to drive the load, PMOS transistor PT _31,
Since the direction of the size of the PT ₃₂ and the NMOS transistor NT ₃₁ is set larger, there is a difference in the through-current. The second point, since the PMOS transistor PT ₃₂ is in the normally on less concerned about in terms of breakdown voltage, the channel length P
MOS transistors PT ₂₁ and can be made shorter than the PT _31, capacity when the gate voltage is 0V may be sufficiently large. Further, when the gate voltage is V _CC level, the square to the gate voltage an effect greater through current blocking effect of obtaining an output of 0V as described above.

FIG. 2 shows the input / output characteristics of the circuit of FIG. 1, and FIG. 3 shows the through current i _VPP of the circuit of FIG. 1 (the present invention) and the conventional circuit. As can be seen from FIGS. 2 and 3, the circuit of the present invention has good input / output characteristics, and the through current i _VPP at the time of switching is significantly reduced as compared with the conventional circuit.

As described above, according to this embodiment,
The PMOS transistor PT ₃₁ and the NMOS transistor NT ₃₁ between the supply line of the high voltage V _PP and the ground are connected in series to configure the output stage, the output node ND ₃₁ and PMOS consists connection midpoint of the both transistors connect the PMOS transistor PT ₃₂ in series between the transistor PT _31, since then supplied the input voltage V _iN to the gate, it is possible low voltage operation as well, thereby reducing the through current . Therefore, an excessive current consumption output of the booster circuit can be prevented, and a decrease in output voltage can be avoided. As a result, the output current capability of the booster circuit can be reduced,
As a result, there is an advantage that the size of the booster circuit can be reduced.

It should be noted that in this embodiment, P
MOS transistors PT ₃₂ the output node ND ₃₁ and PMO
Was connected in series between the S transistor PT _31, it is not limited thereto and may be any between the supply line of the high voltage V _PP and the output node ND _31. Therefore, even when connecting the PMOS transistor PT ₃₂ in series between the supply line and the PMOS transistor PT ₃₁ of the high voltage V _PP, it is possible to reduce a through current.

[0030]

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the level conversion circuit according to the present invention. In this embodiment, in addition to the configuration of the first embodiment described above, also between the node ND ₂₁ and the PMOS transistor PT _21, PMO of through-current blocking
Connecting the S transistor PT ₂₂ in the series. And
The input voltage V _IN by level inverted by the inverter INV ₁₃ is supplied to the gate of the PMOS transistor PT ₂₂ and the NMOS transistor NT _21, and an inverter INV ₁₃
Output node ND ₃₁ via the NMOS transistor NT ₁₂ whose gate is connected to the power supply voltage V _CC to output and PM
It is configured to be supplied to the gate of the OS transistor PT _21.

Next, the operation of the above configuration will be described. ground
Power supply voltage V switched from level (0V)_CCAt the level
Supplied input voltage V_INIs the NMOS transistor NT
₁₁Through the PMOS transistor PT₃₁Apply to gate
And the NMOS transistor NT₃₁And
And PMOS transistor NT₃₂Is applied to the gates.
In parallel with this, the power supply voltage V_CCInput supplied at level
Voltage V_INIs the inverter INV₁₃Undergoes a level reversal effect at
And the NMOS transistor NT at the ground level₁₂Out through
Force node ND₃₁And PMOS transistor PT_{twenty one}No
And NMOS transistors directly
NT_{twenty one}And PMOS transistor NT _{twenty two}Sign on the gate
Be added.

Output node ND₃₁Inverter INV
₁₃And a ground level voltage is supplied by the
Transistor PT₃₁And PT₃₂Is almost off,
NMOS transistor NT₃₁Is turned on
Output node ND₃₁Level rapidly changes to the ground level
Move. That is, V_CCLevel input voltage V_INIs grounded.
Converted to 0V, V_OUTIs output as This and
The through current is the PMOS transistor PT₃₂Due to the existence of
Smaller. At this time, the PMOS transistor
TA PT_{twenty one}And PT_{twenty two}Turns on and the NMOS transistor
Transistor NT_{twenty one}Is turned off, the node ND
_{twenty one}Level is high voltage V_PPYou will be raised to a level. this
As a result, the PMOS transistor PT ₃₁OFF state is stable
Is held.

On the other hand, when the input voltage V _IN is equal to the power supply voltage V
_When the input is switched from the _CC level to 0 V, PM
OS transistors PT ₃₁ and PT ₃₂ is turned on, NMOS transistor NT ₃₁ is turned off, also the output node ND _31, NMOS transistors NT
_The power supply voltage V _CC level is supplied via ₁₂ . Thus, the output node ND ₃₁ is raised quickly to a high voltage V _PP level. That is, the input voltage V _{IN of} 0 V is 20 V
And output as V _OUT .

The PMOS transistors PT ₂₁ and PT ₂₂ are substantially turned off, and the NMOS transistors NT
_{Since 21} is turned on, the level of the output node ND ₂₁ is changed to the ground level. Also, V _PP level of the output node ND ₃₁ is supplied to the gate of the PMOS transistor PT _21. As a result, PMOS transistor PT ₂₁ is turned off. Therefore, the node ND ₂₁ is held stably ground level, the on state of the PMOS transistor PT ₃₁ is held stably. The through-current at this time is narrowed smaller by the presence of the PMOS transistor PT _22.

According to the second embodiment, in addition to the effects of the first embodiment, there is an advantage that a through current can be further reduced and an operation speed can be improved.

It should be noted that in the present embodiment, P
The MOS transistors PT ₂₂ between the node ND ₂₁ and the PMOS transistor PT ₂₁ connected in series, but is not limited to this, as in the case of PMOS transistor PT ₃₂ described above, the high voltage V _PP it may be anywhere between the supply line and the output node ND _31. Therefore, even when connecting the PMOS transistor PT ₃₂ in series between the supply line and the PMOS transistor PT ₂₁ of the high voltage V _PP,
Through current can be reduced.

[0037]

Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the level conversion circuit according to the present invention. This embodiment is different from the second embodiment in that the input voltage V _IN is supplied to the gate of the PMOS transistor PT ₃₁ via the NMOS transistor NT ₁₁ and the output of the inverter INV ₁₃ is supplied to the output node via the NMOS transistor NT _12. Instead of supplying the gates of the ND ₃₁ and the PMOS transistor PT ₂₁ , the input voltage V _IN is supplied directly to the gate of the NMOS transistor NT ₃₁ , and the output of the inverter INV ₁₃ is supplied directly to the gate of the NMOS transistor NT ₂₁ . It is in.

According to this embodiment, although the operation speed is inferior to that of the second embodiment, there is an advantage that the size of the transistor is not restricted, and the through current can be reduced.

[0039]

Fourth Embodiment FIG. 6 is a circuit diagram showing a fourth embodiment of the level conversion circuit according to the present invention.
Is a circuit for a negative voltage corresponding to the configuration of FIG.

[0040] In this circuit, instead of the NMOS transistor NT ₁₁ of the circuit of FIG. 1, the gate is grounded, using the PMOS transistor PT ₁₁ the substrate is connected to the supply line of the power supply voltage V _CC, NMOS transistors NT _21a and The source of NT _31a is connected to the supply line of a negative high voltage V _BB such as -10 V, and the node ND ₂₁ and NMOS
The gate of the transistor _{NT31a and} the output node ND
Constitute a cross-coupled by connecting the ₃₁ and the gate of the NMOS transistor NT _21a and PMOS transistor PT _21. Then, a through current blocking NMOS transistor NT _32a connected in series between the output node ND ₃₁ and the NMOS transistor NT _31a, NMOS transistors NT
It is directly connected to the gate of the gate and the PMOS transistor PT ₃₁ of _32a to the supply line of the input voltage V _IN.

In this circuit, the input voltage V _IN supplied at the power supply voltage V _CC level is the same as that of the PMOS transistor PT _11.
Together it is applied to the gate of the NMOS transistor NT _31a via the directly applied to the gate of the PMOS transistor PT ₃₁ and the NMOS transistor NT _32a. Accordingly, the NMOS transistors _NT31a and _NT32a are turned on, and the PMOS transistor PT
₃₁ is turned off. Thus, Thus, the output node ND ₃₁ is pulled down to the negative high voltage V _BB level.
That is, the input voltage V _IN at the power supply voltage V _CC level is −10.
It is converted to a negative high voltage of V and output as V _OUT .
Also, V _BB level of the output node ND ₃₁ is supplied to the gate of the NMOS transistor NT _21a and PMOS transistor PT _21. Thus, the NMOS transistor NT _21a is turned off, PMOS transistor PT ₂₁ is turned on, the level of the node ND ₂₁ is held stably in the V _CC level, the on state of the NMOS transistor NT _31a is stably maintained, the output voltage V _OUT is output stably at the V _BB level.

[0042] In contrast, when the input voltage V _IN is input at 0V, PMOS transistor PT ₃₁ is turned on, NMOS transistors NT _31a and NT _32a is substantially turned off. Thus, the output node ND ₃₁ is V _CC
The output voltage V _OUT is output at the _Vcc level. V _CC level at the output node ND ₃₁ is NMOS
Transistor NT _21a and PMOS transistor PT
Is applied to the gate of _21, NMOS transistors NT _21a
Is turned on, PMOS transistor PT ₂₁ is turned off. Thus, the node ND ₂₁ is negative high voltage V
Reduced to _BB level. V _BB level of the node ND ₂₁ is supplied to the gate of the NMOS transistor NT _31a. Therefore, the NMOS transistor _NT31a is stably held in the off state, and the output voltage V _OUT is stably output at the V _CC level.

In this embodiment, the same effect as that of the first embodiment can be obtained. In this embodiment, the NMOS transistor NT _32a for blocking a through current is used.
Output nodes have been connected in series between the ND ₃₁ and NMOS transistor NT _31a a is not limited thereto and may be any between the supply line of the negative high voltage V _BB and the output node ND ₃₁ . Therefore, even when connecting the NMOS transistor NT _31a in series between the supply line and the NMOS transistor NT _31a of the high voltage V _BB, it is possible to reduce a through current. Also, by connecting an NMOS transistor in series between the supply line of the node ND ₂₁ and the negative high voltage V _BB, it is possible to reduce further the through current.

[0044]

As described above, according to the present invention,
There is an advantage that a low level operation can be performed, a through current can be reduced, and a level conversion circuit capable of preventing an excessive current consumption output of the booster circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a level conversion circuit according to the present invention.

FIG. 2 is a diagram showing input / output characteristics of the circuit of FIG.

FIG. 3 is a diagram showing through currents of the circuit of FIG. 1 and a conventional circuit.

FIG. 4 is a circuit diagram showing a second embodiment of the level conversion circuit according to the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the level conversion circuit according to the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the level conversion circuit according to the present invention.

FIG. 7 is a circuit diagram showing a first configuration example of a conventional level conversion circuit.

FIG. 8 is a circuit diagram showing a second configuration example of a conventional level conversion circuit.

FIG. 9 is a circuit diagram showing a third configuration example of a conventional level conversion circuit.

FIG. 10 is a circuit diagram showing a fourth configuration example of a conventional level conversion circuit.

[Explanation of symbols]

_{NT 11, NT 21, NT 31} , NT 21a, NT 31a, NT
_32a ... NMOS transistor _{PT 21, PT 22, PT 31} , PT 32 ... PMOS transistor ND ₃₁ ... output node V _IN ... Input voltage V _OUT ... output voltage V _CC ... supply voltage V _PP ... positive high voltage V _BB ... negative High voltage

Claims (1)

(57) [Claims] A first power supply connected in series between a first power supply and a second power supply, and a connection point between the first power supply and the second power supply to form an output node;
Polarity of the transistor and the first transistor opposite
And a third transistor connected in parallel with the first and second transistors to the first power supply, at least the first and third transistors are cross-coupled, and the input voltage To a first or second power supply level, wherein a fourth transistor having the same polarity as the first transistor is connected in series between the first power supply and the output node. , A gate of the first transistor and an input voltage supply line.
Between the first transistor and the fifth transistor having a polarity opposite to that of the first transistor.
The source and drain of each transistor are connected in series.
Is, the level conversion circuit in which the gate of the at least the second and fourth transistors are characterized by being connected to the supply line of the input voltage.