JPH0716097B2 - Method for manufacturing multilayer printed wiring board - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a multilayer printed wiring board, and in particular, multilayer printing partially having through holes formed by dividing conductor layers for high-density mounting. The present invention relates to a method for manufacturing a wiring board.

[Conventional technology]

In order to improve the performance and economical efficiency of highly integrated electronic devices such as LSI and IC, the density of multilayer printed wiring boards (hereinafter referred to as “multilayer boards”) is increasing.

Two main measures are taken to increase the density of multilayer boards. First, there is an increase in the number of conductor layers, that is, a higher number of layers,
The second measure is to increase the number of wiring lines between basic grids. However, in the first measure, the number of via holes connecting the conductor layers between the layers is increased, and the second measure increases the number of wirings, and the wiring accommodability is significantly limited. So, in particular,
When this via hole is provided as a through hole in the multilayer board, it is dealt with by reducing the diameter of the via hole, but the plate thickness / hole diameter ratio (aspect ratio) increases and the productivity of the multilayer board is significantly hindered. ing.

Therefore, as a means for solving the above-mentioned drawbacks, as shown in FIG. 3 (A), two sets of the catalyst-containing insulating substrates 3 on which the conductor circuit patterns 1 are formed are arranged in the outermost layers, respectively.
As shown in FIG. 3 (B), an insulating substrate 4 without a catalyst and a prepreg 5 with a catalyst provided with a hole portion 16 hollowed out in a concentric circle having a diameter larger than the diameter of the through hole of the multilayer plate are inserted therein. 3, a step of forming a multilayer substrate 7 by heating and pressurizing, a step of forming a through hole 8 at a predetermined position of the multilayer substrate 7 as shown in FIG. As shown in (D), the conductor layer 11 that is electrically connected to the end face of the conductor circuit pattern 1 is formed on the end face of the insulating substrate 3 containing catalyst on the inner wall of the through hole 8 of the multi-layer substrate 7 by electroless plating, and then divided. There is an example of achieving high density by selectively forming the via hole 12 and the normal through hole 13 (Japanese Patent Application No. 61-02936).
1).

[Problems to be Solved by the Invention]

However, in the above-described conventional manufacturing method, a hole formed in a concentric circle having a diameter larger than the diameter of the through hole is provided in the through hole for forming the normal through hole in the insulating substrate without a catalyst inside the multilayer substrate. Therefore, there is a drawback that a clearance is required between the through hole and the hole portion, the basic lattice in the plane direction cannot be made small, and it becomes a factor that hinders high density in the plane direction.

Further, since it is necessary to fill the above-mentioned holes only with the resin containing the catalyst impregnated in the prepreg containing the catalyst, a void is generated when the thickness of the insulating substrate without the catalyst is too large, and thus the thickness is restricted, There is a drawback that it becomes a limiting factor for the electrical characteristics, especially the impedance characteristics, of the multilayer board.

Furthermore, it is necessary to adjust the amount of resin in the catalyst-containing prepreg layer according to the number of holes, and it is difficult to control the smoothness of the multilayer plate and the interlayer thickness depending on the degree of concentration of the holes in the plane direction. There is a drawback that

An object of the present invention is to provide a method of manufacturing a multilayer printed wiring board which has a high density, has no restriction on impedance characteristics, and can control smoothness and interlayer thickness.

[Means for Solving the Problems]

The method for manufacturing a multilayer printed wiring board according to the present invention is such that a conductor circuit pattern is provided on one side in advance, and two sets of catalyst-containing insulating substrates each having a conductor on the entire other side are provided with the conductor circuit pattern inside. A step of forming an insulating substrate without catalyst and a prepreg containing a catalyst inside the outermost layer, heating and pressurizing to form a multi-layered substrate, and forming a through hole at a predetermined position of the multi-layered substrate. A step of masking a part of the through hole, adsorbing a catalyst on the inner wall of the through hole that is not masked, a step of removing the mask, the insulating substrate containing the catalyst on the inner wall of the through hole, and And a step of forming a conductor layer by electroless plating including a catalyst-containing insulating layer formed of the catalyst-containing prepreg and a portion where the catalyst is adsorbed.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1A to 1F are vertical cross-sectional views showing the order of steps for explaining the manufacturing method according to the first embodiment of the present invention.

In the first embodiment, first, as shown in FIG. 1 (A), the conductor circuit pattern 1 is previously provided on one side by a photo printing method,
In addition, one set of two catalyst-containing insulating substrates 3 each having a copper foil 2 on the entire other surface is placed in the outermost layer with the conductor circuit pattern 1 inside, and the insulating substrate 4 without catalyst and the catalyst are placed inside thereof. Insert it with the prepreg 5 and set it.

Next, as shown in FIG. 1 (B), heating and pressurization are performed to obtain a multilayer substrate 7 including the catalyst-containing insulating layer 6 and the catalyst-free insulating substrate 4.

Next, as shown in FIG. 1 (C), through holes 8a and 8b are drilled at predetermined positions by an N / C drilling device.

Next, as shown in FIG.
The through holes 8a forming the rule by a photo printing method, for example,
DuPont Dry Film Liston 1220 Using,
After forming the mask 9, based on palladium chloride
The through hole 8b without mask 9 is immersed in the catalyst solution.
The catalyst 10 is adsorbed on the entire inner wall.

Next, as shown in FIG. 1 (E), after removing the mask 9 with an organic solvent (not shown), electroless copper plating is applied to both surfaces of the multilayer substrate 7 and the inner walls of the through holes 8a, 8b. A conductor layer 11 is formed on the. In this case, in the through hole 8a, the conductor layer 11 is formed only on the catalyst-containing insulating layer 6 and not on the insulating substrate 4 without a catalyst, so that the conductor layer 11 is separated at the inner wall of the through hole 8a, Moreover, the conductor circuit pattern 1 and the outer copper foil 2
On the other hand, in the through hole 8b, the conductor layer 11 is formed on the entire inner wall by the catalyst 10 previously adsorbed.

Next, as shown in FIG. 1 (F), a multilayer printed wiring board including divided via holes 12 and normal through holes 13 is formed by forming a circuit of the outermost layer by a photo printing method.
You get 14.

2 (A) and 2 (B) are vertical cross-sectional views showing the manufacturing process of the second embodiment of the present invention in the order of steps.

In the embodiment shown in FIG. 1, the conductor layer 11 was formed only by electroless plating as shown in FIG. 1 (F), but in the second embodiment, first, as shown in FIG. As shown in A), after forming the conductor layer 11 by electroless plating by thin plating of about several μm, the conductor layer 15 is formed by thick plating by electroless plating such as copper pyrophosphate bath. .

Next, as shown in FIG. 2 (B), by the photo printing method,
A multilayer printed wiring board (14) having divided via holes (12) and normal through holes (13) is obtained.

The manufacturing method other than the method of forming the conductor layer 11 described above is the same as that of the first embodiment.

In general, an insulating resin used for a printed wiring board has poor alkali resistance, whereas an electroless plating bath has high temperature and high alkalinity, has a low deposition rate, and requires long-time plating. Therefore, by using an electroless plating bath that has a high plating rate and does not require a highly alkaline bath, it is possible to prevent material deterioration in the separated portion of the conductor layer 11 of the divided via hole 12, thereby enabling a high-density basic grid design. There is an advantage that makes it possible.

〔The invention's effect〕

As described above, according to the present invention, when selectively forming divided via holes in a multilayer printed wiring board, various design constraint elements such as the basic lattice arrangement, the interlayer thickness, and the characteristic impedance design as in the prior art are used. There is no effect, and there is an effect that a high-density multilayer printed wiring board having a significantly improved wiring accommodation property can be obtained.

[Brief description of drawings]

1 (A) to 1 (F) are longitudinal sectional views showing the manufacturing method of the first embodiment of the present invention in the order of steps, FIG. 2 (A),
(B) is a longitudinal sectional view showing the manufacturing method of the second embodiment of the present invention in the order of steps, and FIGS. 3 (A) to (D) are examples of the conventional method for manufacturing a multilayer printed wiring board. FIG. 6 is a vertical cross-sectional view showing in the order of steps to be performed. 1 ... Conductor circuit pattern, 2 ... Copper foil, 3 ... Insulating substrate with catalyst, 4 ... Insulating substrate without catalyst, 5 ... Prepreg with catalyst, 6 ... Insulating layer with catalyst, 7 ... Multilayer Substrate, 8,8a, 8b ... Through hole, 9 ... Mask, 10 ... Catalyst, 1
1 …… Conductor layer, 12 …… Separated via holes, 13 ……
Ordinary through hole, 14 ... Multi-layer printed wiring board, 15 ... Electrolytic plating conductor layer, 16 ... Hole part.

Claims (1)

[Claims] 1. A catalyst-containing insulating substrate having a conductor circuit pattern provided on one surface in advance and a conductor provided on the other surface entirely.
A step of forming a multi-layered substrate by placing one set of each in the outermost layer with the conductor circuit pattern inside and inserting an insulating substrate without a catalyst and a prepreg containing a catalyst inside and heating and pressurizing it. A step of forming a through hole at a predetermined position of the multilayer substrate; a step of masking a part of the through hole and then adsorbing a catalyst on the inner wall of the through hole that is not masked; and a step of removing the mask. A step of forming a conductor layer by electroless plating including a catalyst-containing insulating layer formed of the catalyst-containing insulating substrate and the catalyst-containing prepreg on the inner wall of the through hole and a portion where the catalyst is adsorbed. A method for manufacturing a multi-layer printed wiring board, which is characterized.