JPH07160379A - Signal processor - Google Patents

Abstract

(57) [Summary] [Structure] The data processor is provided with an input / output circuit capable of inputting and outputting signals at any of a plurality of levels, and the peripheral device outputs a response signal to the instruction signal from the data processor. Means are provided, and means for receiving the response signal and providing a switching signal corresponding to the response signal to the input / output circuit is provided between the data processor and the peripheral device. [Effect] When a system is configured by combining devices having different power supply voltage specifications, the data processor dynamically changes the signal level so as to match the peripheral device of the communication partner without providing a large-scale external circuit. As a result, it is possible to configure a system that combines devices with different power supply voltage specifications at low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital system construction technique, and further to a technique effectively used for constructing a system in which devices having different power supply voltage specifications coexist and a system corresponding to a plurality of power supply voltage specifications.

[0002]

2. Description of the Related Art Currently, a single power supply of 5V is generally used as a standard power supply voltage for digital systems. However, from the viewpoints of miniaturization of LSI process technology, low power consumption of the system, reduction of influence on noise, etc., the demand for lowering the power supply voltage is increasing, and the power supply voltage is 3V.
Alternatively, devices and systems below that have been put into practical use, and there are data processors and peripheral devices having various power supply voltage specifications. Under these circumstances, the following two methods are generally adopted when configuring the system.

First, it is possible to combine devices having different input / output signal levels depending on the power supply voltage specifications of the devices making up the system, and to provide a level converter on these signal lines for communication. It is a system.
For example, power supply voltage lines of 5V and 3.3V are prepared in the system, 5V specification products and 3.3V specification products are mixed, and a level converter is inserted in the signal line between them to enable communication. It is a thing. The other is a single power supply voltage system that uses the same power supply voltage specifications and the same input / output signal level for each device that constitutes the system.
There are V single system and 3.3V single system, but the data processors and peripherals used are 5V specification product and 3.3V specification product.

[0004]

However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, when a system is configured by a plurality of devices having different power supply voltage specifications and these devices are interconnected via a level converter, the number of parts increases and the cost increases accordingly.
Further, if a level converter is provided on the signal line, the communication speed will be slowed down.

On the other hand, in the case of constructing a system consisting only of devices having the same power supply voltage specification, data processors and peripheral devices are required for the number of power supply voltage specifications. Must be designed and manufactured, and the manufacturing cost becomes very high. Also,
At present, it is in the transition period to low power supply voltage, so when constructing a low power supply voltage system, it is not always the case that a low power supply voltage system device having the same function as a 5V system device is manufactured. Sometimes it is not possible to build a system.

An object of the present invention is to enable a system to be constructed at low cost without providing a large-scale external circuit when the system is constructed by combining devices having different power supply voltage specifications. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, when a system is configured by combining devices with different power supply voltage specifications, it is possible to input / output signals at any of multiple levels to the data processor instead of interposing a level converter between the devices with different power supply voltage specifications. In addition to providing such an input / output circuit, the peripheral device is provided with means for outputting a response signal to the instruction signal from the data processor, and between the data processor and the peripheral device,
A means for receiving the response signal and providing a switching signal corresponding to the response signal to the input / output circuit is provided.

Further, between the data processor and the peripheral device,
Instead of providing a means for receiving the response signal and giving a switching signal corresponding to the response signal to the input / output circuit, a means for identifying a peripheral device as a communication partner is provided inside the data processor and one of a plurality of levels. An input / output circuit capable of inputting / outputting a signal is provided, and the level of the signal to be output by the input / output circuit is determined according to the signal formed by the identifying means when communicating between the data processor and the peripheral device. It may be done.

[0009]

According to the above-mentioned means, the data processor can dynamically change the signal level so as to match with the peripheral device of the communication partner without providing a large-scale external circuit, thereby reducing the cost. The above object of being able to configure a system in which devices with different power supply voltage specifications are combined is achieved. Moreover, since a system in which devices having different power supply voltage specifications are combined can be configured, there is no need to design a device for each power supply voltage specification, and the cost can be reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined. The system of this embodiment is
Although not particularly limited, a plurality of LSI chips are mounted on a single printed circuit board, for example.

In FIG. 1, reference numeral 1 is a data processor as a central device, PE0, PE1, ... PEn are peripheral devices such as a memory connected to the data processor 1 via signal lines such as a bus. Each of the processor 1 and each of the peripheral devices PE0, PE1, ..., PEn is composed of one semiconductor chip such as silicon and is an LSI.
Has been converted. In this embodiment, the peripheral devices PE0, PE
1, ......... PEn is a mixture of 5V type devices (devices driven by a power supply voltage of 5V) and 3V type devices (devices driven by a power supply voltage of 3.3V). The system is configured. On the other hand, the data processor 1 is composed of a higher power supply voltage system, that is, a 5V system device of the peripheral devices PE0, PE1, ... PEn.

The data processor 1 includes an address generation circuit 11, a data calculator 12, a bus control circuit 13 and the like, and outputs an address signal generated by the address generation circuit 11 and a bus control signal formed by the bus control circuit 13. The peripherals PE0, PE1, ... PEn are output to the outside by the drivers 14a and 14b, data is taken in through the input / output driver 15, and the data calculator 1 is used.
2 performs arithmetic processing, and the result is the above peripheral device PE.
0, PE1, ......... Has a function of outputting to PEn.

The address signal output from the output driver 14a is decoded by the decoder control circuit 3 to form a selection signal (chip select signal CS). The selection signal causes the peripheral devices PE0, PE1, ... P.
Select and specify any one of En. Although not particularly limited, the decoder control circuit 3 is supplied with the higher power supply voltage of the system, that is, 5V. Therefore,
The selection signal output from the decoder control circuit 3 is set to a 5V system signal level.

In this embodiment, the peripheral devices PE0, P0
Each of E1, ..., PEn includes a response signal generation circuit 21 therein, and is configured to form and output a response signal when receiving the selection signal (CS). The response signal is a signal according to the power supply voltage level of each peripheral device, that is, a signal having an amplitude of 5V or close to 5V peripheral device, and a signal having an amplitude of 3V or close to 3V peripheral device. To be done. Therefore, the response signal generation circuit 21 in the 3V peripheral device is configured to have a function of receiving the 5V selection signal (CS) and converting the level into the 3V response signal. On the other hand, the input / output driver 15 in the data processor 1 is configured to be able to selectively input / output either a signal of a level suitable for a 3V system device or a signal of a level suitable for a 5V system device, The level of the input / output signal is selected by the switching signal CH input from the terminal 16.

Further, in this embodiment, the response signals output from the peripheral devices PE0, PE1, ... PEn are received between the data processor 1 and the peripheral devices PE0, PE1 ,. A response signal control circuit 4 for determining the level and forming a switching signal CH for the input / output driver 15 in the data processor 1 is provided. The response signal control circuit 4 includes, for example, two inverters provided for each input response signal and having different logic threshold levels, and the response signal input based on the output signals of these inverters is a 3V system. It can be configured by a logic circuit that determines whether the signal is a 5V system signal or not and forms a switching signal CH in accordance with the signal. The response signal control circuit 4 is configured to generate and output a switching signal that causes the data processor to output a signal of a predetermined level when there is no response signal.

In this embodiment, the level of the input / output signal in the input / output driver 15 in the data processor 1 is adjusted by the switching signal CH from the response signal control circuit 4, so that the 3V type device and the 5V type device are controlled. It becomes possible to communicate between the data processor and the peripheral device in the mixed system. Moreover, even if the 3V system peripheral device and the 5V system peripheral device are replaced, the response signal control circuit 4 detects this and forms a switching signal corresponding to the response signal and supplies it to the data processor 1. Communication with peripheral devices is guaranteed.

The central device (1) in this embodiment
Is not limited to a data processor, and is a device that has a so-called microprocessor, coprocessor, digital signal processor, or other data processing function and plays a central role in a system, regardless of its name. It may be a device, and does not necessarily have the address output function and the bus control signal output function as in the above-described embodiment.

FIG. 2 shows another embodiment of the data processing system to which the present invention is applied. This embodiment corresponds to a modification of the system of FIG. 1, and the system of FIG. 1 is configured by two power supply voltage system devices, a 5V system device and a 3V system device. The second system is composed of n power supply voltage system (V0, V1, V2 ... Vn) devices. The data processor 1
Is composed of the highest power supply voltage (V0) system device in the system, and the input / output driver 15 in the data processor 1 has levels (V0, V1, V2 ...) Suitable for the respective power supply voltage system devices. .. Vn) is selectively input / output, and the level of the input / output signal is selected by the switching signals CH0 ... CHn input from the external terminal 16. Although not shown, each of the peripheral devices PE0, PE1, ... PEn has a built-in response signal generation circuit similar to that of the embodiment of FIG.
Other configurations are similar to those of the system shown in FIG.

FIG. 3 shows a second embodiment when the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined. In this embodiment, instead of the response signal control circuit 4 in the embodiment of FIG. 1, information indicating whether the peripheral device is a 3V system or a 5V system is entered in the data processor 1 in correspondence with the address range of each peripheral device. The address reference table 17 as the identification means is prepared, the address generated by the address generation circuit 11 is used to refer to the address reference table 17 to identify the communication partner, and the switching signal CH corresponding thereto is input / output the driver 15 To adjust the level of the input / output signal. The address reference table 17 is a RAM (random
Access memory) or registers.

According to the system of this embodiment, an external circuit such as the response signal control circuit 4 in the embodiment of FIG. 1 is unnecessary, and the system is simplified. Further, the peripheral devices PE0, PE1, ... PEn do not need to form and output a response signal even when receiving the selection signal, and there is an advantage that no design change is required in applying the present embodiment. . It should be noted that predetermined data may be written in the address reference table 17 in advance during initialization of the system via an internal data bus or an external terminal provided separately. Further, instead of providing the address reference table 17 in the data processor 1, it is also possible to provide it in the external decoder control circuit 3.

FIG. 4 shows another embodiment of the data processing system to which the present invention is applied. This embodiment is shown in FIG.
This embodiment is a modification of the above embodiment, and the difference is that the switching signal output from the address reference table 17 is supplied not only to the input / output driver 15 but also to the external decoder control circuit 3 and the decoder control circuit 3. The input / output driver is also configured to selectively input / output a signal of a level suitable for a 3V system device or a signal of a level suitable for a 5V system device, and is supplied from the decoder control circuit 3 to peripheral devices. The level of the selected signal is also changed according to the power supply voltage specification.

According to the system of this embodiment, the response signal control circuit 4 in the embodiment of FIG. 1 is unnecessary, and the peripheral devices PE0, PE1, ... No need to form and output
The application of this embodiment has an advantage that no design change is required.

FIG. 5 shows a third embodiment when the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined. In this embodiment, the data processor 1 in the embodiment of FIG.
This is an example in the case of being configured to be operable at any power supply voltage of the system. That is, the data processor 1 of this embodiment is internally provided with the power supply voltage detection circuit 18 and the switching signal control circuit 19, and the switching signal control circuit 19 supplies the power supply voltage detection signal from the power supply voltage detection circuit 18 and the external terminal. The switching control signal CH for the input / output driver 15 is formed based on the switching signal supplied from the response signal control circuit 4 via 16. Other configurations are similar to those of the embodiment shown in FIG.

The power supply voltage detection circuit 18 shown as an example in FIG. 5 includes a voltage detection unit composed of a resistor R1 and a Zener diode D1 in the reverse direction, which are connected in series between the power supply voltage V0 and the ground point. The signal forming section is composed of a P-channel MOSFET Q1 and a resistor R2 connected in series between the power supply voltage V0 and the ground point. In the power supply voltage detection circuit 18, when a power supply voltage V0 close to 5V is applied, a current flows through the Zener diode D1,
The node N1 of the voltage detecting unit has a potential (0 V) close to the ground point, which turns on the MOSFET Q1 and the output node N2 of the signal forming unit has a potential close to the power supply voltage V0.

On the other hand, the power supply voltage detection circuit 18 is 3.3V.
When a power supply voltage V0 close to is applied, the current flowing through the Zener diode D1 is cut off, and the node N1 of the voltage detection unit becomes a potential 3.3V close to the power supply voltage V0, whereby the MOSFET Q1 is turned off, The output node N2 of the signal forming unit has a potential (0 V) close to the ground point. According to this embodiment, since the data processor 1 has the power supply voltage detection circuit 18, the peripheral devices PE0, P0.
E1, ......... Everything that was a 5V type device in PEn was replaced with a 3V type device, and the peripheral device PE
When the power supply voltage of 0, PE1, ...

FIG. 6 shows another embodiment of the data processing system to which the present invention is applied. This embodiment is shown in FIG.
In the data processor 1 of the embodiment shown in FIG. 5, the power supply voltage detection circuit 18 and the switching signal control circuit 19 of the embodiment of FIG.
Is built in. Therefore, the embodiment of FIG. 6 combines the advantages of the embodiment of FIG. 4 with the advantages of the embodiment of FIG.

FIG. 7 shows an embodiment of the variable amplitude input / output driver circuit 15 provided in the data processor. In the figure, reference numeral 15a is an output driver, and reference numeral 15b is an input buffer. Output driver 15a
Is a P-channel MOSFET connected in series between a power supply voltage Vcc of 5V and a ground potential (0V).
A push-pull type output stage including a 151 and an N-channel MOSFET 152 and an N-channel MOSFET 153 connected in parallel with the P-channel MOSFET 151 is provided. Also, the output driver 15
a is a signal for receiving the switching signal CH from the response signal control circuit 4 or the address reference table 17, the enable signal EN from the internal circuit, and the data signal DT to be output, and controlling the turning on and off of each of the MOSFETs 151 to 153. It has a logic circuit portion to be formed.

The output stage is a P-channel MOSFET.
When 151 is turned on and N-channel MOSFETs 152 and 153 are turned off, a signal of Vcc level (5V) is output. On the other hand, N-channel MOSFET 15
3 is turned on and the P-channel MOSFET 151 and the N-channel MOSFET 152 are turned off, V
A signal having a level lower than cc by the threshold voltage of MOSFET 153 is output. Therefore, MOSFET 15
By setting the threshold voltage of 3 to a value such as 1.7 V, a high level signal such as 3.3 V can be output. Further, the output stage is M
When all the OSFETs 151 to 153 are turned off, the output is brought into a high impedance state. The enable signal EN is a control signal for switching the output stage between a data output state and an output high impedance state. When the enable signal EN is at a high level, it is in a data output state, and when it is at a low level, it is an output high impedance state. It is said that

The logic circuit section includes the signals CH, EN,
3-input NAND gate G1 having DT as an input signal and 2-input NAN having the signals CH, EN and DT as input signals
Two-input NAND having the D gate G2 and the signal EN and the signal DT which are inverted by the inverter G4 as input signals
A gate G3, inverters G5 and G6 for transmitting the output signal of the NAND gate G1 to the gate terminal of the high-side output MOSFET 151, and an inverter for inverting the output signal of the NAND gate G2 and transmitting it to the gate terminal of the high-side output MOSFET 153. G7 and an inverter G8 that transmits the output signal of the NAND gate G1 to the gate terminal of the low-side output MOSFET 152.

Table 1 shows the signals CH, EN and DT input to the output driver 15a and the output driver 15a.
The relationship with the level of the signal output from is shown.

[Table 1] From the above table, by switching the switching signal CH, C
When H is low level, output level is 5V system,
It can be seen that the output level can be switched to the 3V system when CH is at the high level.

The input buffer 15b has input inverters G11, G1 set with different logic threshold voltages.
G12, a transmission gate TG1 for transmitting the output signal of the input inverter G11 to the internal logic circuit, and a transmission gate TG2 for transmitting the output signal of the input inverter G12 to the internal logic circuit. The transmission gates TG1 and TG2 are not particularly limited,
A transmission gate composed of a P-channel MOSFET and an N-channel MOSFET connected in parallel to each other is used, and is configured to be complementarily turned on / off by the switching signal CH. Specifically, when the switching signal CH is low level, the transmission gate TG1 is rendered conductive to transmit the output signal of the input inverter G11 to the internal logic circuit, and when the switching signal CH is high level, the transmission gate TG2 is turned on. The output signal of the input inverter G12 is rendered conductive and transmitted to the internal logic circuit.

For example, in the case of the CMOS interface, the logic threshold voltage of the input inverter G11 is 5V system by controlling the gm ratio or the gate size ratio of the P-channel MOSFET and the N-channel MOSFET which compose the input inverter G11. Is set to a value such as 2.5V according to the signal of
Logic threshold voltage of 1.65 according to 3V system signal
It is set to a value like V. On the other hand, when another interface such as the TTL interface is used, the logical threshold voltage of the input inverter may be set so as to match the interface. Therefore, by switching the switching signal CH, the input buffer 15b of the present embodiment appropriately sets the level through the inverter G11 when the external input signal is 5V system and through the inverter G12 when the external input signal is 3V system. The determined signal can be supplied to the internal circuit.

FIG. 8 shows a fourth embodiment in which the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined. This embodiment is an example of a system composed of a plurality of boards, and n boards B0 and B each composed of a plurality of LSI chips.
1, ... Bn is inserted into a connector 210 provided in a housing (rack) 200, and the connectors 210 into which boards are inserted are electrically connected to each other by a bus 220 to form one data processing system. Is configured.

Here, each of the boards is a so-called CPU board composed of a processor chip such as a data processor, a microprocessor, or a coprocessor and an I / O interface chip, a memory board composed of a plurality of memory chips, Analog L such as A / D converter
Peripheral boards configured with SI chips are included. In this embodiment, although not particularly limited, the power supply voltage is unified to 5V or 3.3V for each board, and CP
A decoder control circuit 3 and a response signal control circuit 4 similar to those of the embodiment shown in FIGS. 1 to 6 are provided between the U board and other peripheral boards, and an address conversion table is provided on the CPU board. Equipped with memory or register,
It is configured to be able to communicate with each other even if the power supply voltage is different for each board.

FIG. 9 shows a fifth embodiment in which the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined. This embodiment is configured as a device protected by a housing (rack) in the same unit as each board in the system shown in FIG. 8, and is a control device as a central device including a data processor and the like. 100 and peripheral device 110 (PE1, PE
2 ......... PEn), cable 3 instead of bus
00, they are electrically connected to each other. Also in this embodiment, the power supply voltage is 5 for each device.
It is standardized to V or 3.3V, and the central unit 10
0 and other peripheral devices 110 (PE1, PE2 ......... PE
n), a decoder control circuit 3 and a response signal control circuit 4 similar to those of the embodiment shown in FIGS. 1 to 6 are provided, or a memory or a register having an address conversion table is provided in the central device 100. It is provided so that the devices can communicate with each other even if the power supply voltage is different.

As described above, in the above embodiment, the data processor is provided with the input / output circuit capable of inputting / outputting the signal at any of a plurality of levels, and the peripheral device receives the instruction signal from the data processor. A means for outputting a response signal is provided, and a means for receiving the response signal and giving a switching signal corresponding to the response signal to the input / output circuit is provided between the data processor and the peripheral device. When configuring a system by combining devices with different voltage specifications, the data processor can dynamically change the signal level so as to match the peripheral device of the communication partner, without providing a large-scale external circuit. As a result, it is possible to configure a system that combines devices with different power supply voltage specifications at low cost. Moreover, there is no need to design a device for each power supply voltage specification, and there is an effect that cost can be reduced.

Further, a means for identifying a peripheral device to be a communication partner and an input / output circuit capable of inputting / outputting a signal at any of a plurality of levels are provided inside the data processor, and when communication is performed between the data processor and the peripheral device. In addition, since the level of the signal to be output by the input / output circuit is determined according to the signal formed by the identifying means, the scale of the external circuit can be further reduced, and the power supply can be manufactured at a lower cost. A system that combines devices with different voltage specifications can be configured.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the power supply voltage is not limited to 5V and 3.3V, and may have another voltage value. In the above description, the case where the invention made by the present inventor is mainly applied to the data processing system which is the background field of application has been described. However, the present invention is not limited thereto, and a plurality of power supply voltage specifications are different. The present invention can be used for general systems including semiconductor devices (including IC and LSI).

[0039]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it is possible to configure a system that combines devices with different power supply voltage specifications at low cost, and it is not necessary to design a device for each power supply voltage specification, so that the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined.

FIG. 2 is a block diagram showing another embodiment of a data processing system to which the present invention is applied,

FIG. 3 is a block diagram showing a second embodiment when the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined;

FIG. 4 is a block diagram showing another embodiment of the data processing system to which the present invention is applied,

FIG. 5 is a block diagram showing a third embodiment when the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined;

FIG. 6 is a block diagram showing another embodiment of the data processing system to which the present invention is applied,

FIG. 7 is a circuit diagram showing an embodiment of a variable amplitude input / output driver circuit provided in a data processor,

FIG. 8 is a block diagram showing a fourth embodiment when the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined;

FIG. 9 is a block diagram showing a fifth embodiment when the present invention is applied to a data processing system in which devices having different power supply voltage specifications are combined.

[Explanation of symbols]

 PE0 to PEn Peripheral device 1 Central device (data processor) 3 Decoder control circuit 4 Response signal control circuit 11 Address generation circuit 12 Data calculator 13 Bus control circuit 15 Input / output driver 17 Address reference table 18 Power supply voltage detection circuit 19 Switching signal control Device 21 Connector 22 Bus 30 Cable 100 Controller 110 Peripheral device

Claims (4)

[Claims] 1. A central device for processing a signal or data is provided with an input / output circuit capable of inputting / outputting a signal at any of a plurality of levels, and a peripheral device responds to an instruction signal from the central device. A means for outputting a signal is provided, and a means for receiving the response signal and providing a switching signal corresponding to the response signal to the input / output circuit is provided between the data processor and the peripheral device. Signal processing device. 2. The central device is provided with a power supply voltage detecting means therein, and is configured to determine an input / output level in the input / output circuit based on a detection signal from the power supply voltage detecting means and the switching signal. The signal processing device according to claim 1, wherein the signal processing device comprises: 3. A central device for processing a signal or data is provided with a means for identifying a peripheral device as a communication partner and an input / output circuit capable of inputting / outputting a signal at any of a plurality of levels inside the central device. And a peripheral device, the level of the signal to be output by the input / output circuit is determined according to the signal formed by the identification means when the communication is performed between the signal and the peripheral device. Processing equipment. 4. The central device internally includes a power supply voltage detecting means, and determines an input / output level in the input / output circuit based on a detection signal from the power supply voltage detecting means and a signal from the identifying means. The signal processing device according to claim 3, wherein the signal processing device is configured as described above.