JP2008085876A - Interface circuit and circuit system using the same - Google Patents

Abstract

Even when there is a difference in interface voltage between various devices, the difference in the interface voltage is dynamically absorbed when signals are transferred between the devices.
An interface circuit interposed between a device and a common connection line when a plurality of devices send and receive signals through the common connection line, and when a signal is output from the device to the common connection line, An output converter that converts the signal level in the device to a signal level that is appropriate for the device that is exchanged on the common connection line, and that that corresponds to the device that is exchanged on the common connection line when a signal is input from the common line to the device. At least one of the input conversion units for converting the signal level into the signal level in the device.
[Selection] Figure 1

Description

  The present invention relates to an interface circuit and a circuit system using the interface circuit.

Conventionally, it is difficult to connect devices having a plurality of interface voltages, and the interface voltage is set according to a device for which the interface power supply voltage cannot be lowered for the reason of characteristics. Conversely, even for a device that can lower the interface voltage for characteristics reasons, it must match the interface voltage of the device to which it is connected, and the interface voltage cannot be actively reduced.
JP 2003-203044 A JP 2000-235441 A JP 2005-117628 A

  In other words, when considering a system in which various devices are connected to each other, the interface voltage cannot be lowered according to the characteristics of each device, and the interface voltage must be adjusted to the voltage of the device that cannot be lowered. It was.

  Therefore, although the core voltage inside the device has been lowered in accordance with the advancement of technology and the demand for lower power consumption, the interface voltage has not been lowered relatively. The share of power consumption at the interface has also increased.

  In addition, as the voltage difference between the interface voltage and the core voltage inside the LSI increases, the adverse effect of increasing the influence on device characteristics (operation speed, specifications, etc.) such as transistor manufacturing variations and voltage fluctuations has become apparent. It was.

  An object of the present invention is to provide a technique capable of dynamically absorbing a difference in the interface voltage at the time of signal exchange between the devices even when there is a difference between the interface voltages in the various devices as described above. is there.

  The present invention employs the following means in order to solve the above problems. That is, the present invention provides an interface circuit interposed between the device and the common connection line when a plurality of devices send and receive signals through the common connection line, and the device connects the common connection line to the common connection line. At the time of signal output, an output conversion unit that converts the signal level in the device to a signal level corresponding to the device exchanged by the common connection line, and at the time of signal input from the common connection line to the device, It is an interface circuit including at least one of input conversion units for converting a signal level transmitted and received through the common connection line into a signal level in the device.

Further, the present invention provides a plurality of devices, a common connection line connecting the devices, and an interface interposed between the device and the common connection line when the device transmits and receives signals through the common connection line. A control circuit for controlling a circuit, and each of the devices has the interface circuit, and the interface circuit sets a signal level in the device when a signal is output from the device to the common connection line. An output conversion unit for converting the signal level to a level corresponding to a device transmitted / received by the common connection line; and a signal level transmitted / received by the common connection line when the signal is input from the common connection line to the device. It may be a circuit system having at least one of input conversion units for converting the signal level into the internal signal level.

  According to the present invention, even when there is a difference between interface voltages in various devices, the difference in the interface voltage can be dynamically absorbed when signals are transmitted between the devices.

  Hereinafter, a circuit system according to the best mode for carrying out the present invention (hereinafter referred to as an embodiment) will be described with reference to the drawings. The configuration of the following embodiment is an exemplification, and the present invention is not limited to the configuration of the embodiment.

<Outline of invention>
This circuit system is configured by connecting various devices that process signals whose voltage levels and interface standards do not match each other to a bus. In the devices included in the circuit system, the input interface and / or the output interface dynamically match the signals with the standards of both interfaces at the timing when signals are exchanged with other devices through the bus.

  FIG. 1 shows a basic configuration of the circuit system. This circuit system includes a bus 1 (corresponding to a common connection line of the present invention), various devices 2A-2D connected to the bus 1, whether or not various devices 2A-2D can be connected to the bus 1, and signals at the time of connection. And a control circuit 3 for controlling the conversion.

In FIG. 1, the type of bus 1 is not limited. For example, USB (Universal Serial Bus
), Fiber Channel, SSA (Serial Storage Architecture), IEEE 1394, and other buses constituting a serial interface. Also, a bus connecting parallel interfaces such as SCSI (Small Computer System Interface), ISA (Industry Standard Architecture), IDE (Integrated Drive Electronics), ATA (AT Attachment), or the like may be used. Further, an internal bus connecting the CPU and the memory may be used.

  The devices 2A-2D are LSIs that exchange signals with the bus 1 and process information based on the signals. The devices 2A to 2D are collectively referred to as device 2. In addition, they are individually referred to as device 2A, device 2B, and the like. However, in the present embodiment, the number of devices 2 is not limited to four. Further, the interface voltage types of the device 2 are not limited to four types.

  The control circuit 3 controls whether or not the device 2 can be connected to the bus 1 and the conversion of the signal at the time of connection by the chip selection signal. Among the devices 2A to 2D, the device 2 that is permitted to be connected to the bus 1 by the chip selection signal of the control circuit 3 is connected to the signal in the device 2 according to the chip selection signal. The signal is converted to a signal matching the above, and the signal is input from the bus 1 or the signal is output to the bus 1. The chip selection signal may be individually provided for each individual device 2. Further, one chip selection signal may be shared with a plurality of devices 2 that process signals simultaneously.

  FIG. 2 is an example of a timing chart of each chip selection signal when a chip selection signal is provided in each device 2. In FIG. 2, each signal indicates a chip selection signal (/ CSA, / CSB, / CSC, / CSD) of the device 2A-2D. When each signal is at the LO level, each device 2 is selected.

  FIG. 3 shows an example of a circuit system in which a plurality of devices 2 having various interface voltages and devices X having switchable interface voltages corresponding to them are connected by a bus 1. In this system, device 2A has a signal interface of 1.8v, device 2B has a signal of 2.5v, device 2C has a signal of 3.3v, and device 2D has a signal interface of 1.2v. Here, the interface voltage is, for example, a voltage that defines the signal amplitude of an amplifier connected to the bus 1.

  In this system, for example, when the device 2A and the device X are connected, the interface of the device X having a voltage of 1.8 V is selected and used. At this time, the devices 2 other than the device 2A and the device X are disconnected from the bus 1. Similarly, when the device 2B and the device X are connected, the 2.5V voltage interface of the device X is selected and used.

  FIG. 4 shows a circuit system in which a plurality of devices 2 having various interface voltages and a device X to which power is supplied to an interface unit from a power supply 4 that supplies switchable voltages corresponding to them are connected by a bus 1. An example of In this example, the interface unit of the device X is provided with an amplifier 5 that converts a signal level. The amplifier 5 is supplied with power from a power supply 4 that can change the power supply voltage. Therefore, for example, when the device 2A and the device X having an interface voltage of 1.8v are connected to the bus 1, the power supply voltage supplied from the power supply 4 is controlled to 1.8v to thereby provide an amplifier for the interface portion of the device X. 5 may be supplied with electric power. The same applies to the other devices 2B-2D.

  FIG. 5A shows a processing procedure for controlling by switching the interface of a device having a plurality of interface voltages. FIG. 5A corresponds to the processing procedure of the control circuit 3 of the circuit system of FIG.

  In this process, the control circuit 3 determines whether or not there are a plurality of interface standards (S1). Here, the interface standard is a first signal system in which a signal value is defined by an upper potential and a lower potential set corresponding to a power supply voltage with reference to a ground potential, that is, 0 v, or a predetermined reference potential And the second signal system in which the signal value is relatively defined by the positive amplitude value in the positive direction and the negative amplitude value in the negative direction from the reference voltage.

  Here, the first signal system is a signal system in which an absolute value from 0v is defined. The second signal system can be said to be a signal system in which positive and negative amplitudes centered on the reference potential are defined. For example, the number of types of these interface standards may be set in a register in the control circuit 3 and referred to by the control circuit 3.

  When there is only one type of interface standard, the control circuit transmits a chip selection signal to the device 2 to be controlled, device X (selected device 2, device X) (S2). At this time, the corresponding interface voltage is set in each device 2 and device X by the chip selection signal. Then, signals are transmitted and received between the selected device 2 and device X (S3).

  When the interface standard is 2 or more, the control circuit transmits a chip selection signal and an interface selection signal corresponding to the chip selection signal to the device 2 to be controlled, device X (selected device 2, device X) (S4). ). At this time, the corresponding interface standard and interface voltage are set in each device 2 and device X by the chip selection signal. Then, signals are transmitted and received between the selected device 2 and device X (S5).

  Even when the interface standard is 2 or more, the interface selection signal from the control circuit is not required if the standard used between the devices selected by the chip selection signal can be fixed. In that case, a circuit for selecting an interface standard corresponding to the combination of interfaces may be incorporated in each device. For example, it is assumed that devices A and B are both the first standard and device C is the second standard. In this case, if the connection between the devices A and B is selected, the interface of the first standard is selected, and the connection between the devices A and C is provided with a selection circuit for selecting the interface of the second standard. Good.

  FIG. 5B shows a processing procedure of the control circuit 3 in a circuit system in which power is supplied to the interface unit from the power supply 4 that supplies a switchable voltage. FIG. 5A corresponds to the processing procedure of the control circuit 3 of the circuit system of FIG.

  In this process, the control circuit 3 first transmits a chip selection signal to the target device 2, the device X, etc., and the power supply 4 (S11). Then, the power supply 4 controls the power supply voltage to be supplied to a value corresponding to the type of the chip selection signal (S12).

  Next, the control circuit 3 determines whether or not there are a plurality of interface standards (S13). When the interface standard is one type, signals are transmitted and received between the device 2 and the device X selected in S11 (S14). That is, in this case, the interface voltage is changed as the power supply voltage is changed, and it is not necessary to control each device 2.

  When the interface standard is 2 or more, the control circuit transmits an interface selection signal corresponding to the chip selection signal to the device 2 to be controlled, the device X (the device 2 selected in S11 or the device X). As a result, the interface method is switched (S15). Then, signals are transmitted and received between the selected device 2 and device X (S16).

<< First Embodiment >>
A circuit system according to a first embodiment of the present invention will be described with reference to FIGS. 6A and 6B. FIG. 6A is a configuration diagram of the output interface unit IF1 (corresponding to the interface circuit of the present invention) of the circuit system. The output interface unit IF1 is interposed between the internal circuit of the device 2 and the bus 1, and converts the signal level output from the device 2 to the bus 1 into a signal level corresponding to the counterpart device that transmits and receives signals.

  A feature of this circuit system is that it has a power supply 4 (also referred to as a voltage supply source) whose supply voltage is variable. All chip selection signals are input to the power supply 4 from the control circuit 3 (see FIG. 4). The power supply 4 changes the power supply voltage according to the type of the asserted chip selection signal. Therefore, the supply voltage is changed according to the device (pair) selected by the control circuit 3 and accessing the bus 1.

  6A includes an internal logic terminal DVA to which an output signal from the internal logic is input, an external output unit out that is connected to the bus 1 and outputs a signal to the bus 1, an internal logic terminal DVA, and the external It has a conversion circuit (corresponding to the output conversion unit of the present invention) for converting a signal with the output terminal out. The conversion circuit includes an inverter IV1 that inverts the signal of the internal logic terminal DVA, three P-channel transistors PM1 to PM3, and three N-channel transistors NM1 to NM3.

Among these transistors, the transistors PM1 and PM2 are both connected at the source to the power supply 4 and connected to the other gate at their drains to constitute a flip-flop FF1. The drain of the transistor PM1 is connected to the ground potential via the drain and source of the transistor NM1. The gate of the transistor NM1 is connected to the internal logic terminal DVA via the inverter IV1. The drain of the transistor PM2 is connected to the ground potential via the drain and source of the transistor NM2. The gate of the transistor NM2 is connected to the internal logic terminal DVA. The transistors PM3 and NM3 are connected in a complementary manner to constitute a CMOS inverting amplifier AMP1. AMP1 is also called an output driver.

  An output signal is output from the internal logic of the device 2 to the internal logic terminal DVA. Hereinafter, the operation of the output interface IF1 will be described. FIG. 6B is a timing diagram of signals of the output interface IF1. In FIG. 6B, the time change of the signal at the output voltage VIF of the power supply 4, the internal logic terminal DVA, and the external output terminal out is shown.

  As shown in FIG. 6B, the power supply voltage of the power supply 4 changes like, for example, VIFB, VIFA, and VIFC. On the other hand, a pulse waveform signal in which the LO level is VSS and the HI level is VDDI is input to the internal logic terminal DVA.

  Here, when the internal logic terminal DVA is at the LO level, it is inverted by the inverter IV1, the gate of the transistor NM1 becomes the HI level, and the transistor NM1 is turned on. Then, the drain of the transistor PM1 and the gate of the transistor PM2 are both at the LO level, and the transistor PM2 is turned on.

  On the other hand, since the gate of the transistor NM2 is at the LO level, the transistor NM2 is turned off. Accordingly, the drain of the transistor PM2, which is the output terminal of the flip-flop circuit FF1, (the drain of the transistor NM2) is at the HI level. The signal at the output terminal of the flip-flop circuit FF1 is inverted and output by the inverting amplifier AMP1.

  Therefore, when the internal logic terminal DVA is at the LO level, the external output terminal is at the LO level. Similarly, when the internal logic terminal DVA is at the HI level, the external output terminal is at the HI level.

  The power supply voltages of the flip-flop circuit FF1 and the inverting amplifier AMP1 are variable between VIFA and VIFC according to the control signal from the control circuit 3. Therefore, the output interface unit IF1 dynamically determines the signal level of the signal input to the internal logic terminal DVA, that is, the amplitude of the counterpart device that is permitted to connect to the bus 1 in accordance with an instruction from the control circuit 3. Can be converted to a signal level that conforms to

  As described above, according to the circuit system of this embodiment, when a signal processed by the internal logic of the device 2 is output to the bus 1, the signal level is dynamically transferred via the bus 1. Can be converted to

<< Second Embodiment >>
A circuit system according to a second embodiment of the present invention will be described with reference to FIGS. 7A and 7B. In the first embodiment, the signal level output from the output interface unit IF1 is converted by the power supply 4 having a variable supply voltage. In this embodiment, an example of a system that converts a signal level by switching a plurality of power supply voltages with a switch will be described. Other configurations and operations of the circuit system are the same as those in the first embodiment. Therefore, the same components are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 7A is a configuration diagram of the output interface unit IF2 of the present circuit system. As shown in FIG. 7A, the sources of the transistors PM1, PM2, and PM3 are connected to the common terminal ND1. Furthermore, the common terminal ND1 is connected to the power supply of the power supply voltage VIFA via the switch SW1. Here, the switch SW1 is composed of, for example, a P-channel transistor, and the chip selection signal / CSA of the device 2A is input to the gate thereof. Therefore, in the present circuit system, when the device 2A is selected, the switch SW1 is turned on, and the power supply voltage VIFA is supplied to the common terminal ND1.

  With the same configuration, when the device 2B is selected in this circuit system, the switch SW2 is turned on, and the power supply voltage VIFB is supplied to the common terminal ND1. With the same configuration, when the device 2C is selected in this circuit system, the switch SW3 is turned on, and the power supply voltage VIFC is supplied to the common terminal ND1. SW1 to SW3 correspond to the power supply switching unit of the present invention.

  Thus, according to the output interface unit IF2 of the present embodiment, the power supply voltage supplied to the common terminal ND1 can be controlled in accordance with the chip selection signal from the control circuit 3. Accordingly, as in the case of the first embodiment, the output interface unit IF2 dynamically changes the signal level of the signal input to the internal logic terminal DVA, that is, the amplitude, in response to an instruction from the control circuit 3, to the signal transmission / reception partner device. It can be converted to a corresponding signal level. FIG. 7B shows a timing diagram of the interface unit IF2.

  In this way, the interface unit IF2 also functions in the same manner as the interface unit IF1 of the first embodiment. Therefore, according to the circuit system of this embodiment, when a signal processed by the internal logic of the device 2 is output to the bus 1, the signal level is dynamically changed to a signal corresponding to the counterpart device that is exchanged on the bus 1. Can be converted to a level.

<< Third Embodiment >>
A circuit system according to a third embodiment of the present invention will be described with reference to FIGS. 8A and 8B. The first embodiment and the second embodiment show examples of the output interface units IF1 and IF2 that convert the signal to the signal level of the bus 1 when the signal processed by the internal logic of the device 2 is output to the bus 1. It was. In the present embodiment, at a timing controlled by the control circuit 3, a signal having a signal level and signal system different from those of the internal logic of the device 2 is input from the bus 1, and a signal level and signal that can be processed by the internal logic of the device 2. An example of the input interface unit IF3 for conversion to the above method will be described. In this circuit system, as in the first embodiment, a power supply 4 (voltage supply source) whose supply voltage is variable is provided in the system.

  FIG. 8A is a configuration diagram of the input interface unit IF3 of the present embodiment, and FIG. 8B is a timing diagram showing signals at each terminal. As shown in FIG. 8A, the input interface unit IF3 includes an input terminal in connected to the bus 1 (see FIG. 3), a differential amplifier AMP3 connected to the input terminal in, and a stage subsequent to the differential amplifier AMP3. Inverting amplifier AMP4 connected, and inverter IV3 connected to input terminal in in parallel with differential amplifier AMP3, and IV4 connected to the next stage of IV3 are included. Both the output signal of the inverting amplifier AMP4 and the output signal of the inverter IV4 are connected to the internal logic terminal DVX connected to the internal logic of the device 2.

  The differential amplifier AMP3 includes N-channel transistors NM4 and NM5 that form a comparison circuit, P-channel transistors PM4 and PM5 that connect the drains of the transistors NM4 and NM5 to the power supply 4, and the sources of the transistors NM4 and NM5, respectively. An N-channel transistor NM6 connected to the ground potential is included.

  The gate of the transistor NM4, which is one input of the comparison circuit, is connected to the input terminal in. The gate of the transistor NM5, which is the other input of the comparison circuit, is connected to the reference potential vref. Further, the gates of the transistors PM4 and PM5 are both connected to the drain of the transistor NM5.

  Further, the sources of the transistors NM4 and NM5 of the comparison circuit are connected to the ground potential via the drain and source of the N-channel transistor NM6, and a signal obtained by inverting the signal of the control terminal IFSW is connected to the gate of the transistor NM6. Entered. Therefore, when the control terminal IFSW is at the HI level, the transistor NM6 is turned off, and the differential amplifier AMP3 including the comparison circuit is cut off. On the other hand, when the control terminal IFSW is at the LO level, the transistor NM6 is turned on, and the differential amplifier AMP3 including the comparison circuit operates.

  The operation of the differential amplifier AMP3 (corresponding to the signal system conversion unit of the present invention) having such a configuration in the operating state will be described. When the potential of the input terminal in is higher than the reference potential vref, more current flows through the transistor NM4 than through the transistor NM5, and the drain of the transistor NM4 is at the LO level. At this time, the drain of the transistor NM5 rises and the current flowing through the transistors PM4 and PM5 connected to the power supply 4 decreases.

  On the other hand, when the potential of the input terminal in is lower than the reference potential vref, more current flows through the transistor NM5 than through the transistor NM4, and the drain of the transistor NM5 is at the LO level. As a result, the current flowing through the transistors PM4 and PM5 connected to the power supply 4 increases, and the drain potential of the transistor NM4 increases. As described above, the output of the differential amplifier AMP3 is switched between the LO level and the HI level depending on the difference value between the potential of the input terminal “in” and the reference potential vref.

Therefore, when the signal input to the input terminal “in” is an SSTL standard signal, the signal can be converted to the signal level of the internal logic (full amplitude between the power supply voltages VDDI and VSS).
In this embodiment, the SSTL (Stub Series terminated Transceiver Logic, corresponding to the second signal system of the present invention) standard signal and the LVTTL (Low Voltage Transistor Transistor Logic, corresponding to the first signal system of the present invention) standard are used. It is a circuit that assumes the signal. here,
The SSTL standard signal is a standard signal in which a potential higher than a reference potential by a predetermined value or more is defined as an HI level, and a potential lower than the reference potential by a predetermined value or more is defined as an LO level. The LVTTL standard signal is a so-called full-amplitude signal, and a signal level equal to or higher than a predetermined value corresponding to the power supply voltage with respect to the ground potential 0v is defined as the HI level. In addition, a signal level equal to or lower than a predetermined value corresponding to the ground potential (or negative power supply voltage) is defined as the LO level.

  The inverting amplifier AMP4 inverts and amplifies the output of the differential amplifier AMP3 and outputs it to the internal logic terminal DVX. However, as shown in FIG. 8A, in the inverting amplifier AMP4, a P-channel transistor and an N-channel transistor are complementarily coupled with CMOS (Complementary Metal-Oxide Semiconductor), and P-channel transistors PM7 and PM8 are cascade-coupled. Two N-channel transistors NM7 and NM8 are cascade-coupled. The signal of the control terminal IFSW is input to the gate of one P-channel transistor PM7. Further, the signal of the control terminal IFSW is inverted and input to the gate of one N-channel transistor NM7 by the inverter IV2. Therefore, when the control terminal IFSW is at the HI level, the inverting amplifier AMP4 is cut off. On the other hand, when the control terminal IFSW is at the LO level, the inverting amplifier AMP4 operates.

  The power supply voltage of the differential amplifier AMP3 is supplied with, for example, the voltage VIFA from the voltage variable power supply 4 in the circuit system outside the chip of the device 2. VIFA is set to a voltage VIFA corresponding to the input SSTL. On the other hand, the inverting amplifier AMP4 is driven by the voltage VDDI corresponding to the level of the signal processed by the internal logic of the device 2.

  Further, for example, the signal of the control terminal IFSW is output as HI level when another device 2B or 2C is selected, and as L when the device 2A and its counterpart device 2D shown in FIG. 8A are selected. It can be configured with a circuit.

  The operation of the inverting amplifier AMP4 having such a configuration is as follows. That is, when VDDI is equal to or lower than VIFA, the maximum amplitude is converted to the level of the signal processed by the internal logic of the device 2 by inverting the signal to the power supply voltage VDDI in the inverting amplifier AMP4. . On the other hand, when VDDI is higher than VIFA, the signal is amplified to the power supply voltage VDDI in the inverting amplifier AMP4, whereby the maximum amplitude is converted to the level of the signal processed by the internal logic of the device 2.

  Of the inverters IV3 and IV4 connected in two stages, for example, the voltage VIFB (or VIFC) is supplied from the voltage variable power supply 4 as the power supply voltage of the first-stage inverter IV3. The power supply voltage of the second stage inverter IV4 is driven by the voltage VDDI corresponding to the level of the signal processed by the internal logic of the device 2. Therefore, similarly to the differential amplifier AMP3 and the inverting amplifier AMP4, the maximum amplitude of the signal input to the input terminal in is also converted by the inverters IV3 and IV4 connected in two stages. In the case of the inverters IV3 and IV4, a signal input in accordance with the LVTTL standard is directly output to the internal logic terminal DVX with the amplitude of the voltage VDDI-VSS corresponding to the signal level processed by the internal logic.

  Note that if the types of signals are not mixed, such as an SSTL standard signal and an LVTTL standard signal, it is not necessary to switch IFSW, and only one of the upper and lower sides of the input interface IF3 in FIG. .

  FIG. 9A shows a first embodiment of a vref circuit that generates a reference voltage. In FIG. 8A, the power supply voltage of the differential amplifier AMP3 that is dynamically set is set equal to the VIF in FIG. 9A. In this case, for example, as shown in FIG. 9A, the power supply voltage VIF may be divided into two by a resistor to generate vref. Further, as shown in FIG. 9B, instead of the resistor, vref may be generated by controlling the gate potential of the transistor and dividing the power supply voltage VIF into two according to the conductive state.

  The above operation is shown in the timing diagram of FIG. 8B. FIG. 8B shows a time change of signals of the control terminal IFSW, the input terminal in, and the internal logic terminal DVX. When IFSW is at the LO level (VSS in FIG. 8B), the differential amplifier AMP3 and the inverting amplifier AMP4 operate to allow the SSTL signal to be input and to convert the signal amplitude. In addition, when IFSW is at the HI level (VIF in FIG. 8B), the inverters IV3 and IV4 operate, and an LVTTL standard signal can be input, and the signal amplitude is converted. The differential amplifier AMP3 and the inverting amplifier AMP4 of the present invention correspond to the input conversion unit of the present invention. Inverters IV3 and IV4 correspond to the input conversion unit of the present invention.

<< 4th Embodiment >>
A circuit system according to a fourth embodiment of the present invention will be described with reference to FIGS. 10A and 10B. In the third embodiment, as in the first embodiment, the power supply voltage provided in the circuit system and having a variable supply voltage is used to control the power supply voltages of the differential amplifier AMP3 and the inverter IV3. The example of the input interface unit IF3 that inputs a signal from the bus 1 in which the signal level and the signal system change and converts the signal to a signal level and a signal system that can be processed by the internal logic of the device 2 has been described. In this embodiment, instead of the power supply 4 having a variable supply voltage, the signal level is converted by switching a plurality of power supply voltages with a switch, as in the second embodiment, and the signal of the bus 1 is converted to the internal logic of the device 2. The input interface unit IF4 for converting to a signal level and a signal system that can be processed in the above will be described. Other configurations and operations of the present embodiment are the same as those of the third embodiment. Therefore, the same components are denoted by the same reference numerals and the description thereof is omitted.

  FIG. 10A is a configuration diagram of the input interface unit IF4 of the present embodiment, and FIG. 10B is a timing diagram showing signals at each terminal.

  As shown in FIGS. 10A and 10B, the power supply voltages of the differential amplifier AMP3 and the inverting amplifier AMP4 are switched between VIFA and VIFD in accordance with the chip selection signals / CSA to / CSD, as in the third embodiment. The signal conversion process is realized.

<< 5th Embodiment >>
A circuit system according to a fifth embodiment of the present invention will be described with reference to FIGS. 11A and 11B. As shown in FIGS. 11A and 11B, in this embodiment, the highest power supply voltage among the power supply voltages that can be selected in the circuit system is set to the output interface unit IF5 as compared with the configurations of the first to fourth embodiments. , And supplied to the back gate of the P-channel transistor of IF6. With such a configuration, even when the power supply voltage of each P-channel transistor is variably controlled, the reverse bias between the substrate (N-type region) and the source and drain (P-type region) is secured in all P-channel transistors. .

  Similarly, the lowest voltage among the negative side power supply voltages may be supplied to the back gate by the N-channel transistor. However, since the lowest voltage of the negative side power supply voltage is usually the ground potential, in this case, the back gate of the N-channel transistor may be grounded.

  With the configuration as described above, even when a plurality of power supply voltages are switched and controlled in the circuit system, the reverse bias between the P-type region and the N-type region of each device 2 can be guaranteed, and stable operation is realized. Such a configuration can be applied to any of the first to fourth embodiments.

<< 6th Embodiment >>
A circuit system according to a sixth embodiment of the present invention will be described with reference to FIGS. 12A to 12D. FIG. 12A is a configuration diagram of the circuit system of the present embodiment. In the present embodiment, in addition to the configurations of the first to fifth embodiments, a cutoff switch is provided between the bus 1 and each device 2.

  FIG. 12C shows the function of the cutoff switch. Here, it is assumed that the output interface unit of the device 2 has a power supply voltage of 1.8 v, a ground potential of 0 v, and is disconnected from the bus 1 in a high impedance state. In this case, for example, by setting the gate of the P-channel transistor to the HI level (for example, 1.8 v) and the gate of the N-channel transistor to the LO level (for example, 0 v) with the CMOS inverter of the output interface unit, the device 2 Can be disconnected from the bus 1.

However, in this state, when a signal having a HI level of, for example, 3.3v propagates to the bus 1, the HI level of the signal propagating through the bus 1 is higher than the gate potential of the P-channel transistor. , The P-channel transistor may turn on and current may flow. Even in such a case, the device 2 can be reliably disconnected from the bus 1 by providing the cutoff switch 6 as shown in FIG. 12C.

FIG. 12D shows the configuration of the cutoff switch. The cutoff switch 6 is configured, for example, by connecting a P-channel transistor and an N-channel transistor in parallel. Then, the chip selection signal / CS # of device 2 (for example, / CSA for device A) is applied to the gate of the P channel transistor (selected at the LO level). On the other hand, an inverted signal (HI level) of the chip selection signal / CS # of device 2 is applied to the gate of the N channel transistor. Thus, when the chip of device 2 is selected, both the two transistors are turned on, and device 2 is connected to bus 1.

  On the other hand, when the chip of device 2 is not selected, both the two transistors are turned off, and device 2 is connected to bus 1. However, the HI level when the chip selection signal / CS # is not selected is set to a voltage equal to the highest interface voltage among the devices 2 currently connected to the bus 1 in the circuit system.

  That is, the power supply voltage of the device having the highest HI level interface voltage among the devices connected to the bus 1 is applied to the gate of the P-channel transistor. The power supply voltage having the highest interface voltage is also applied to the back gate of the P channel transistor. On the other hand, the power supply voltage (for example, ground potential) of the lowest interface voltage at the LO level among the devices connected to the bus 1 is applied to the back gate of the N channel transistor. As a result, it is possible to prevent inflow of current as shown by the dotted arrow in FIG. 12C for all the non-selected devices 2 connected to the bus 1.

  In the example of FIG. 12A, among the devices 2 connected to the bus 1, the device 2C is operating at the highest interface voltage 3.3v. Therefore, in this case, the chip selection signal is used at 3.3v. In addition, since the device 2C having the highest interface voltage 3.3v has no possibility of current flowing when not selected, it is not necessary to provide the cutoff switch 6.

  FIG. 12B shows an example of a system in which the devices 2C and 2D are not connected to a signal on the bus 1. For example, it is assumed that the devices 2C and 2D exchange data with respect to other signals. In this case, among the devices connected to the bus 1 for the signal, the device 2B operates at the highest interface voltage 2.5v. Therefore, a cut-off switch may be provided in the device 2A connected to the bus 1 with an interface voltage 1.8v lower than this voltage.

<< 7th Embodiment >>
A circuit system according to a seventh embodiment of the present invention will be described with reference to FIGS. 13A to 14B. FIG. 13A to FIG. 13C show a configuration when this circuit system is mounted on a package.

  In the present embodiment, a configuration in which a plurality of devices 2 (that is, semiconductor chips) are mounted on one package will be described. In this case, let us consider a case in which one device 2 has a dedicated IF for a specific device and an IF for another device as an interface with a counterpart device that transmits and receives signals.

FIG. 13A is an image diagram of a connection relationship between a pad and a bonding wire. here,
The changeover switch described in the second embodiment, the fourth embodiment, and the fifth embodiment exists in the IO circuit of FIG. 13A. Here, the bonding wire to the counterpart device in the same package and the bonding wire connected to the system bus via the package pin are connected via different pads. FIG. 13B is a cross-sectional image view of the chip. As shown in FIG. 13B, there is a technique in which pads are arranged in an upper layer of an IO circuit. Further, as shown in FIG. 13B, the pad layer has a lower pattern density than the wiring layer, and a sufficient free area exists. Thus, by arranging the pad increase in the circuit system of this embodiment in the area on the IO circuit, it is possible to increase the number of pads while suppressing an increase in chip size. If the pads are arranged in this manner, the size of the IO circuit hardly increases even if pads are separately provided for the in-package device and the system bus outside the package and the bonding wires are connected.

  FIG. 13C shows an example of a circuit system in which a plurality of devices 2 are bundled in one package.

  Normally, when outputting from each pad via separate package pins as shown in FIG. 13B, there is a concern about an increase in the number of package pins. However, in the case of a system configuration in which a plurality of devices are bundled in the same package (referred to as SiP (System in Package), MCP (Muti Chip Package), etc.) due to the configuration of the circuit system of the present embodiment. Since devices can be connected only by bonding wires, the number of package pins can be increased.

  FIG. 14A is a configuration diagram of the interface IF7 of the circuit system. FIG. 14B is a timing diagram showing the time change of the signal level of each terminal. Signals processed by the internal logic of the LO level VSS and the HI level VDDI are input to the internal logic terminal DVA in FIG. 14A. Here, the output interface unit IF7 with a changeover switch in the case where an output driver having a power supply voltage of VDDI and an output driver having another power supply voltage are separately described.

  In FIG. 14A, the configurations and operations of the flip-flop FF1 and the inverting amplifier AMP1 are the same as those in the first embodiment. Therefore, the signal level VDDI in the internal logic circuit is converted into the signal level VIF of the bus 1 by the circuit including the internal logic terminal DVA, the flip-flop FF1, the inverting amplifier AMP1, and the external terminal out2, as in the first embodiment. The external terminal out2 may be configured to be connected to a bonding wire to the system bus in FIG. 13A, for example.

  On the other hand, in a circuit including the internal logic terminal DVA, the inverter IV5, the inverting amplifier AMP5, and the external terminal out1, the signal level VDDI in the internal logic circuit is output as it is. The external terminal out1 may be configured to be connected to a bonding wire to the device 2D in the same package in FIG. 13A, for example.

  In FIG. 14A, when control terminal / CS = L, output to out1 or ou2 is possible. In this case, as shown in FIG. 14B, when the control terminal Output switch = H, the signal to the external terminal out1 (output to the device 2D) is valid. Further, when Output switch = L, the signal to the external terminal out2 (output to the system bus) is valid. In FIG. 14A, when Output switch = H, the inverting amplifier AMP1, which is a level shifter, is also deactivated so that useless current is not consumed.

  Further, when the control terminal / CS = H, both Out 1 and 2 are not selected. In this case, both inverting amplifiers AMP1 and AMP5 are in a high impedance state.

  With the configuration as described above, signal exchange with the counterpart device 2D that does not require signal level conversion may be performed through an output driver without level conversion. Devices in the same package may be able to be realized with the same signal level and signal standard as the device itself. Therefore, by providing such a dedicated output that does not require level conversion, signals can be exchanged at high speed and with low power consumption with a device in the same package that is frequently accessed.

  Further, by providing pads as shown in FIG. 13A, it is possible to suppress an increase in package pins, further suppress the chip size, and provide an interface that performs level conversion and an interface that does not perform level conversion.

<< Eighth Embodiment >>
The interface IF8 of the circuit system according to the eighth embodiment of the present invention will be described with reference to FIGS. 15A and 15B. The circuit system of the present embodiment is further provided with a simultaneous output function for an interface that is not subjected to level conversion to an interface that is subjected to level conversion, in addition to the configuration of the seventh embodiment. Other configurations and operations are the same as those of the seventh embodiment. Therefore, the same components are denoted by the same reference numerals as those in the seventh embodiment, and description thereof is omitted.

  In FIG. 15A, when the control terminal / CS = L, output to out1 or out2 is possible. Then, as shown in FIG. 15B, when the control terminal / both enable = L and output switch = H, the signals are simultaneously output to both out1 and out2. Also, when / both enable = H, out2 (output to the system bus) is valid when output switch = L. Further, when output switch = H, out1 (output to device D) is valid. Furthermore, when output switch = H, the inverting amplifier AMP1, which is a level shifter, is deactivated so that useless current is not consumed. Further, when the control terminal / CS = L, both Out1 and Out2 are not selected. In this case, both inverting amplifiers AMP1 and AMP5 are in a high impedance state.

<< Ninth Embodiment >>
The interface IF9 of the circuit system according to the ninth embodiment of the present invention will be described with reference to FIGS. 16A and 16B. The circuit system of the present embodiment is similar to the second embodiment, instead of having a power supply 4 (voltage supply source) whose supply voltage is variable in the system as in the first embodiment or the seventh embodiment. The signal level is switched by switching a plurality of power supply voltages with a switch. Other configurations and operations are the same as those of the seventh embodiment. Therefore, the same components are denoted by the same reference numerals as those in the seventh embodiment, and description thereof is omitted.

  In FIG. 16A, when control terminal / CS = L, output to out1 or out2 is possible. As shown in FIG. 16B, out1 (output to the device 2D) is valid when the control terminal Output switch = H. Also, when Output switch = L, out2 (output to the system bus) is valid. Furthermore, when Output switch = H, the level shifter is also deactivated so that useless current is not consumed.

  Further, when the control terminal / CS = H, both Out 1 and 2 are not selected. In this case, both inverting amplifiers AMP1 and AMP5 are in a high impedance state. As with the second embodiment, the power supply voltage is switched between VIFA / B by Pswitch (example of VIFA ≦ VIFB). When Pswitch = H, the signal is output at the VIFA signal level. When pswitch = L, the signal is output at the VIFB signal level.

<< 10th Embodiment >>
The interface IF10 of the circuit system according to the eighth embodiment of the present invention will be described with reference to FIGS. 17A and 17B. The circuit system of this embodiment is provided with a simultaneous output function for the interface to which level conversion is performed and the interface to which level conversion is not performed in addition to the configuration of the ninth embodiment. Other configurations and operations are the same as those of the ninth embodiment. Therefore, the same constituent elements are denoted by the same reference numerals as those in the ninth embodiment, and the description thereof is omitted.

  In FIG. 17A, when the control terminal / CS = L, output to out1 or out2 is possible. Then, as shown in FIG. 17B, when the control terminal / both enable = L and output switch = H, the signals are output simultaneously to both out1 and out2. When / both enable = H, out2 (output to the system bus) becomes valid when output switch = L. Also, when output switch = H, out1 (output to device D) is valid. Further, when output switch = H, the inverting amplifier AMP1, which is a level shifter, is deactivated so that useless current is not consumed.

  Further, when the control terminal / CS = H, both Out 1 and 2 are not selected. In this case, both inverting amplifiers AMP1 and AMP5 are in a high impedance state.

<< 11th Embodiment >>
The interface IF11 of the circuit system according to the eleventh embodiment of the present invention will be described with reference to FIGS. 18A and 18B. In the present embodiment, a circuit system having an input interface that does not convert a signal standard with respect to the configuration of the third embodiment will be described.

  That is, in FIG. 18A, the circuit including the external terminal in2 and the inverters IV7 and IV8 is an input circuit that does not convert the signal standard. On the other hand, the external terminal in1, the differential amplifier AMP3, and the inverting amplifier AMP4 are circuits that convert a signal of the SSTL standard into a signal level inside the logic, and are the same as those described in the third embodiment.

  As shown in FIG. 18B, in1 (input of deviceD) is valid when IFSW = H. When IFSW = L, in2 (system bus signal input) is valid.

<< Twelfth Embodiment >>
The interface IF12 of the circuit system according to the twelfth embodiment of the present invention will be described with reference to FIGS. 19A and 19B. In the present embodiment, an input interface unit with a changeover switch in the case of separately having a VDDI potential input circuit and another voltage input circuit is shown. This embodiment is different from the eleventh embodiment in that signal transmission / reception with the device 2D in the same package is performed by LVTTL.

  As shown in FIG. 19B, in1 (input of deviceD) is effective when IFSW = H. When IFSW = L, in2 (system bus signal input) is valid.

<< 13th Embodiment >>
A circuit system according to a thirteenth embodiment of the present invention will be described with reference to FIGS. 20A and 20B. In the present embodiment, an example of a circuit system having an input / output circuit that converts a signal level in both an input interface and an output interface will be described.

In FIG. 20A, a circuit block IF13 indicates an output interface. The configurations and operations of the flip-flop FF1 and the inverting amplifier AMP1 in the circuit block IF13 are the same as those in the first embodiment. The circuit block IF14 indicates an input interface. The configurations and operations of the differential amplifier AMP3 and the inverting amplifier AMP4 in the circuit block IF14 are the same as those in the third embodiment.

  As shown in FIG. 20B, output is possible when OE (Output enable) = H. When OE = L, input is possible. When OE = L, n01 = H and n02 = L, and the output driver side is in a high impedance state and does not disturb the input signal.

<< System design in this embodiment >>
FIG. 21 shows a design flowchart when designing the circuit system of the present embodiment. In this design, first, it is determined whether or not a combination of devices for transmitting and receiving data is known (S21). If the combination of devices is not known, data transmission / reception between devices is designed (S22).

  If the device combination is known, the magnitude relationship between the device combination and the interface voltage is clearly indicated (S23). Then, it is determined whether or not the power supply variable method is based on switching (S24).

  When the power supply variable method is switching, the IO part of the device is designed (S25). Next, it is determined whether there is one type of interface standard (S26). If there is only one type of interface standard, a switch is provided and one type of interface circuit corresponding to the standard is designed (S27). On the other hand, when there are two or more types of interface standards, a switch is provided and the number of corresponding types of interface circuits corresponding to the standards is designed (S28).

  If the power supply variable method is not switching, a variable power supply is arranged in the circuit system (S29). Then, the IO unit of the device is designed (S30). Next, it is determined whether there is one type of interface standard (S31). When there is one type of interface standard, one type of interface circuit corresponding to the standard is designed (S32). On the other hand, when there are two or more types of interface standards, the number of corresponding types of interface circuits corresponding to the standards is designed (S33).

<< Effects of the Embodiment >>
It can be used in a system that is configured by mounting various types of devices such as digital, analog, and multiple types of memories, and the choice of devices can be expanded. For devices that can reduce the interface voltage, it is effective to reduce the power consumption at the interface by producing a device with a low interface voltage and applying this system. In particular, if the interface voltage related to a signal with a large number of buses (memory interface, etc.) can be lowered, the effect of reducing power consumption is great. In addition, the bus can be shared by a plurality of signals, and the bus resources can be reduced. Furthermore, the possibility of suppressing the deterioration of characteristics caused by the voltage difference between the core voltage inside the LSI and the interface voltage can be expected.

<Others>
The present embodiment includes the following aspects of the invention (hereinafter referred to as supplementary notes).
(Appendix 1)
When a plurality of devices send and receive signals through a common connection line, an interface circuit interposed between the device and the common connection line,
An output converter that converts a signal level in the device to a signal level corresponding to a device that is exchanged on the common connection line when a signal is output from the device to the common connection line; and An interface circuit comprising at least one of input conversion units for converting a signal level corresponding to a device exchanged with the common connection line into a signal level in the device when a signal is input to the device. (1)
(Appendix 2)
The interface according to appendix 1, wherein the output conversion unit and the input conversion unit include a switch unit that connects the device to the common connection line according to a predetermined selection signal, or shuts off the common connection line and the device. circuit. (2)
(Appendix 3)
The output conversion unit and the input conversion unit are connected to any one of an amplifier circuit and two or more power supplies that supply two or more drive voltages to the amplifier circuit, respectively. The interface circuit according to appendix 1 or 2, including a power supply switching unit that is cut off from the amplifier circuit. (3)
(Appendix 4)
The interface circuit includes a first signal system in which a signal value is defined by an upper potential and a lower potential set with reference to a ground potential, a positive amplitude value in a positive direction from a predetermined reference potential, and a negative value from the reference voltage. 4. The interface circuit according to any one of appendices 1 to 3, further comprising a signal system conversion unit that converts a signal value with a second signal system in which the signal value is defined by a negative amplitude value of the direction. (4)
(Appendix 5)
Multiple devices,
A common connection line connecting the devices;
A control circuit that controls an interface circuit interposed between the device and the common connection line when the device transmits and receives a signal through the common connection line;
Each of the devices has the interface circuit,
The interface circuit is
An output converter that converts a signal level in the device to a signal level corresponding to a device that is exchanged on the common connection line when a signal is output from the device to the common connection line; and A circuit system having at least one of input conversion units for converting a signal level corresponding to a device exchanged with the common connection line into a signal level in the device when a signal is input to the device. (5)
(Appendix 6)
The circuit system according to appendix 5, wherein the control circuit includes a selection signal output unit that outputs the signal to the common connection line or selects a device that inputs the signal from the common digital line.
(Appendix 7)
The circuit system according to appendix 6, wherein the output conversion unit and the input conversion unit include a switch unit that connects the device to the common connection line or cuts off the common connection line and the device according to the selection signal. .
(Appendix 8)
The output conversion unit and the input conversion unit are connected to any one of an amplifier circuit and two or more power supplies that supply two or more drive voltages to the amplifier circuit, respectively. The interface circuit according to appendix 6 or 7, including a power supply switching unit, which is cut off from the amplifier circuit.
(Appendix 9)
The circuit system according to appendix 4, wherein the interface circuit includes an amplifier driven by a power source whose output voltage is controlled according to a control signal from the control circuit.
(Appendix 10)
The interface circuit includes a first signal system in which a signal value is defined by an upper potential and a lower potential set with reference to a ground potential, a positive amplitude value in a positive direction from a predetermined reference potential, and the reference voltage. The circuit system according to any one of appendices 5 to 9, further including a signal system conversion unit that converts the signal value between the second signal system in which the signal value is defined by the negative amplitude value in the negative direction.
(Appendix 11)
When the output conversion unit includes a P channel transistor, the highest power supply voltage among the power supply voltages provided corresponding to the plurality of signal levels is supplied to the back gate voltage of the P channel transistor. The circuit system according to any one of appendices 5 to 10.
(Appendix 12)
When the output conversion unit includes an N channel transistor, the back gate voltage of the N channel transistor is the lowest voltage among the negative power supply voltage and the ground potential provided corresponding to the plurality of signal levels. 11. The circuit system according to any one of supplementary notes 5 to 10, wherein:

  The present invention can be effectively used when a system is configured using a plurality of types of semiconductor devices, particularly when a plurality of types of semiconductor devices having different interface voltages are used. In addition, due to advantages such as low power consumption related to data transmission / reception, this technology is actively used to create (low) devices with different interface voltages and configure the system by using them. Can also be used.

It is a figure showing the basic composition of the circuit system concerning the embodiment of the present invention. It is an example of a timing chart of each chip selection signal when a chip selection signal is provided in each device. FIG. 3 is a diagram illustrating an example of a circuit system in which a plurality of devices having various interface voltages and devices having switchable interface voltages corresponding to the devices are connected by a bus. FIG. 3 is a diagram illustrating an example of a circuit system in which a plurality of devices having various interface voltages and devices to which power is supplied to an interface unit from a power supply that supplies switchable voltages corresponding to the devices are connected by a bus. It is a figure which shows the process sequence which switches and controls the interface of the device which has a some interface voltage with a switch. It is a figure which shows the process sequence of the control circuit 3 in the circuit system which supplies electric power to the interface part from the power supply 4 which supplies the voltage which can be switched. It is a block diagram of the output interface part which concerns on 1st Embodiment of this invention. It is a timing diagram of the circuit system of a 1st embodiment. It is a block diagram of the output interface part which concerns on 2nd Embodiment of this invention. It is a timing diagram of the circuit system of a 2nd embodiment. It is a block diagram of the input interface part which concerns on 3rd Embodiment of this invention. It is a timing diagram of the circuit system of a 3rd embodiment. 1 is a diagram illustrating a first embodiment of a vref circuit that generates a reference voltage; FIG. FIG. 6 is a diagram illustrating a second embodiment of a vref circuit that generates a reference voltage. It is a block diagram of the input interface part which concerns on 4th Embodiment of this invention. It is a timing diagram of the circuit system of a 4th embodiment. It is a block diagram of the output interface part which concerns on 5th Embodiment of this invention. It is a timing diagram of the circuit system of a 4th embodiment. It is a block diagram (the 1) of the circuit system which concerns on 6th Embodiment of this invention. It is a block diagram (the 2) of the circuit system which concerns on 6th Embodiment of this invention. It is a figure which shows the function of a cutoff switch. It is a figure which shows the structure of a cutoff switch. It is an image figure of the connection relation of a pad and a bonding wire. It is a section image figure of a chip concerning a 7th embodiment of the present invention. It is a figure which shows the example of the circuit system which bundles the several device 2 in the package which concerns on 7th Embodiment of this invention. It is a block diagram of the circuit system which concerns on 7th Embodiment of this invention. It is a timing diagram of the circuit system of a 7th embodiment. It is a block diagram of the circuit system which concerns on 8th Embodiment of this invention. It is a timing diagram of the circuit system of 8th Embodiment. It is a block diagram of the circuit system which concerns on 9th Embodiment of this invention. It is a timing diagram of the circuit system of 9th Embodiment. It is a block diagram of the circuit system which concerns on 10th Embodiment of this invention. It is a timing diagram of the circuit system of a 10th embodiment. It is a block diagram of the circuit system which concerns on 11th Embodiment of this invention. It is a timing diagram of the circuit system of 11th Embodiment. It is a block diagram of the circuit system which concerns on 12th Embodiment of this invention. It is a timing diagram of the circuit system of 12th Embodiment. It is a block diagram of the circuit system which concerns on 12th Embodiment of this invention. It is a timing diagram of the circuit system of 12th Embodiment. It is a design-time flowchart in the case of designing the circuit system which concerns on embodiment of this invention.

Explanation of symbols

1 Bus 2, 2A, 2B, 2C, 2D Device 3 Control circuit 4 Power supply 5 Amplifier AMP1 Inverting amplifier AMP3 Differential amplifier AMP4 Inverting amplifier FF1 Flip-flop IF1-IF11 Interface circuit IV1, IV2, IV3, IV4, IV5 Inverter PM1, PM2 , PM3 P channel transistors NM1, NM2, NM3 N channel transistors

Claims (5)

When a plurality of devices send and receive signals through a common connection line, an interface circuit interposed between the device and the common connection line,
An output conversion unit that converts a signal level in the device to a signal level transmitted and received by the common connection line when a signal is output from the device to the common connection line; and from the common connection line to the device An interface circuit comprising at least one of input conversion units for converting a signal level transmitted and received through the common connection line into a signal level in the device when a signal is input.   2. The switch according to claim 1, wherein the output conversion unit and the input conversion unit include a switch unit that connects the device to the common connection line or cuts off the common connection line and the device according to a predetermined selection signal. Interface circuit.   The output conversion unit and the input conversion unit are connected to any one of an amplifier circuit and two or more power supplies that supply two or more drive voltages to the amplifier circuit, respectively. The interface circuit according to claim 1, further comprising a power supply switching unit that is cut off from the amplifier circuit.   The interface circuit includes a first signal system in which a signal value is defined by an upper potential and a lower potential set with reference to a ground potential, a positive amplitude value in a positive direction from a predetermined reference potential, and a negative value from the reference voltage. 4. The interface circuit according to claim 1, further comprising: a signal system conversion unit that converts a signal value with a second signal system in which a signal value is defined by a negative amplitude value of a direction. 5. Multiple devices,
A common connection line connecting the devices;
A control circuit that controls an interface circuit interposed between the device and the common connection line when the device transmits and receives a signal through the common connection line;
Each of the devices has the interface circuit,
The interface circuit is
An output conversion unit that converts a signal level in the device to a signal level transmitted and received by the common connection line when a signal is output from the device to the common connection line; and from the common connection line to the device A circuit system having at least one of input conversion units for converting a signal level transmitted and received through the common connection line into a signal level in the device when a signal is input.

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