JPH07147321A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07147321A JPH07147321A JP29649393A JP29649393A JPH07147321A JP H07147321 A JPH07147321 A JP H07147321A JP 29649393 A JP29649393 A JP 29649393A JP 29649393 A JP29649393 A JP 29649393A JP H07147321 A JPH07147321 A JP H07147321A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact holes
- conductor film
- conductor
- interlayer insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000004065 semiconductor Substances 0.000 title claims description 27
- 239000004020 conductor Substances 0.000 claims abstract description 49
- 239000011229 interlayer Substances 0.000 claims abstract description 25
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 23
- 239000010937 tungsten Substances 0.000 claims abstract description 23
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 21
- 125000006850 spacer group Chemical group 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 29
- 238000005530 etching Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 21
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 description 11
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical compound [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 150000003657 tungsten Chemical class 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にコンタクト孔を充填する導電体膜の形成方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a conductor film filling a contact hole.
【０００２】[0002]
【従来の技術】半導体装置の微細化が進むにつれて、配
線層が多層化されている。これに伴ない、異なる配線層
を接続するためのコンタクト孔の種類も増え、かつ、こ
れらのコンタクト孔の口径もそれぞれ小さくなってい
る。これらのコンタクト孔内にスパッタリングのみによ
り導電体膜を充填することは、困難である。この傾向に
対する製造工程の短縮，製造原価の低減の１つとして、
上層の配線層（例えば第３層）から異なる種類の下層の
配線層（例えば第１，および第２層の配線層）への深さ
の異なる（例えば２種類の）コンタクト孔を形成し、こ
れらのコンタクト孔に同時に導電体膜を充填する種々の
方法が提案されている。これらの方法の１つが、特開平
２−３０８５２４号公報に開示されている。2. Description of the Related Art As semiconductor devices have been miniaturized, wiring layers have become multi-layered. Along with this, the types of contact holes for connecting different wiring layers are increasing, and the diameters of these contact holes are decreasing. It is difficult to fill the conductive film in these contact holes only by sputtering. As one of the shortening of the manufacturing process and the reduction of manufacturing cost against this tendency,
Forming contact holes having different depths (for example, two types) from upper wiring layers (for example, third layer) to different types of lower wiring layers (for example, first and second wiring layers), and Various methods have been proposed for simultaneously filling the contact holes with the conductor film. One of these methods is disclosed in JP-A-2-308524.
【０００３】半導体装置の製造工程の断面図である図３
を参照すると、上記公開公報記載の製造方法は、以下の
ようになっている。まず、半導体基板１表面にゲート酸
化膜２を形成し、ゲート酸化膜２上にゲート電極１５を
形成した後、ゲート電極１５の側壁に絶縁膜スペーサ３
を形成する。半導体基板１表面に拡散層４を形成した
後、全面に層間絶縁膜６を形成する。次に、公知のフォ
トリソグラフィ技術により、拡散層４に達する深さの深
いコンタクト孔１７を層間絶縁膜６に形成する〔図３
（ａ）〕。次に、減圧ＣＶＤ法により、全面に多結晶シ
リコン膜を形成する。この多結晶シリコン膜を異方性エ
ッチングすることにより、上記コンタクト孔１７の側壁
に多結晶シリコン膜スペーサ１２を形成する〔図３
（ｂ）〕。続いて、ゲート電極１５に達する深さの浅い
コンタクト孔１８を形成する〔図３（ｃ）〕。次に、タ
ングステンの選択ＣＶＤ法により、コンタクト孔１７，
１８をそれぞれタングステン膜２０により充填する〔図
３（ｄ）〕。FIG. 3 is a sectional view of a manufacturing process of a semiconductor device.
With reference to, the manufacturing method described in the above publication is as follows. First, the gate oxide film 2 is formed on the surface of the semiconductor substrate 1, the gate electrode 15 is formed on the gate oxide film 2, and then the insulating film spacer 3 is formed on the sidewall of the gate electrode 15.
To form. After forming the diffusion layer 4 on the surface of the semiconductor substrate 1, the interlayer insulating film 6 is formed on the entire surface. Next, a contact hole 17 having a depth reaching the diffusion layer 4 is formed in the interlayer insulating film 6 by a known photolithography technique [FIG.
(A)]. Next, a polycrystalline silicon film is formed on the entire surface by the low pressure CVD method. By anisotropically etching this polycrystalline silicon film, a polycrystalline silicon film spacer 12 is formed on the side wall of the contact hole 17 [FIG.
(B)]. Then, a contact hole 18 having a depth reaching the gate electrode 15 is formed [FIG. 3 (c)]. Next, the contact hole 17,
Each 18 is filled with a tungsten film 20 [FIG. 3 (d)].
【０００４】[0004]
【発明が解決しようとする課題】上記公開公報記載の半
導体装置の製造方法は、深さの深いコンタクト孔の側壁
にのみ第１の導電体膜からなるスペーサを形成しておく
ことにより、このコンタクト孔への第２の導電体膜の選
択成長の時間を短縮する。その結果として、深さの異な
るコンタクト孔に、同時に第２の導電体膜を充填するこ
とが可能であるとしている。しかしながら、現実の半導
体装置では、さまざまな深さのコンタクト孔が存在する
ため、深さの異なる全てのコンタクト孔を同時に第２の
導電体膜で充填することは、極めて困難である。そのた
め、これらのコンタクト孔に接続する上層の配線が、こ
れらのコンタクト孔の上端近傍で断線しやすくなる。ま
たこの方法では、コンタクト孔の開口を２度に分けて行
なうため、フォトリソグラフィ工程の回数が増大し、製
造工期が長くなるという問題もある。In the method of manufacturing a semiconductor device described in the above-mentioned publication, the spacer made of the first conductor film is formed only on the side wall of the deep contact hole to form the contact. The time for selective growth of the second conductor film in the holes is shortened. As a result, it is possible to simultaneously fill the contact holes having different depths with the second conductor film. However, in an actual semiconductor device, since contact holes having various depths exist, it is extremely difficult to simultaneously fill all the contact holes having different depths with the second conductor film. Therefore, the upper layer wirings connected to these contact holes are easily broken near the upper ends of these contact holes. Further, in this method, since the contact holes are opened twice, there is a problem that the number of photolithography steps is increased and the manufacturing period is prolonged.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置の製
造方法の第１の態様は、半導体基板の表面からの上面の
高さがそれぞれ異なる複数の種類の配線層を形成し、全
面に層間絶縁膜を形成し、口径が同じでこれらの配線層
の上面に達する深さの異なる複数の種類のコンタクト孔
をこの層間絶縁膜に形成する工程と、全面に第１導電体
膜を形成し、この第１導電体膜を異方性エッチングして
上記層間絶縁膜の上面から所定の深さより下方のそれぞ
れの上記コンタクト孔の側壁にこの第１導電体膜からな
るスペーサを形成する工程と、第２導電体膜の選択成長
を行ない、それぞれの上記コンタクト孔をこの第２導電
体膜で充填する工程とを有する。According to a first aspect of a method for manufacturing a semiconductor device of the present invention, a plurality of types of wiring layers having different heights from the surface of a semiconductor substrate are formed, and an interlayer is formed over the entire surface. A step of forming an insulating film, forming a plurality of types of contact holes having the same diameter and different depths reaching the upper surfaces of these wiring layers in this interlayer insulating film, and forming a first conductor film on the entire surface, Anisotropically etching the first conductor film to form spacers made of the first conductor film on the sidewalls of the contact holes below a predetermined depth from the upper surface of the interlayer insulating film; And a step of selectively growing the two conductor films and filling each of the contact holes with the second conductor film.
【０００６】本発明の半導体装置の製造方法の第２の態
様は、半導体基板の表面からの上面の高さがそれぞれ異
なる複数の種類の配線層を形成し、全面に層間絶縁膜を
形成し、口径が同じでこれらの配線層の上面に達する深
さの異なる複数の種類のコンタクト孔をこの層間絶縁膜
に形成する工程と、全面に第１導電体膜を形成し、それ
ぞれの上記コンタクト孔が充填されるまで全面に第２導
電体膜を成長する工程と、上記第２導電体膜および上記
第１導電体膜を異方性エッチングによりエッチバックし
て、それぞれの上記コンタクト孔における上記層間絶縁
膜の上面から所定の深さまでのこの第１導電体膜を除去
する工程と、第３導電体膜の選択成長を行ない、それぞ
れの上記コンタクト孔をこの第３導電体膜と上記第２導
電体膜とで充填する工程とを有する。好ましくは、上記
第１導電体膜がチタン膜と窒化チタン膜との積層膜から
なり、上記第２，および第３導電体膜がタングステン膜
からなる。According to a second aspect of the method for manufacturing a semiconductor device of the present invention, a plurality of types of wiring layers having different heights from the surface of the semiconductor substrate are formed, and an interlayer insulating film is formed on the entire surface. A step of forming a plurality of types of contact holes having the same diameter and different depths reaching the upper surfaces of these wiring layers in the interlayer insulating film; and forming a first conductor film on the entire surface, A step of growing a second conductor film on the entire surface until it is filled, and etching back the second conductor film and the first conductor film by anisotropic etching to obtain the interlayer insulation in each of the contact holes. The step of removing the first conductor film from the upper surface of the film to a predetermined depth and the selective growth of the third conductor film are performed, and the contact holes are formed in the third conductor film and the second conductor, respectively. Fill with membrane And a step. Preferably, the first conductor film is a laminated film of a titanium film and a titanium nitride film, and the second and third conductor films are a tungsten film.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.
【０００８】半導体装置の製造工程の断面図である図１
を参照すると、本発明の第１の実施例は、以下のように
なっている。FIG. 1 is a sectional view of a manufacturing process of a semiconductor device.
Referring to, the first embodiment of the present invention is as follows.
【０００９】まず、Ｐ型の半導体基板１表面にゲート酸
化膜２を形成し、ゲート酸化膜２上にポリサイドゲート
電極５を形成した後、ポリサイドゲート電極５の側壁に
絶縁膜スペーサ３を形成する。半導体基板１表面にＮ型
の拡散層４を形成した後、全面に層間絶縁膜６を形成す
る。次に、公知のフォトリソグラフィ技術により、拡散
層４に達する深さの深いコンタクト孔７と、ポリサイド
ゲート電極５に達する深さの浅いコンタクト孔８とを層
間絶縁膜６に同時に形成する。コンタクト孔７の口径
は、コンタクト孔８の口径と同じである〔図１
（ａ）〕。First, a gate oxide film 2 is formed on the surface of a P-type semiconductor substrate 1, a polycide gate electrode 5 is formed on the gate oxide film 2, and then an insulating film spacer 3 is formed on a sidewall of the polycide gate electrode 5. Form. After the N type diffusion layer 4 is formed on the surface of the semiconductor substrate 1, the interlayer insulating film 6 is formed on the entire surface. Next, a well-known photolithography technique is used to simultaneously form a deep contact hole 7 reaching the diffusion layer 4 and a shallow contact hole 8 reaching the polycide gate electrode 5 in the interlayer insulating film 6. The diameter of the contact hole 7 is the same as the diameter of the contact hole 8 [Fig.
(A)].
【００１０】次に、ＰＨ3 ，ＳｉＨ4 ガスを用いた温度
５００〜６００℃，圧力６０〜１００Ｐａの減圧ＣＶＤ
法により、全面に第１導電膜であるリンドープド多結晶
シリコン膜９を堆積する。このリンドープド多結晶シリ
コン膜９の膜厚は、コンタクト孔７，８の口径に比べて
薄く、所望の薄さになっている〔図１（ｂ）〕。Next, low pressure CVD using PH 3 and SiH 4 gas at a temperature of 500 to 600 ° C. and a pressure of 60 to 100 Pa.
By the method, the phosphorus-doped polycrystalline silicon film 9 which is the first conductive film is deposited on the entire surface. The film thickness of the phosphorus-doped polycrystalline silicon film 9 is smaller than the diameters of the contact holes 7 and 8 and has a desired thickness [FIG. 1 (b)].
【００１１】続いて、流量比０．３〜０．４のＨＢｒ／
Ｃｌ2 ガスを用いた圧力５０〜７０Ｐａ，パワー２００
〜３００Ｗでのプラズマ異方性エッチングを行ない、コ
ンタクト孔７，８の側壁にのみに、それぞれリンドープ
ド多結晶シリコン膜スペーサ９ａを残置させる。これら
リンドープド多結晶シリコン膜スペーサ９ａの上端は層
間絶縁膜６の上面（コンタクト孔７，８の上端）より低
い。この間隔は所定の値であり、この値はコンタクト孔
７，８の口径の１／２であることが好ましい。上記エッ
チングにおいて、層間絶縁膜６上面のリンドープド多結
晶シリコン膜９が除去された後、さらに所定の時間この
エッチングを続行するすることにより、上記形状のリン
ドープド多結晶シリコン膜スペーサ９ａが得られる〔図
１（ｃ）〕。Subsequently, HBr / with a flow rate ratio of 0.3 to 0.4
Pressure of 50 to 70 Pa using Cl 2 gas, power of 200
Plasma anisotropic etching is performed at .about.300 W to leave the phosphorus-doped polycrystalline silicon film spacers 9a only on the sidewalls of the contact holes 7 and 8, respectively. The upper ends of the phosphorus-doped polycrystalline silicon film spacers 9a are lower than the upper surface of the interlayer insulating film 6 (upper ends of the contact holes 7 and 8). This interval is a predetermined value, and this value is preferably 1/2 of the diameter of the contact holes 7 and 8. In the above etching, after the phosphorus-doped polycrystalline silicon film 9 on the upper surface of the interlayer insulating film 6 is removed, the etching is continued for a further predetermined time to obtain the phosphorus-doped polycrystalline silicon film spacer 9a having the above-described shape [Fig. 1 (c)].
【００１２】次に、流量比１〜２のＷＦ6 ／ＳｉＨ4 ガ
スを用いた温度２００〜３００℃，圧力０．１〜０．３
Ｐａのタングステンの選択ＣＶＤ法により、コンタクト
孔７，８内をそれぞれ第２導電体膜であるタングステン
膜１０Ａにより充填する。このタングステン膜１０Ａ
は、それぞれのコンタクト孔７，８の底面とリンドープ
ド多結晶シリコン膜スペーサ９ａの表面とからほぼ同じ
成長速度で成長する。コンタクト孔７，８の口径が等し
く，リンドープド多結晶シリコン膜スペーサ９ａの上端
が上述のようになっている場合には、タングステン膜１
０Ａが成長してそれぞれのコンタクト孔７，８の上端に
到達するのは、ほぼ同時である。このとき、タングステ
ン膜１０Ａの上面は、それぞれ概ね平坦になっている
〔図１（ｄ）〕。なお、リンドープド多結晶シリコン膜
スペーサ９ａの上端とコンタクト孔７，８の上端とが一
致している場合には、これらの上端においても、タング
ステン膜１０Ａは成長初期の段階から成長するため、最
終的なタングステン膜１０Ａの上面が層間絶縁膜６の上
面より突出した形状になり、後工程での上層の配線の形
成に支障をきたすことになる。Next, using WF 6 / SiH 4 gas with a flow rate ratio of 1 to 2, the temperature is 200 to 300 ° C., and the pressure is 0.1 to 0.3.
The contact holes 7 and 8 are filled with the tungsten film 10A that is the second conductor film by the selective CVD method of tungsten of Pa. This tungsten film 10A
Grow at substantially the same growth rate from the bottom surfaces of the contact holes 7 and 8 and the surface of the phosphorus-doped polycrystalline silicon film spacer 9a. If the diameters of the contact holes 7 and 8 are equal and the upper end of the phosphorus-doped polycrystalline silicon film spacer 9a is as described above, the tungsten film 1
It is almost the same time that 0A grows and reaches the upper ends of the respective contact holes 7 and 8. At this time, the upper surfaces of the tungsten films 10A are substantially flat [FIG. 1 (d)]. When the upper end of the phosphorus-doped polycrystalline silicon film spacer 9a and the upper ends of the contact holes 7 and 8 are aligned with each other, the tungsten film 10A also grows from these initial stages even at these upper ends. The upper surface of the tungsten film 10A has a shape protruding from the upper surface of the interlayer insulating film 6, which hinders the formation of an upper wiring in a later step.
【００１３】その後、それぞれのタングステン膜１０Ａ
（およびコンタクト孔７，８）を介して、それぞれ拡散
層４およびポリサイドゲート電極３に接続される上層の
配線層（図示せず）を層間絶縁膜６上面に形成する。Then, each tungsten film 10A is formed.
An upper wiring layer (not shown) connected to the diffusion layer 4 and the polycide gate electrode 3 respectively (and via the contact holes 7 and 8) is formed on the upper surface of the interlayer insulating film 6.
【００１４】なお、上記第１の実施例はＮ型の拡散層の
みを有する場合の半導体装置の製造方法であるが、Ｎ型
の拡散層とＰ型の拡散層とを有する半導体装置の場合に
は、第１導電体膜として減圧ＣＶＤ法による低濃度のド
ープド多結晶シリコン膜あるいはノンドープド多結晶シ
リコン膜，もしくはスパッタリング等による所望の膜厚
（コンタクト孔を充填するのでなければ問題はない）の
金属膜等を用いてもよい。The first embodiment is a method of manufacturing a semiconductor device having only an N type diffusion layer. However, in the case of a semiconductor device having an N type diffusion layer and a P type diffusion layer. Is a low-concentration doped polycrystalline silicon film or a non-doped polycrystalline silicon film formed by the low pressure CVD method as the first conductor film, or a metal having a desired film thickness (there is no problem unless the contact hole is filled) by sputtering or the like. A film or the like may be used.
【００１５】上記第１の実施例は、１度のフォトリソグ
ラフィ工程により２種類の深さのコンタクト孔を開口し
ても、これら２種類のコンタクト孔内に同時に導電体膜
を充填できる。充填された導電体膜の上面も概ねコンタ
クト孔の上端と一致し、かつ、概ね平坦の面となる。そ
の結果、製造工程が短縮される。さらに、これらのコン
タクト孔に接続される上層の配線のこれらコンタクト孔
の上端近傍での断線は、起りにくくなる。深さが異なる
３種類以上のコンタクト孔がある場合でも、本実施例を
適用することは可能である。In the first embodiment, even if the contact holes having two kinds of depths are opened by one photolithography process, the conductor film can be simultaneously filled in these two kinds of contact holes. The upper surface of the filled conductor film also substantially coincides with the upper end of the contact hole and is a substantially flat surface. As a result, the manufacturing process is shortened. Further, disconnection of upper layer wirings connected to these contact holes near the upper ends of these contact holes is less likely to occur. Even if there are three or more types of contact holes having different depths, this embodiment can be applied.
【００１６】半導体装置の製造工程の断面図である図２
の参照すると、本発明の第２の実施例は、以下のように
なっている。FIG. 2 is a sectional view of the manufacturing process of the semiconductor device.
The second embodiment of the present invention is as follows.
【００１７】まず、上記第１の実施例と同様に、Ｐ型の
半導体基板１表面にゲート酸化膜２を形成し、ゲート酸
化膜２上にポリサイドゲート電極５を形成した後、ポリ
サイドゲート電極５の側壁に絶縁膜スペーサ３を形成す
る。半導体基板１表面にＮ型の拡散層４を形成した後、
全面に層間絶縁膜６を形成する。次に、拡散層４に達す
る深さの深いコンタクト孔７と、ポリサイドゲート電極
５に達する深さの浅いコンタクト孔８とを層間絶縁膜６
に同時に形成する。コンタクト孔７の口径は、コンタク
ト孔８の口径と同じである〔図２（ａ）〕。First, similarly to the first embodiment, the gate oxide film 2 is formed on the surface of the P type semiconductor substrate 1, the polycide gate electrode 5 is formed on the gate oxide film 2, and then the polycide gate is formed. The insulating film spacer 3 is formed on the side wall of the electrode 5. After forming the N type diffusion layer 4 on the surface of the semiconductor substrate 1,
An interlayer insulating film 6 is formed on the entire surface. Next, the contact hole 7 having a deep depth reaching the diffusion layer 4 and the contact hole 8 having a shallow depth reaching the polycide gate electrode 5 are formed.
To form at the same time. The diameter of the contact hole 7 is the same as the diameter of the contact hole 8 [FIG. 2 (a)].
【００１８】次に、温度３００〜４００℃，圧力３５０
〜８００Ｐａ，パワー２〜３ｋＷでのスパッタリングに
より、全面にチタン膜と窒化チタン膜とが積層されてな
る第１導電体膜であるところのチタン−窒化チタン膜１
１を形成する。このチタン−窒化チタン膜１１の膜厚
も、コンタクト孔７，８の口径に比べて薄く、所望の薄
さになっている〔図２（ｂ）〕。Next, the temperature is 300 to 400 ° C. and the pressure is 350.
-Titanium-titanium nitride film 1 which is a first conductor film formed by laminating a titanium film and a titanium nitride film on the entire surface by sputtering at 800 Pa and a power of 2 to 3 kW.
1 is formed. The film thickness of the titanium-titanium nitride film 11 is smaller than the diameters of the contact holes 7 and 8 and has a desired thickness [FIG. 2 (b)].
【００１９】続いて、ＳｉＨ4 還元，もしくはＨ2 還元
を用いたＣＶＤ法（いわゆるブランケットＣＶＤ法）に
より、全面に第２導電体膜であるところの膜厚が少なく
ともコンタクト孔７，８の口径の１／２のタングステン
膜を形成する。本実施例では、全面に上記チタン−窒化
チタン膜１１が形成されているため、このタングステン
膜はコンタクト孔７，８の側壁にも十分に成長し，空洞
（キャビティ）の形成がなされることなくこれらコンタ
クト孔７，８を充填することができる。次に、流量比２
〜３のＣＦ4 ／Ｏ2 ガスを用いた圧力１３０〜２７０Ｐ
ａ，パワー２００〜３００Ｗのプラズマ異方性エッチン
グによるエッチバックにより、タングステン膜１０Ｂと
チタン−窒化チタン膜１１ａとをそれぞれのコンタクト
孔７，８内に残置させる。このエッチングではチタン膜
および窒化チタン膜に比べてタングステン膜のエッチン
グ速度が高いため、タングステン膜１０Ｂの上面はチタ
ン−窒化チタン膜１１ａの上端より低くなっている。チ
タン−窒化チタン膜１１ａの上端は層間絶縁膜６の上面
（コンタクト孔７，８の上端）より低く、この間隔は所
定の値であり、この値はコンタクト孔７，８の口径の１
／２であることが好ましい〔図２（ｃ）〕。Then, by a CVD method using SiH 4 reduction or H 2 reduction (so-called blanket CVD method), the film thickness of the second conductor film is at least equal to the diameter of the contact holes 7 and 8. A half tungsten film is formed. In the present embodiment, since the titanium-titanium nitride film 11 is formed on the entire surface, this tungsten film also grows sufficiently on the sidewalls of the contact holes 7 and 8 without forming a cavity. These contact holes 7 and 8 can be filled. Next, the flow rate ratio 2
˜3, CF 4 / O 2 gas pressure 130-270P
a, the tungsten film 10B and the titanium-titanium nitride film 11a are left in the respective contact holes 7 and 8 by etching back by plasma anisotropic etching with power of 200 to 300 W. Since the etching rate of the tungsten film is higher than that of the titanium film and the titanium nitride film in this etching, the upper surface of the tungsten film 10B is lower than the upper end of the titanium-titanium nitride film 11a. The upper end of the titanium-titanium nitride film 11a is lower than the upper surface of the interlayer insulating film 6 (upper ends of the contact holes 7 and 8), and this distance is a predetermined value, which is 1 of the diameters of the contact holes 7 and 8.
It is preferably / 2 [Fig. 2 (c)].
【００２０】次に、上記第１の実施例と同様に、流量比
１〜２のＷＦ6 ／ＳｉＨ4 ガスを用いた温度２００〜３
００℃，圧力０．１〜０．３Ｐａのタングステンの選択
ＣＶＤ法により、コンタクト孔７，８内にそれぞれ第３
導電体膜であるタングステン膜１０Ｃを形成する。この
結果、コンタクト孔７，８内はそれぞれタングステン膜
１０Ｂとタングステン膜１０Ｃとにより充填される〔図
２（ｄ）〕。Next, as in the first embodiment, temperatures of 200 to 3 using WF 6 / SiH 4 gas with a flow rate ratio of 1 to 2 are used.
By the selective CVD method of tungsten at a temperature of 00 ° C. and a pressure of 0.1 to 0.3 Pa, third contact holes are formed in the contact holes 7 and 8, respectively.
A tungsten film 10C which is a conductor film is formed. As a result, the contact holes 7 and 8 are filled with the tungsten film 10B and the tungsten film 10C, respectively (FIG. 2 (d)).
【００２１】なお、第１導電体膜（例えば、チタン膜，
窒化チタン膜等）と第２導電体膜（例えば、タングステ
ン膜）とのエッチング速度がほぼ等しくなる異方性エッ
チングが存在するならば、第１導電体膜の上端および第
２導電体膜の上面が層間絶縁膜の上面と一致するまでエ
ッチバックすればよいことになり、図２（ｄ）に示した
ような第３導電体膜の形成は必要が無くなる。The first conductor film (for example, titanium film,
If there is anisotropic etching in which the etching rates of the titanium nitride film or the like) and the second conductor film (for example, a tungsten film) are substantially equal, the upper end of the first conductor film and the upper surface of the second conductor film are present. Is to be etched back until it coincides with the upper surface of the interlayer insulating film, and the formation of the third conductor film as shown in FIG. 2D is not necessary.
【００２２】上記第２の実施例は、上記第１の実施例と
同じ効果を有する。さらに本実施例は、コンタクト孔底
部にバリアメタルとして機能するチタン−窒化チタン膜
が残留形成されているため、上記第１の実施例よりコン
タクト孔でのリーク電流が低減される。The second embodiment has the same effect as the first embodiment. Further, in this embodiment, since the titanium-titanium nitride film functioning as a barrier metal remains formed at the bottom of the contact hole, the leak current in the contact hole is reduced as compared with the first embodiment.
【００２３】[0023]
【発明の効果】以上説明したように本発明の半導体装置
の製造方法によると、１度のフォトリソグラフィ工程に
より２種類以上の深さのコンタクト孔を開口しても、こ
れらのコンタクト孔内に同時に導電体膜を充填できる。
充填された導電体膜の上面も概ねコンタクト孔の上端と
一致し、かつ、概ね平坦の面となる。その結果、製造工
程が短縮される。さらに、これらのコンタクト孔に接続
される上層の配線のこれらコンタクト孔の上端近傍での
断線は、起りにくくなる。As described above, according to the method of manufacturing a semiconductor device of the present invention, even if contact holes having two or more kinds of depths are formed by one photolithography process, the contact holes are simultaneously formed in these contact holes. A conductor film can be filled.
The upper surface of the filled conductor film also substantially coincides with the upper end of the contact hole and is a substantially flat surface. As a result, the manufacturing process is shortened. Further, disconnection of upper layer wirings connected to these contact holes near the upper ends of these contact holes is less likely to occur.
【図１】本発明の第１の実施例の製造工程の断面図であ
る。FIG. 1 is a sectional view of a manufacturing process according to a first embodiment of the present invention.
【図２】本発明の第２の実施例の製造工程の断面図であ
る。FIG. 2 is a cross-sectional view of the manufacturing process of the second embodiment of the present invention.
【図３】従来の半導体装置の製造工程の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device manufacturing process.
１ 半導体基板 ２ ゲート酸化膜 ３ ポリサイドゲート電極 ４ 拡散層 ５ 絶縁膜スペーサ ６ 層間絶縁膜 ７，８，１７，１８ コンタクト孔 ９ リンドープド多結晶シリコン膜 ９ａ リンドープド多結晶シリコン膜スペーサ １０Ａ，１０Ｂ，１０Ｃ，２０ タングステン膜 １１，１１ａ チタン−窒化チタン膜 １２ 多結晶シリコン膜 １２ａ 多結晶シリコン膜スペーサ １５ ゲート電極 1 Semiconductor Substrate 2 Gate Oxide Film 3 Polycide Gate Electrode 4 Diffusion Layer 5 Insulating Film Spacer 6 Interlayer Insulating Film 7, 8, 17, 18 Contact Hole 9 Phosphorus Doped Polycrystalline Silicon Film 9a Phosphorus Doped Polycrystalline Silicon Film Spacer 10A, 10B, 10C , 20 Tungsten film 11, 11a Titanium-titanium nitride film 12 Polycrystalline silicon film 12a Polycrystalline silicon film spacer 15 Gate electrode
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/285 ３０１ Ｒ 7376−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical indication H01L 21/285 301 R 7376-4M
Claims (3)
ぞれ異なる複数の種類の配線層を形成し、全面に層間絶
縁膜を形成し、同じ口径を有し，該配線層の上面に達す
る深さの異なる複数の種類のコンタクト孔を該層間絶縁
膜に形成する工程と、 全面に第１導電体膜を形成し、該第１導電体膜を異方性
エッチングして前記層間絶縁膜の上面から所定の深さよ
り下方のそれぞれの前記コンタクト孔の側壁に該第１導
電体膜からなるスペーサを形成する工程と、 第２導電体膜の選択成長を行ない、それぞれの前記コン
タクト孔を該第２導電体膜で充填する工程とを有するこ
とを特徴とする半導体装置の製造方法。1. A plurality of types of wiring layers each having a different height from the surface of the semiconductor substrate are formed, an interlayer insulating film is formed on the entire surface, and the depth is the same as that of the wiring layer. A plurality of types of contact holes having different thicknesses are formed in the interlayer insulating film, and a first conductor film is formed on the entire surface, and the first conductor film is anisotropically etched to form an upper surface of the interlayer insulator film. Forming a spacer made of the first conductor film on the side wall of each of the contact holes below a predetermined depth from, and selectively growing the second conductor film to form each of the contact holes in the second hole. And a step of filling with a conductor film.
ぞれ異なる複数の種類の配線層を形成し、全面に層間絶
縁膜を形成し、同じ口径を有し，該配線層の上面に達す
る深さの異なる複数の種類のコンタクト孔を該層間絶縁
膜に形成する工程と、 全面に第１導電体膜を形成し、それぞれの前記コンタク
ト孔が充填されるまで全面に第２導電体膜を成長する工
程と、 前記第２導電体膜および前記第１導電体膜を異方性エッ
チングによりエッチバックして、それぞれの前記コンタ
クト孔における前記層間絶縁膜の上面から所定の深さま
での該第１導電体膜を除去する工程と、 第３導電体膜の選択成長を行ない、それぞれの前記コン
タクト孔を該第３導電体膜と前記第２導電体膜とで充填
する工程とを有することを特徴とする半導体装置の製造
方法。2. A plurality of types of wiring layers each having a different height from the surface of the semiconductor substrate are formed, an interlayer insulating film is formed on the entire surface, and the depth is the same as that of the wiring layer. Forming a plurality of different kinds of contact holes in the interlayer insulating film, and forming a first conductive film on the entire surface and growing a second conductive film on the entire surface until the contact holes are filled. And a step of etching back the second conductor film and the first conductor film by anisotropic etching to obtain a first depth from the upper surface of the interlayer insulating film in each of the contact holes to a predetermined depth. And a step of selectively growing the third conductor film and filling each of the contact holes with the third conductor film and the second conductor film. Method for manufacturing semiconductor device .
ン膜との積層膜であり、前記第２導電体膜および前記第
３導電体膜がタングステン膜であることを特徴とする請
求項２記載の半導体装置の製造方法。3. The first conductor film is a laminated film of a titanium film and a titanium nitride film, and the second conductor film and the third conductor film are tungsten films. 2. The method for manufacturing a semiconductor device according to 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5296493A JP3014019B2 (en) | 1993-11-26 | 1993-11-26 | Method for manufacturing semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5296493A JP3014019B2 (en) | 1993-11-26 | 1993-11-26 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07147321A true JPH07147321A (en) | 1995-06-06 |
| JP3014019B2 JP3014019B2 (en) | 2000-02-28 |
Family
ID=17834273
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5296493A Expired - Fee Related JP3014019B2 (en) | 1993-11-26 | 1993-11-26 | Method for manufacturing semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP3014019B2 (en) |
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