JPH04320329A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for forming a contact with a low resistance and without junction leak. CONSTITUTION:A silicon layer 6 is formed on a semiconductor substrate 11 at a bottom portion of a contact hole 3, a high-melting-point metal silicide layer 7 is formed in self-alignment manner, and then a metal film 8 is selectively formed on this high-melting-point metal silicide layer 7.

Description

[Detailed description of the invention]

[Object of the invention]

0002

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to burying contact holes.

0003

2. Description of the Related Art In recent years, as semiconductor devices have become more highly integrated, circuits have become increasingly finer.

[0004] As the miniaturization progresses, the aspect ratio of the through holes that connect the wiring layers increases.
A problem arises in that the step coverage of the wiring film deteriorates and the resistance increases. As a method to solve this problem, a method has been proposed in which polycrystalline silicon or metal containing impurities is buried in the contact hole.

The following methods are available for burying polycrystalline silicon containing impurities into contact holes.

First, as shown in FIG. 7(a), a silicon oxide film 2 with a thickness of 1.5 μm is formed on the surface of a silicon substrate 1 on which a field oxide film 22 has been formed, and then RIE is performed.
1.0 μm for contacting with the diffusion layer 11 by the method
20 nm thick Ti layer 4 and 70 nm thick TiN layer 5 as barrier metal.
form. After this, as shown in Fig. 7(b),
A polycrystalline silicon layer 6 containing boron is formed by CVD using 2 H6 and SiH4.

After this, as shown in FIG. 7(c),
In this method, this polycrystalline silicon layer 6 is etched back by the RIE method, and the polycrystalline silicon layer 6 is formed only in the contact hole 3.

[0008] Furthermore, as a method of embedding metal in a contact hole, a method of selectively growing a metal film such as a W film is carried out as follows.

First, as shown in FIG. 8(a), a silicon oxide film 2 with a thickness of 1.5 μm is formed on the surface of a silicon substrate 1 on which a field oxide film 22 has been formed, and then RIE is performed.
1.0 μm for contacting with the diffusion layer 11 by the method
A contact hole 3 with a diameter of 20 nm is formed, and a T
An i layer 4 and a 20 nm TiN layer 5 are formed.

After this, as shown in FIG. 8(b), 750
A 40 nm T layer is formed at the bottom of the contact hole by heat treatment at ℃.
An iSi2 layer 7 is formed, and unreacted Ti layer 4 and Ti
N layer 5 is etched away and Ti is deposited only on the bottom of the contact.
A Si2 layer 7 is formed.

Then, as shown in FIG. 8(c), WF6
A tungsten layer 8 is selectively formed by a CVD method using SiH4 and SiH4.

However, as shown in FIG. 7, when a polycrystalline silicon film containing impurities is buried in a contact hole, the specific resistance is as high as several tens to hundreds of μΩcm, and the contact resistance also becomes high.

Further, as shown in FIG. 8, when a metal film such as a W film is embedded, the specific resistance becomes as low as 10-odd μΩcm. However, in this case, since the Ti layer is silicided by reacting with the silicon substrate 1, the TiSi2
There is an upper limit to the thickness of layer 7. Therefore, as shown in FIG. 8(d), the tungsten layer 8 tends to dig into the silicon substrate 1 along the grain boundaries of the TiSi2 layer 7, causing a problem of junction leakage.

[0014]

[Problems to be Solved by the Invention] As described above, the conventional method of burying contact holes has the problems of high contact resistance and junction leakage.

The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a method for forming a contact with low resistance and no junction leak.

[Configuration of the invention]

[0017]

[Means for Solving the Problems] Therefore, in the present invention, a silicon layer is selectively formed on the semiconductor substrate at the bottom of the contact hole, and then a refractory metal silicide layer is formed from this silicon layer in a self-aligned manner. , a metal film is formed on this high melting point metal silicide layer. Here, the silicon layer formed on the substrate refers to amorphous silicon, polycrystalline silicon, or epitaxial silicon, and the high melting point metal silicide refers to Ti, Zn, Mo, Co, Ni.
, W, etc., and silicon, and the metal film is a metal such as W, Al, Cu, etc.

[0018]

As described above, according to the method of the present invention, the contact resistance can be lowered by burying the refractory metal silicide layer and the metal film in the contact hole. Further, since a high melting point metal silicide layer having a thickness of, for example, 0.15 μm or more can be formed between the substrate and the metal film, junction leakage due to penetration of the diffusion layer of the metal film can be prevented.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Embodiment 1 FIGS. 1(a) to 1(f) are cross-sectional views showing the manufacturing process of a semiconductor device according to a first embodiment of the present invention.

First, after forming a field oxide film 22 on a silicon substrate 1, an opening is formed and a 70 nm thick p-oxide film is formed.
Form a + type diffusion layer. After that, the film thickness was 1.5 using the CVD method.
A silicon oxide film 2 with a diameter of 1.0 μm is formed, and this silicon oxide film 2 is patterned by reactive ion etching using CHF using a resist pattern formed by photolithography as a mask to form a contact hole 3 with a diameter of 1.0 μm. do. And further after this, 6
By thermal decomposition of SiH4 at 00°C, a film thickness of 1.
A 3 μm thick polycrystalline silicon film 6 is formed to fill the contact hole 3 (FIG. 1(a)).

Next, the polycrystalline silicon film 6 is etched back by RIE using chlorine, leaving a polycrystalline silicon layer 6 with a thickness of 0.2 μm at the bottom of the contact hole 3 (
Figure 1(b)).

Next, by DC sputtering, a titanium film 4 with a thickness of 90 nm and a T film with a thickness of 70 nm are deposited on the entire surface of the substrate.
An iN film 5 is formed (FIG. 1(c)).

Next, as shown in FIG. 1(d), lamp annealing is performed at 750° C. to 800° C. for 120 seconds in a nitrogen atmosphere to form a TiSi2 film with a thickness of 0.23 μm on the diffusion layer 11.
Form layer 7.

Thereafter, as shown in FIG. 1(e), the unreacted Ti film 4 and TiN film 5 are removed by etching with a mixed solution of hydrogen peroxide and sulfuric acid.

Next, as shown in FIG. 1(f), WF6
TiSi by selective CVD method using and SiH4
2. A W layer 8 having a thickness of 1.2 μm is selectively formed only on layer 7.

In the contact hole filled in this way, the TiSi2 film thickness is as thick as 0.23 μm, so the W layer 8 does not dig into the substrate 1, and junction leakage can be prevented, and the TiSi2 layer 7 Since the contact resistance is formed of only the W layer 8 and the W layer 8, the contact resistance can be lowered.

Furthermore, it is possible to obtain a device with good ohmic contact properties and good characteristics even when miniaturized.

Example 2 Next, a second embodiment of the present invention will be described.

In Example 1, the Ti layer 4 was also formed on the silicon oxide film 2, but this example is characterized in that it is formed only on the polycrystalline silicon layer 6.

[0031] Therefore, the step of removing the unreacted Ti film can be omitted.

The process up to forming the contact hole 3 and filling the polycrystalline silicon layer is the same as in Example 1 (see FIG. 2(a)
) and (b) ).

After this, as shown in FIG. 2(c), TiC
A titanium layer 4 having a thickness of 90 nm is selectively formed only on the polycrystalline silicon layer 6 by a thermal decomposition method using l4, SiH4, and H2. The substrate temperature at this time is 400~
The temperature shall be 450°C.

Thereafter, as shown in FIGS. 2(d) and 2(e), a TiSi2 layer 7 and a W layer 8 are formed in the same manner as in Example 1, but the step of removing the unreacted Ti layer is not necessary. .

[0035] This method also makes it possible to form a highly reliable contact with low contact resistance as in the first embodiment.

Example 3 Next, a third embodiment of the present invention will be described.

In this example, TiSi2 7 is grown on the polycrystalline silicon layer 6 at a high temperature of 600 to 750°C, and at the same time this titanium layer is reacted with the polycrystalline silicon layer 6, thereby selectively forming the titanium layer in the contact hole. A TiSi2 layer 7 is formed, followed by lamp annealing at 800°C for 30 seconds.
It is characterized in that the TiSi2 layer 7 is made to have a low resistance by performing the process.

The process up to the formation of the contact hole 3 and the filling of the polycrystalline silicon layer is the same as in Examples 1 and 2 (
Figures 3(a) and (b)).

After this, as shown in FIG. 3(c), TiC
A titanium layer is selectively formed only on the polycrystalline silicon layer 6 by a thermal decomposition method using L4, SiH4, and H2, and at the same time, this layer is reacted with the polycrystalline silicon layer 6 to form a titanium layer.
An iSi2 layer 7 is formed. The substrate temperature at this time is 60
The temperature shall be 0 to 750°C.

[0040] Then, lamp annealing at 800°C for 30 seconds
The resistance of the TiSi2 layer 7 was lowered by applying
Further, a W layer 8 is selectively formed thereon as shown in FIG.

[0041] This method also makes it possible to form a highly reliable contact with low contact resistance as in Examples 1 and 2.

Example 4 Next, a fourth embodiment of the present invention will be described.

In Example 1, the polycrystalline silicon film 6 was formed on the diffusion layer 11, but in this example, SiBr was formed at 850°C.
4 and H2 are decomposed to selectively form an epitaxial silicon layer 9 on the diffusion layer 11, and the subsequent steps are the same as in the first embodiment.

That is, as shown in FIG. 4(a), after forming the contact hole 3, SiBr4 and H2 are decomposed at 850° C. by selective epitaxial growth to form an epitaxial silicon layer 9 on the diffusion layer 11. do.

After that, contacts are formed in the same manner as in Example 1, as shown in FIGS. 4(b) to 4(e).

Example 5 Next, a fifth embodiment of the present invention will be described.

In Example 2, the polycrystalline silicon film 6 was formed on the diffusion layer 11, but in this example, as in Example 4, the polycrystalline silicon film 6 was
SiBr4 and H2 are decomposed at 50°C to form a diffusion layer 11.
This embodiment is characterized in that an epitaxial silicon layer 9 is selectively formed thereon, and the subsequent steps are the same as in the second embodiment.

That is, as shown in FIG. 5(a),
After forming the contact hole 3, SiBr4 and H2 are decomposed at 850° C. by selective epitaxial growth to form an epitaxial silicon layer 9 on the diffusion layer 11.

Afterwards, contacts are formed in the same manner as in Example 2, as shown in FIGS. 5(b) to 5(e).

Example 6 Next, a sixth embodiment of the present invention will be described.

In Example 3, the polycrystalline silicon film 6 was formed on the diffusion layer 11, but in this example, as in Examples 4 and 5, SiBr4 and H2 were decomposed at 850° C. and the polycrystalline silicon film 6 was formed on the diffusion layer 11. This method is characterized by selectively forming an epitaxial silicon layer 9, and the subsequent steps are as in Example 3.
It is similar to

That is, as shown in FIG. 6(a),
After forming the contact hole 3, SiBr4 and H2 are decomposed at 850° C. by selective epitaxial growth to form an epitaxial silicon layer 9 on the diffusion layer 11.

Afterwards, contacts are formed in the same manner as in Example 3, as shown in FIGS. 6(b) and 6(c). In the above embodiment, the case where the contact is formed on the p+ type diffusion layer 11 has been described, but it goes without saying that the present invention is also applicable to the case where the contact is formed on the n+ type diffusion layer.

[0054] In addition to polycrystalline silicon and epitaxial silicon, silicon to be buried in the contact hole may include polycrystalline silicon, epitaxial silicon,
Amorphous silicon may also be used. When forming an amorphous silicon film on the entire surface of the substrate, the substrate temperature is 50°C.
It may be carried out by thermal decomposition of SiH4 at a temperature of 0° C. or lower. When forming a silicon layer by selective growth,
It is sufficient to use a method of decomposing SiBr4 and H2, and depending on the substrate temperature at this time, the polycrystalline silicon layer (60
It is also possible to grow an amorphous silicon layer (450°C).

Further, in the above embodiment, Ti was used as the high melting point metal, but metals such as Zn, Mo, Co, Ni, and W may also be used.

[0056] In addition to W, the metal film may include Al, C, etc.
Metals such as u are also applicable. An Al film can be selectively formed on the silicide layer using triisobutylaluminum, and a Cu film can also be selectively formed on the silicide layer using CuCl2. Furthermore, the metal film may be formed not only selectively on the silicide layer but also over the entire surface of the substrate including the silicide layer.

In addition, various modifications can be made without departing from the gist of the present invention.

Furthermore, the thickness of the TiSi2 layer is not limited to the above embodiment. In order to investigate the relationship between the thickness of the TiSi2 layer and the junction leakage current, the following experiment was conducted.

That is, contact is made with the n+ diffusion layer (70 nm thick) formed on the surface of the p-type silicon substrate. After forming a TiSi2 layer with varying thickness in a contact hole with a diameter of 1.0 μm and a depth of 1.5 μm, a W layer is completely buried, and wiring is formed with Al alloy on top of this to form an n+/p junction. The junction leak current was measured. FIG. 7 is a characteristic diagram showing the results. When the TiSi2 film thickness is 0.15 μm or more, the junction leak current becomes large. This is thought to be due to the fact that the W layer penetrates through the TiSi2 layer and junction breakdown occurs because the TiSi2 layer is thin. As a result, the thickness of the TiSi2 layer is 0.
．． It can be seen that approximately 15 μm or more is required.

[0060]

As explained above, according to the present invention, a silicon layer is formed on a semiconductor substrate at the bottom of a contact hole, and then a silicide layer of a high melting point metal is formed from this silicon layer in a self-aligned manner. Since a metal film is formed on this high melting point metal silicide layer, it is possible to form a contact with low resistance and no junction leak.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a manufacturing process diagram of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a manufacturing process diagram of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a characteristic diagram showing the relationship between TiSi2 film thickness and junction leakage current.

FIG. 8 is a manufacturing process diagram of a conventional semiconductor device.

FIG. 9 is a manufacturing process diagram of a conventional semiconductor device.

[Explanation of symbols]

1 Silicon substrate 2 Silicon oxide film 22 Field oxide film 3 Contact hole 4 Ti film 5 TiN film 6 Polycrystalline silicon film 7 TiSi2 layer 8 W layer 9 Epitaxial silicon layer 11 Diffusion layer

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including a step of forming a contact on a semiconductor substrate, a contact hole forming step of forming an insulating film on the substrate and forming a contact hole in the insulating film, and a step of forming a contact hole in the contact hole. a silicon layer forming step of selectively forming a silicon layer; a silicide layer forming step of forming a thick refractory metal silicide layer from the silicon layer in a self-aligned manner; and forming a metal film on the refractory metal silicide layer. 1. A method for manufacturing a semiconductor device, comprising a step of forming a metal film.