JPH07142491A - Solder bump forming method and semiconductor device having bump formed by the method - Google Patents
Solder bump forming method and semiconductor device having bump formed by the methodInfo
- Publication number
- JPH07142491A JPH07142491A JP5290149A JP29014993A JPH07142491A JP H07142491 A JPH07142491 A JP H07142491A JP 5290149 A JP5290149 A JP 5290149A JP 29014993 A JP29014993 A JP 29014993A JP H07142491 A JPH07142491 A JP H07142491A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- bump
- ccb
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 title claims abstract description 70
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000010438 heat treatment Methods 0.000 claims abstract description 3
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 3
- 230000008018 melting Effects 0.000 claims description 3
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims 1
- 229910001887 tin oxide Inorganic materials 0.000 claims 1
- 229910020220 Pb—Sn Inorganic materials 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 4
- 230000004907 flux Effects 0.000 description 4
- 229910021514 lead(II) hydroxide Inorganic materials 0.000 description 4
- 229910006404 SnO 2 Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 229910018487 Ni—Cr Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052745 lead Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
- H01L2224/11472—Profile of the lift-off mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/118—Post-treatment of the bump connector
- H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
- H01L2224/11849—Reflowing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/165—Material
- H01L2224/16505—Material outside the bonding interface, e.g. in the bulk of the bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 特別なプロセスを用いずに、ＣＣＢ半田バン
プの耐湿性を向上させること。
【構成】 半導体チップを基板にフリップ・チップ接続
するための半田バンプの形成方法であって、前記半導体
チップの能動素子面にバンプ用の半田を定着させ、その
半田を溶融して基板と接続し、その接続後にその半田の
表面を加熱もしくはリフローにより酸化する。
(57) [Abstract] [Purpose] To improve the moisture resistance of CCB solder bumps without using a special process. A method for forming solder bumps for flip-chip connecting a semiconductor chip to a substrate, wherein solder for bumps is fixed on the active element surface of the semiconductor chip, and the solder is melted and connected to the substrate. After the connection, the surface of the solder is oxidized by heating or reflow.
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体チップの実装を
行う半田バンプに関し、特に、半導体チップを気密封止
せず、半田バンプが外部環境にさらされる場合に適用し
て有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder bump for mounting a semiconductor chip, and more particularly to a technique effective when applied to an external environment where the solder bump is exposed without hermetically sealing the semiconductor chip. is there.
【０００２】[0002]
【従来の技術】従来における半導体チップを基板にフリ
ップ・チップ接続するための半田バンプ（以下、ＣＣＢ
半田バンプと記す）の材質は、バンプの作り易さ、コス
ト、バンプ下地メタライズとの関係からＰｂ−Ｓｎ系の
半田が多く用いられる。2. Description of the Related Art Solder bumps (hereinafter referred to as CCBs) for flip-chip connecting a conventional semiconductor chip to a substrate.
As the material of the solder bump), Pb-Sn based solder is often used in consideration of the ease of making the bump, the cost, and the bump base metallization.
【０００３】Ｐｂ−Ｓｎ系の半田は、主に、高融点側で
あるＰｂの含有量がＳｎより多い（Ｐｂリッチ）のもの
が使用される。As the Pb-Sn type solder, a solder having a higher melting point Pb content than Sn (Pb rich) is mainly used.
【０００４】このＰｂリッチの半田は、半導体装置のリ
ークがあった場合等により、高湿度中にさらされると水
酸化鉛を生成し、腐食が進むという耐湿性に劣る欠点が
あり、この欠点を補うために、従来のＣＣＢ半田バンプ
には、樹脂をコーティングしたものがある。This Pb-rich solder has a drawback in that it is inferior in moisture resistance such that lead hydroxide is generated when exposed to high humidity due to leakage of a semiconductor device, etc., and corrosion progresses. To compensate, some conventional CCB solder bumps are resin coated.
【０００５】[0005]
【発明が解決しようとする課題】本発明者は、上記従来
技術を検討した結果以下の問題点を見いだした。DISCLOSURE OF THE INVENTION The present inventors have found the following problems as a result of examining the above prior art.
【０００６】上記従来技術において、ＣＣＢ半田バンプ
の耐湿性を向上させるために、樹脂をコーティングして
いたが、このコーティングには特別なプロセスが必要と
なるという問題点があった。In the above-mentioned prior art, a resin was coated in order to improve the moisture resistance of the CCB solder bump, but there was a problem in that this coating requires a special process.
【０００７】本発明の目的は、特別なプロセスを用いず
に、ＣＣＢ半田バンプの耐湿性を向上させることが可能
な技術を提供することにある。An object of the present invention is to provide a technique capable of improving the moisture resistance of CCB solder bumps without using a special process.
【０００８】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面によって明らか
になるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００９】[0009]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
下記のとおりである。Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.
【００１０】半導体チップを基板にフリップ・チップ接
続するための半田バンプの形成方法であって、前記半導
体チップの能動素子面にバンプ用の半田を定着させ、そ
の半田を溶融して基板と接続し、その接続後にその半田
の表面を加熱もしくはリフローにより酸化する。A method of forming solder bumps for flip-chip connecting a semiconductor chip to a substrate, wherein solder for bumps is fixed on the active element surface of the semiconductor chip, and the solder is melted and connected to the substrate. After the connection, the surface of the solder is oxidized by heating or reflow.
【００１１】[0011]
【作用】上述した手段によれば、半導体チップを基板に
フリップ・チップ接続するための半田バンプの形成方法
であって、前記半導体チップの能動素子面にバンプ用の
半田を定着させ、その半田を溶融して基板と接続し、そ
の接続後にその半田の表面を酸化することにより、ＣＣ
Ｂ半田バンプの表面にＳｎの酸化膜を形成することがで
きる。According to the above-mentioned means, there is provided a solder bump forming method for flip-chip connecting a semiconductor chip to a substrate, wherein the solder for the bump is fixed on the active element surface of the semiconductor chip, By melting and connecting to the substrate, and oxidizing the surface of the solder after the connection, CC
An Sn oxide film can be formed on the surface of the B solder bump.
【００１２】これにより、高湿度中においてもＣＣＢ半
田バンプの表面に覆われたＳｎの酸化膜によって、水酸
化鉛が生成されることがなくなり、特別なプロセスを用
いずに、ＣＣＢ半田バンプの耐湿性を向上させることが
可能になる。This prevents lead hydroxide from being generated by the Sn oxide film covered on the surfaces of the CCB solder bumps even in high humidity, and the CCB solder bumps can be protected against moisture without using a special process. It becomes possible to improve the property.
【００１３】以下、本発明の構成について、実施例とと
もに説明する。The structure of the present invention will be described below together with embodiments.
【００１４】なお、実施例を説明するための全図におい
て、同一機能を有するものは同一符号を付け、その繰り
返しの説明は省略する。In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.
【００１５】[0015]
【実施例】図１は本発明の一実施例のＣＣＢ半田バンプ
を有する半田封止型半導体装置の構成を説明するための
もので、ＣＣＢ半田バンプ部分を拡大してある。1 is a view for explaining the structure of a solder-sealed semiconductor device having a CCB solder bump according to an embodiment of the present invention, in which the CCB solder bump portion is enlarged.
【００１６】図１において、１は半導体チップ、２は積
層セラミック基板、３はキャップ、４はＰｂ−Ｓｎ半
田、５は接合層（以下、ＢＬＭと記す）、６はＳｎ酸化
膜、１０は半導体装置をそれぞれ示す。In FIG. 1, 1 is a semiconductor chip, 2 is a laminated ceramic substrate, 3 is a cap, 4 is Pb-Sn solder, 5 is a bonding layer (hereinafter referred to as BLM), 6 is an Sn oxide film, and 10 is a semiconductor. Each device is shown.
【００１７】図１に示すように、本実施例の半導体装置
１０の拡大されたＣＣＢ半田バンプの外側の表面に、Ｓ
ｎ酸化膜６が形成されている。このＳｎ酸化膜６は、Ｃ
ＣＢ半田バンプ形成後にその表面を強制的に酸化させて
形成したＳｎＯ2であり、Ｐｂ−Ｓｎ半田が耐湿性に劣
る原因となっていたＰｂを覆ってしまうので、ＣＣＢ半
田バンプの耐湿性を向上させることができる。As shown in FIG. 1, S is formed on the outer surface of the enlarged CCB solder bump of the semiconductor device 10 of this embodiment.
An n oxide film 6 is formed. This Sn oxide film 6 is C
SnO 2 is formed by forcibly oxidizing the surface of CB solder bumps after formation, and because Pb-Sn solder covers Pb, which is the cause of poor moisture resistance, the moisture resistance of CCB solder bumps is improved. Can be made.
【００１８】次に、本実施例の半導体装置１０のＣＣＢ
半田バンプの形成方法について、図２〜図６を用いて詳
細に説明する。Next, the CCB of the semiconductor device 10 of this embodiment
A method for forming the solder bumps will be described in detail with reference to FIGS.
【００１９】まず、図示しないウエーハに形成された半
導体チップ１の上にパッドと良好な電気的接触を得るた
めと、金属間で化合物が生じることを防止するためのＢ
ＬＭ５を形成する。ＢＬＭは、半導体チップ１にＣｒ層
を形成し、そのＣｒ層の上にＮｉ−Ｃｒを形成し、その
Ｎｉ−Ｃｒ層の上にＡｕ層を形成した三層構造である。First, B for obtaining good electrical contact with a pad on the semiconductor chip 1 formed on a wafer (not shown) and for preventing formation of a compound between metals.
Form LM5. The BLM has a three-layer structure in which a Cr layer is formed on the semiconductor chip 1, Ni—Cr is formed on the Cr layer, and an Au layer is formed on the Ni—Cr layer.
【００２０】そして、図２に示すように、半導体チップ
１上にレジストを形成してＰｂ−Ｓｎ半田（Ｐｂ９８
％，Ｓｎ２％含有）をＢＬＭ５上に生成し、リフトオフ
法により、図３に示すように、レジスト７を除去する。Then, as shown in FIG. 2, a resist is formed on the semiconductor chip 1 to form Pb-Sn solder (Pb98).
%, Sn2% content) is formed on the BLM 5, and the resist 7 is removed by the lift-off method as shown in FIG.
【００２１】次に、図４に示すように、その形成された
Ｐｂ−Ｓｎ半田４をフラックスを用いて、酸化膜を除去
しながらリフローする。その後、ウエーハをダイシング
し、各半導体チップ１ごとに分割する。Next, as shown in FIG. 4, the Pb-Sn solder 4 thus formed is reflowed using a flux while removing the oxide film. After that, the wafer is diced and divided into semiconductor chips 1.
【００２２】半導体チップ１が個々に分割された後、図
５に示すように、Ｐｂ−Ｓｎ半田４をフラックスを用い
て再度リフローし、積層セラミック基板２と接合させ、
ＣＣＢ半田バンプを形成する。After the semiconductor chip 1 is divided into individual pieces, as shown in FIG. 5, the Pb-Sn solder 4 is reflowed again by using a flux to bond it to the laminated ceramic substrate 2.
Form CCB solder bumps.
【００２３】そのリフロー後、フラックス洗浄を行い、
ＣＣＢ半田バンプと半導体チップ１と積層セラミック基
板２を清浄にする。After the reflow, flux cleaning is performed,
The CCB solder bumps, the semiconductor chip 1, and the laminated ceramic substrate 2 are cleaned.
【００２４】そして、ＣＣＢ半田バンプ形成後にＰｂ酸
化膜できてしまう前に、図６に示すように、フラックス
を用いないでリフローして、ＣＣＢ半田バンプの表面を
酸化させ、ＳｎＯ2を形成する。Then, before the Pb oxide film is formed after the CCB solder bumps are formed, as shown in FIG. 6, reflow is performed without using flux to oxidize the surfaces of the CCB solder bumps to form SnO 2 .
【００２５】このときの酸化処理装置として、温度と酸
素濃度を管理したリフロー炉体を用い、その設定を最高
温度３５０゜Ｃ，酸素濃度は約１００PPMにし、処理時
間を２〜３分とする。At this time, a reflow furnace whose temperature and oxygen concentration are controlled is used as the oxidation treatment apparatus, and the setting is such that the maximum temperature is 350 ° C., the oxygen concentration is about 100 PPM, and the treatment time is 2 to 3 minutes.
【００２６】また、このときの酸化処理されて生成され
たＣＣＢバンプの酸化物層は、表面がＳｎＯ2層で覆わ
れ、中心付近にＳｎＯ、金属Ｓｎ及びＰｂが混じった遷
移層が集まり、その中間に金属Ｐｂが細かく分散してい
るＳｎＯ層からなる。The surface of the oxide layer of the CCB bump produced by the oxidation treatment is covered with a SnO 2 layer, and a transition layer containing SnO, metals Sn and Pb is gathered in the vicinity of the center of the oxide layer. It is composed of a SnO layer in which metal Pb is finely dispersed in the middle.
【００２７】これは、日刊工業新聞社刊の「ソルダリン
グイン・エレクトロニクス」のＰ１０９〜Ｐ１１０に開
示されていることから明らかであろう。This will be apparent from the fact that it is disclosed on pages 109 to 110 of "Soldering in Electronics" published by Nikkan Kogyo Shimbun.
【００２８】したがって、半導体チップを基板にフリッ
プ・チップ接続するための半田バンプの形成方法であっ
て、前記半導体チップの能動素子面にバンプ用の半田を
定着させ、その半田を溶融して基板と接続し、その接続
後にその半田の表面を酸化することにより、ＣＣＢ半田
バンプの表面にＳｎの酸化膜を形成することができる。Therefore, there is provided a method of forming a solder bump for flip-chip connecting a semiconductor chip to a substrate, wherein the solder for the bump is fixed on the active element surface of the semiconductor chip and the solder is melted to form a substrate. A Sn oxide film can be formed on the surfaces of the CCB solder bumps by connecting and oxidizing the surface of the solder after the connection.
【００２９】これにより、高湿度中においてもＣＣＢ半
田バンプの表面に覆われたＳｎの酸化膜によって、水酸
化鉛が生成されることがなくなり、特別なプロセスを用
いずに、ＣＣＢ半田バンプの耐湿性を向上させることが
可能になる。This prevents lead hydroxide from being generated by the Sn oxide film covered on the surfaces of the CCB solder bumps even in high humidity, and the CCB solder bumps can be moisture-proofed without using a special process. It becomes possible to improve the property.
【００３０】また、従来の半導体装置に設けられていた
ＣＣＢ半田バンプは、気密封止が絶対条件であったが、
本発明のＣＣＢ半田バンプを用いることで、気密封止す
る必要がなくなる。Further, the CCB solder bumps provided in the conventional semiconductor device must be hermetically sealed,
By using the CCB solder bump of the present invention, it is not necessary to hermetically seal.
【００３１】以上、本発明者によってなされた発明を、
前記実施例に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。As described above, the invention made by the present inventor is
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.
【００３２】[0032]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【００３３】半導体チップを基板にフリップ・チップ接
続するための半田バンプの形成方法であって、前記半導
体チップの能動素子面にバンプ用の半田を定着させ、そ
の半田を溶融して基板と接続し、その接続後にその半田
の表面を酸化することにより、ＣＣＢ半田バンプの表面
にＳｎの酸化膜を形成することができ、高湿度中におい
てもＣＣＢ半田バンプの表面に覆われたＳｎの酸化膜に
よって、水酸化鉛が生成されることがなくなり、特別な
プロセスを用いずに、ＣＣＢ半田バンプの耐湿性を向上
させることが可能になる。A method of forming solder bumps for flip-chip connecting a semiconductor chip to a substrate, wherein bump solder is fixed on the active element surface of the semiconductor chip, and the solder is melted and connected to the substrate. By oxidizing the surface of the solder after the connection, a Sn oxide film can be formed on the surface of the CCB solder bump, and the Sn oxide film covered by the surface of the CCB solder bump can be formed even in high humidity. As a result, lead hydroxide is not generated, and the moisture resistance of the CCB solder bumps can be improved without using a special process.
【図１】本発明の一実施例である半導体装置の構成を説
明するための図である。FIG. 1 is a diagram illustrating a configuration of a semiconductor device that is an embodiment of the present invention.
【図２】本実施例の半導体装置におけるＣＣＢ半田バン
プ形成の工程を説明するための図である。FIG. 2 is a diagram for explaining a process of forming CCB solder bumps in the semiconductor device of this embodiment.
【図３】本実施例の半導体装置におけるＣＣＢ半田バン
プ形成の工程を説明するための図である。FIG. 3 is a diagram for explaining a process of forming CCB solder bumps in the semiconductor device of this embodiment.
【図４】本実施例の半導体装置におけるＣＣＢ半田バン
プ形成の工程を説明するための図である。FIG. 4 is a diagram for explaining a process of forming a CCB solder bump in the semiconductor device of this embodiment.
【図５】本実施例の半導体装置におけるＣＣＢ半田バン
プ形成の工程を説明するための図である。FIG. 5 is a diagram for explaining a process of forming CCB solder bumps in the semiconductor device of this embodiment.
【図６】本実施例の半導体装置におけるＣＣＢ半田バン
プ形成の工程を説明するための図である。FIG. 6 is a diagram for explaining a process of forming CCB solder bumps in the semiconductor device of this embodiment.
１…半導体チップ、２…積層セラミック基板、３…キャ
ップ、４…Ｐｂ−Ｓｎ半田、５…ＢＬＭ、６…Ｓｎ酸化
膜、７…レジスト、１０…半導体装置。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Multilayer ceramic substrate, 3 ... Cap, 4 ... Pb-Sn solder, 5 ... BLM, 6 ... Sn oxide film, 7 ... Resist, 10 ... Semiconductor device.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/12 Ｈ０１Ｌ 23/12 Ｆ (72)発明者 林田 哲哉 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical indication location H01L 23/12 H01L 23/12 F (72) Inventor Tetsuya Hayashida 2326 Imai, Ome, Tokyo Hitachi Device Development Center
Claims (2)
接続するための半田バンプの形成方法であって、前記半
導体チップの能動素子面にバンプ用の半田を定着させ、
その半田を溶融して基板と接続し、その接続後にその半
田の表面を加熱もしくはリフローにより酸化することか
らなる半田バンプの形成方法。1. A method of forming a solder bump for flip-chip connecting a semiconductor chip to a substrate, wherein bump solder is fixed on the active element surface of the semiconductor chip.
A method for forming solder bumps, which comprises melting the solder, connecting it to a substrate, and oxidizing the surface of the solder by heating or reflowing after the connection.
ップ・チップ接続した半導体装置において、前記半田バ
ンプの表面にスズの酸化膜を形成したことを特徴とする
半導体装置。2. A semiconductor device in which a semiconductor chip is flip-chip connected to a substrate by solder bumps, wherein a tin oxide film is formed on the surfaces of the solder bumps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5290149A JPH07142491A (en) | 1993-11-19 | 1993-11-19 | Solder bump forming method and semiconductor device having bump formed by the method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5290149A JPH07142491A (en) | 1993-11-19 | 1993-11-19 | Solder bump forming method and semiconductor device having bump formed by the method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07142491A true JPH07142491A (en) | 1995-06-02 |
Family
ID=17752417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5290149A Pending JPH07142491A (en) | 1993-11-19 | 1993-11-19 | Solder bump forming method and semiconductor device having bump formed by the method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07142491A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118294A (en) * | 2000-04-24 | 2002-04-19 | Nichia Chem Ind Ltd | Flip chip type light-emitting diode and manufacturing method thereof |
| WO2008015731A1 (en) * | 2006-07-31 | 2008-02-07 | Fujitsu Limited | Soldering method and apparatus for mounting component on printed wiring board |
| JP2008533743A (en) * | 2005-03-16 | 2008-08-21 | インテル コーポレイション | Method of forming self-passivating interconnect and apparatus using the method |
| JP2010114880A (en) * | 2008-11-04 | 2010-05-20 | Samsung Electronics Co Ltd | Surface acoustic wave element, surface acoustic wave device and methods for manufacturing the same |
-
1993
- 1993-11-19 JP JP5290149A patent/JPH07142491A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002118294A (en) * | 2000-04-24 | 2002-04-19 | Nichia Chem Ind Ltd | Flip chip type light-emitting diode and manufacturing method thereof |
| JP2008533743A (en) * | 2005-03-16 | 2008-08-21 | インテル コーポレイション | Method of forming self-passivating interconnect and apparatus using the method |
| JP4777415B2 (en) * | 2005-03-16 | 2011-09-21 | インテル コーポレイション | Method of forming self-passivating interconnect and apparatus using the method |
| WO2008015731A1 (en) * | 2006-07-31 | 2008-02-07 | Fujitsu Limited | Soldering method and apparatus for mounting component on printed wiring board |
| JP2010114880A (en) * | 2008-11-04 | 2010-05-20 | Samsung Electronics Co Ltd | Surface acoustic wave element, surface acoustic wave device and methods for manufacturing the same |
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