JPH07134158A - Output buffer circuit for mos semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the erroneous operation by simultaneous operation at test with simple circuit structure and low power consumption. CONSTITUTION:In output stage, a first transfer gate 6 is interposed between a VDD-side CMOS transistor 4 and an output terminal 8, and a second transfer gate 7 is interposed between a GNDside CMOS transistor 5 and the output terminal 8. The first transfer gate 6 is driven by the reverse signal of a test mode signal, and the second transfer gate 7 is driven by its reverse signal, so that a voltage drop is caused in the first transfer gates 6, 7 in test mode to limit the output amplitude.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit formed by a CMOS semiconductor integrated circuit.

[0002]

2. Description of the Related Art In general, a test pattern of a tester for selecting a good product or a defective product of a semiconductor integrated circuit is limited to a test pattern length due to a restriction on the tester, and is designed to compress an actual operation. There is. However, since the compression operation is forced, an operation that does not occur in the actual operation of the semiconductor integrated circuit occurs, and there is a fear that an erroneous operation occurs during the selection by the tester.

Particularly, when a large number of output buffer circuits are formed in parallel in a CMOS semiconductor integrated circuit, a simultaneous operation in which the outputs of the output buffer circuits are simultaneously switched to a high level or a low level at the time of selection by the tester described above. May occur, exceeding the power supply capability of the power supply and causing a malfunction. Therefore, the conventional output buffer circuit of the CMOS semiconductor integrated circuit is provided with a measure for preventing malfunction due to simultaneous operation.

As a countermeasure against this, a delay gate or a test circuit is added to each output buffer circuit from the design stage or after manufacturing to logically shift the operation timing so that they do not operate simultaneously during the test. There is a method and a method of strengthening the power supply capacity and relaxing the simultaneous operation limit number.

The following is known as another prior art.

Japanese Unexamined Patent Publication (Kokai) No. 3-121617 (hereinafter referred to as "prior art 1") changes the driving capability of an output buffer by a signal from an external terminal, so that the output buffer cannot be found at the time of circuit design. A "CMOS integrated circuit" is disclosed in which fluctuation of the power supply due to operation is prevented.

Further, in Japanese Patent Laid-Open No. 2-179027 (hereinafter referred to as Prior Art 2), a circuit for controlling the output impedance is added to a buffer circuit using a CMOS inverter circuit so that a plurality of buffer circuits can be simultaneously operated. By detecting the operation and increasing its output impedance, L
An "output buffer circuit" is disclosed in which a large charging current between SI and an external load capacitance is suppressed.

Further, in Japanese Patent Laid-Open No. 62-249449 (hereinafter referred to as Prior Art 3), one delay time of a plurality of output circuit cells connected in parallel is made different from the other delay circuit cells.
A "semiconductor integrated circuit device" is disclosed which prevents a noise margin defect due to potential fluctuation of a power supply system.

[0009]

As described above, in the conventional output buffer circuit of the CMOS semiconductor integrated circuit,
Although measures have been taken to prevent malfunctions due to simultaneous operations that occur due to the compression operation during testing, this is accompanied by an increase in circuit scale and power consumption, so it is desirable to reduce circuit scale and save power. Was not very effective as a measure against.

The present invention has been made to solve the above problems, and has a simple circuit structure and low power consumption, and can prevent malfunction due to simultaneous operations during a test.
An object is to provide an output buffer circuit of a MOS semiconductor integrated circuit.

The invention of Prior Art 1 is intended to prevent malfunction of a plurality of output buffer circuits at the time of simultaneous operation by switching and using output buffers having different driving capabilities depending on evaluation ON and OFF. Since each output buffer circuit requires two output buffers, the circuit scale is expanded, which is contrary to the object of the present invention. In addition, prior art 2
The invention of (1) also requires a synchronous operation detection circuit and the like, so that the circuit scale is expanded similarly to the prior art 1. Further, in the invention of Prior Art 3, in order to increase the number of parallel output circuits, the delay time of each output circuit cell is made different in consideration of the simultaneous operation. However, the usage environment is different from that of the present invention.

[0012]

In order to achieve the above object, the present invention provides an output buffer circuit of a CMOS semiconductor integrated circuit composed of enhancement transistors in which a transmission signal is input to a control electrode and one of the controlled signals is controlled. First CMOS whose electrodes are connected to a first reference power line
The transistor and the first CMOS transistor have opposite characteristics, and the control electrode is connected to the control electrode of the first CMOS transistor, one controlled electrode is connected to the second reference power supply line, and the other controlled electrode is connected. The second CMOS transistor whose control electrode is connected to the other controlled electrode of the first CMOS transistor and serves as the output terminal of the input inverter circuit has the same characteristics as the first CMOS transistor, and the control electrode has the above-mentioned characteristics. A third CMOS transistor connected to the output terminal of the input inverter circuit and having one controlled electrode connected to the first reference power supply line;
It has a characteristic opposite to that of a MOS transistor, and the control electrode is the third
A fourth CMOS transistor connected to the control electrode of the CMOS transistor, one controlled electrode of which is connected to the second reference power supply line to form an output inverter circuit together with the third CMOS transistor; Transfer gate connected between the other controlled electrode of the CMOS transistor and the output terminal, and a second transfer gate connected between the other controlled electrode of the fourth CMOS transistor and the output terminal And a test mode control means for causing both the first and second transfer gates to have a voltage drop when the test mode is on, and for making the first and second transfer gates both conductive when the test mode is off. It was equipped and configured.

[0013]

In the output buffer circuit of the CMOS semiconductor integrated circuit having the above structure, the output buffer circuit is provided between the third CMOS transistor and the output terminal which form the output inverter circuit, and between the fourth CMOS transistor and the output terminal. The first and second transfer gates are turned on together when the test mode is turned on to cause a voltage drop to reduce the output amplitude, thereby parallelizing them at the time of selection on the CMOS semiconductor integrated circuit tester. The number of simultaneous operation limits of the plurality of output buffer circuits provided as above is relaxed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIGS. 1A and 1B show the structure of an output buffer circuit according to the present invention. In FIG.
The input terminal 1 is connected to each gate electrode of the P channel MOS transistor 2 and the N channel MOS transistor 3.

The drain electrodes of the P-channel MOS transistor 2 and the N-channel MOS transistor 3 are
Both P channel MOS transistor 4 and N channel M
It is connected to each gate electrode of the OS transistor 5, and each source electrode is connected to the power supply lines of VDD and GND, respectively.

The source electrode of the P-channel MOS transistor 4 is connected to the VDD power supply line, and the drain electrode is connected to the current input terminal of the first transfer gate 6. The drain electrode of the N-channel MOS transistor 5 is connected to the current output terminal of the second transfer gate 7, and the source electrode is connected to the GND power supply line. Further, the current output end of the first transfer gate 6 and the current input end of the second transfer gate 7 are both connected to the output terminal 8.

That is, in the above output buffer circuit, the transistors 2 and 3 and the transistors 4 and 5 are CMs.
An OS inverter circuit is configured and has an output buffer function by being connected in series.

In FIG. 3B, the test mode input terminal 9 is connected to the input terminal of the first CMOS inverter circuit 10, and the output terminal (φ-(-represents inversion) is output) of the first terminal. Is connected to the gate electrode of the transfer gate 6. Further, the output end of the inverter circuit 10 is connected to the input end of the second CMOS inverter circuit 11, and its output end (outputting φ) is connected to the gate electrode of the second transfer gate 7.

The operation of the above arrangement will be described below with reference to FIGS. 2 and 3.

First, in a normal operating state, the signal applied to the input terminal 1 is applied to the G by the pair of transistors 2 and 3.
It is inverted and amplified between ND and VDD, and further inverted and output between GND and VDD by the transistors 4 and 5.

Here, it is assumed that a low-level test mode signal is input to the test mode input terminal 9 to turn on the test mode. At this time, the output φ− of the first CMOS inverter circuit 10 becomes high level, and the output φ of the second CMOS inverter circuit 11 becomes low level. Therefore, the N channel side of the first transfer gate 6 is turned on and the P channel side is turned off, and the N channel side of the second transfer gate 7 is turned off and the P channel side is turned on.

As a result, a voltage drop Vt (= threshold voltage) occurs in the transfer gates 6 and 7. Therefore, the voltage of the output terminal 8 is GND +, as shown in FIG.
It changes between Vt and VDD-Vt.

Next, assume that a high-level test mode signal is input to the test mode input terminal 9 to turn off the test mode. At this time, the output φ− of the first CMOS inverter circuit 10 becomes low level, and the output φ of the second CMOS inverter circuit 11 becomes high level. Therefore, the first
The N-channel side of the transfer gate 6 is turned off, the P-channel side is turned on, and the N-side of the second transfer gate 7 is turned on.
The channel side is turned on and the P channel side is turned off.

As a result, the input and output terminals of the transfer gates 6 and 7 are rendered conductive. Therefore, the voltage of the output terminal 8 changes between GND and VDD as shown in FIG.

As described above, in the output buffer circuit having the above structure, the voltage of the output terminal 8 changes between GND and VDD when the test mode is off, but when the test mode is on, the P-channel MOS transistor is turned on. 4, the voltage drop V due to the transfer gates 6 and 7 connected to the drain electrodes of the N-channel MOS transistor 5, respectively.
t occurs, and the voltage of the output terminal 8 is GND + Vt to VDD−
Since it changes between Vt, the amplitude becomes smaller.

Therefore, when the test mode is turned on at the time of selection on the tester, the current flowing through the output terminal 8 becomes small, so that the limited number of simultaneous operations can be relaxed, thereby preventing malfunction due to simultaneous operations. be able to. In this case, since the entire circuit is formed by the CMOS circuit and the output amplitude in the test mode is reduced,
The circuit scale is extremely small and can be realized with low power consumption.

It is needless to say that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made without departing from the scope of the present invention.

[0029]

As described above, according to the present invention, it is possible to provide an output buffer circuit of a CMOS semiconductor integrated circuit which has a simple circuit configuration and low power consumption and which can prevent malfunction due to simultaneous operations during a test. be able to.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an output buffer circuit of a CMOS semiconductor integrated circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing an amplitude waveform of an output voltage when a test mode is turned on in the example.

FIG. 3 is a waveform diagram showing an amplitude waveform of an output voltage when the test mode is turned off in the example.

[Explanation of symbols]

 1 Input Terminal 2 P Channel MOS Transistor 3 N Channel MOS Transistor 4 P Channel MOS Transistor 5 N Channel MOS Transistor 6 First Transfer Gate 7 Second Transfer Gate 8 Output Terminal 9 Test Mode Input Terminal 10 First CMOS Inverter Circuit 11 Second CMOS inverter circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 19/0175

Claims (4)

[Claims] 1. An output buffer circuit of a CMOS semiconductor integrated circuit comprising enhancement transistors, wherein a transmission signal is input to a control electrode and one of the controlled electrodes is connected to a first reference power supply line. The CMOS transistor and the first CMOS transistor have opposite characteristics, the control electrode is connected to the control electrode of the first CMOS transistor, one controlled electrode is connected to the second reference power supply line, and the other is connected. The second CMOS transistor whose controlled electrode is connected to the other controlled electrode of the first CMOS transistor and serves as the output end of the input inverter circuit has the same characteristics as the first CMOS transistor, and the control electrode is A third connected to the output terminal of the input inverter circuit, one controlled electrode being connected to the first reference power supply line;
Of the CMOS transistor and the third CMOS transistor have opposite characteristics, the control electrode is connected to the control electrode of the third CMOS transistor, and one controlled electrode is connected to the second reference power supply line, A fourth CMOS transistor forming an output inverter circuit together with the third CMOS transistor; a first transfer gate connected between the other controlled electrode of the third CMOS transistor and an output terminal; Of the second transfer gate connected between the other controlled electrode of the CMOS transistor and the output terminal and the first and second transfer gates when the test mode is turned on. Test mode control means for bringing both the first and second transfer gates into a conductive state when turned off An output buffer circuit for a CMOS semiconductor integrated circuit, comprising: 2. The first and third CMOS transistors are P-channel type, the second and fourth CMOS transistors are N-channel type, and the test mode control means has a test mode input terminal having a first First and second inverter circuits are connected in series, the output terminal of the first inverter circuit is connected to the control electrode of the first transfer gate, and the output terminal of the second inverter circuit is connected to the second transfer gate. 2. The output buffer circuit of the CMOS semiconductor integrated circuit according to claim 1, wherein the output buffer circuit is connected to the control electrode. 3. The first and second inverter circuits are CM
The output buffer circuit of the CMOS semiconductor integrated circuit according to claim 2, wherein the output buffer circuit is formed of an OS semiconductor. 4. The test mode control means controls the control electrode of the first transfer gate so that the N channel side is turned on and the P channel side is turned off when the test mode is turned on, and the N channel side is turned on when the test mode is turned off. The control electrode of the second transfer gate is connected so that it is turned off and the p-channel side is turned on. The control electrode of the second transfer gate is turned on when the test mode is on, the n-channel side is turned off, the p-channel side is turned on, and the test mode is turned on. 2. The output buffer circuit of a CMOS semiconductor integrated circuit according to claim 1, wherein the output buffer circuit is connected to the test mode input terminal so that the N-channel side is turned on and the P-channel side is turned off when it is turned off.