JPH07131346A - A/d converter - Google Patents

Abstract

PURPOSE:To improve the S/N of a signal with a small-scaled circuit after external noise is excluded. CONSTITUTION:An A/D converter 11 converts an analog input IN of one bit to the digital signal of (i) bits with a clock CK. A register group 13 stores the digital data of (i) bits resulting from (n) times of conversion by the A/D converter 11. A data processing circuit 14 calculates the maximum or minimum value of (n) pieces of data stored in the register group 13 or occasionally the average of data. Then, an analog/digital conversion result OUT with noise eliminated is outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an analog circuit of an integrated circuit.
A digital converter, particularly A having a noise removal circuit
It relates to a D converter.

[0002]

2. Description of the Related Art Generally, in an analog-digital converter (hereinafter referred to as an AD converter), when noise is generated externally, the noise is converted and a noise code is output. Therefore, in a set equipped with an AD converter, external noise may cause malfunction.
It is necessary to add a noise prevention circuit before and after the D converter. However, even if a sufficient noise removal circuit is added,
It was very difficult to eliminate the noise caused by the instantaneous fluctuation of the power source and the external physical shock regardless of the magnitude.

In addition, in the oversampling technique and the SDM technique (delta sigma modulation) used in the field of digital audio in recent years, a conversion frequency band exists in the AD converter, and noise outside the band is removed. However, the noise removal frequency band cannot be changed, and it was necessary to redesign the AD converter for application to a set of different applications.

Moreover, the circuits of these SDM AD converters are complicated and the circuit scale is also enormous. This is a cause of increasing the chip size depending on the LSI, which raises the cost of the chip.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of such a situation as described above, and an object thereof is (1) AD for performing AD conversion with external noise removed.
(2) to provide a high-precision AD converter at low cost by enabling a small-scale circuit to improve the S / N ratio of a signal after external noise is eliminated, (2) 3) To provide an inexpensive AD converter that can easily control the frequency band of noise to be removed according to the application.

[0006]

The AD converter according to the first aspect of the present invention is an A / D converter for converting an analog signal into a digital signal.
A D converter, characterized by comprising means for outputting a median value from three AD conversion results.

The frequency of the clock used for the conversion may be variable.

An AD converter according to the second invention is an AD converter for converting an analog signal into a digital signal, and means for performing the conversion a plurality of times four times or more, and a maximum value and a minimum value are excluded from the conversion result. Means for averaging the results and outputting the results.

The frequency of the clock used for the conversion may be variable.

[0010]

According to the first aspect of the present invention, for the conversion result output once, only the result of the median value is output as the conversion result from the conversion results of three times. Thereby, external noise can be eliminated.
Further, by making the frequency of the clock used for conversion variable, the frequency band of noise to be removed can be controlled according to the application.

According to the second aspect of the present invention, the results obtained by removing the maximum value and the minimum value from the AD conversion results of four or more times are added, and the result is divided by the number of additions and the result is output. This eliminates external noise and further improves the S / N ratio of the signal. Further, by making the frequency of the clock used for conversion variable, the frequency band of noise to be removed can be controlled according to the application.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of an AD converter having a noise removing circuit according to the first and second inventions.

IN is an analog input of the AD converter, and OUT is a digital output of the analog-digital conversion result. In the figure, 11 is a normal i-bit AD converter, which converts a 1-bit analog input IN into an i-bit digital signal by a clock CK. AD
The noise removing circuit 12 of the converter comprises a register group 13 and a data processing unit 14. The register group 13 is a memory or a register group, and has a configuration of i bits and n stages.
The register group 13 has i converted by the AD converter 11 n times.
Accumulate bits of digital data. Data processing unit 14
Has a function of obtaining a maximum value or a minimum value of n pieces of data accumulated in the register group 13 and a function of calculating an average of the data in some cases. That is, this is a part for performing arithmetic processing on one i-bit output to be output to OUT as a conversion result of this system from n i-bit data.

The AD converter configured as described above operates as follows. The AD converter 11 converts the 1-bit analog input IN into an i-bit digital signal by the clock CK. The register group 13 stores i-bit digital data converted by the AD converter 11 n times. The data processing unit 14 obtains the maximum value and the minimum value of the n pieces of data accumulated in the register group 13 and, in some cases, calculates the average of the data to obtain the noise-removed analog / digital conversion result OUT. Output.

Next, FIG. 2 shows an embodiment of the noise removing circuit of the AD converter according to the first invention. In the figure, A
Is i-bit digital data after digital conversion,
OUT is a digital conversion result with noise removed.

Further, CK is a conversion clock, and three pulses are generated for a series of conversions in this system.
AD conversion is performed once for the clock pulse. Therefore, the data A converted by the AD converter 11 is input to the D input of the D flip-flop 202 every one clock pulse. PR is a preset signal, which is used when initializing a series of conversions of this system (or
It is a pulse that occurs after the conversion is completed and until the next conversion).

CK2 is a pulse generated after the conversion data is input to the D input of the D flip-flop 202 three times, and CL is a clock for latching the outputs of the transfer gates 212 to 214 by the D flip-flop 208. Is.

Reference numerals 201 to 203 and 208 are D-type flip-flops, 204 and 205 are digital comparators, and 206, 207 and 209 to 211 are AND.
Gates 212 to 214 are transfer gates. Since the data in this figure are all i bits, the D flip-flops 201 to 203 and 208 excluding the digital comparators 204 and 205, the AND gates 206 and 2
07, 209-211, transfer gate 212-
214 has an i-bit configuration.

The signal A is connected to the D input of the D flip-flop 202. The clock CK is connected to the CK input of the D flip-flop 202, the input of the AND gate 206, and the input of the AND gate 207. The preset signal PR is the S input of the D flip-flop 201,
It is connected to the R input of the D flip-flop 208 and the R input of the D flip-flop 203. The Q output of the D flip-flop 202 is the D flip-flop 201.
Of the digital comparator 204, the negative input of the digital comparator 204, the negative input of the D flip-flop 203, the positive input of the digital comparator 205, and the transfer gate 213.
Connected to the input of. The Q output of the D flip-flop 201 is connected to the + input of the digital comparator 204 and the input of the transfer gate 212. The Q output of the D flip-flop 203 is connected to the-input of the digital comparator 205 and the input of the transfer gate 214. AND gate 206
Is connected to the CK input of the D flip-flop 201. The output of the AND gate 207 is connected to the CK input of the D flip-flop 203. The output of the digital comparator 204 is the input of the AND gate 206, A
It is connected to the input of the ND gate 209, the negative input of the AND gate 210, and the negative input of the AND gate 211. The output of the digital comparator 205 is the input of the AND gate 207, the negative input of the AND gate 209, A
It is connected to the negative input of the ND gate 210 and the input of the AND gate 211. The signal CK2 is the AND gate 209
Input, AND gate 210 input, AND gate 21
1 connected to the input. The output of the AND gate 209 is connected to the gate input of the transfer gate 212. The output of the transfer gate 212 is connected to the D input of the D flip-flop 208. The output of the AND gate 210 is connected to the gate input of the transfer gate 213. Transfer gate 213
Is connected to the D input of D flip-flop 208. The output of the AND gate 211 is connected to the gate input of the transfer gate 214. The output of the transfer gate 214 is connected to the D input of the D flip-flop 208. The signal CL is connected to the CK input of the D flip-flop 208. The Q output of the D flip-flop 208 outputs the signal OUT.

The operation of this circuit is as follows. First, from the preset signal PR, the D flip-flop 20
1 is set and D flip-flops 203 and 208 are reset. Next, the i-bit conversion data A is input to the D input of the D flip-flop 202 three times. At that time, in the digital comparators 204 and 205, the Q output of the D flip-flop 202 and D
A digital comparison is performed with the Q output of the flip-flop 201, and a digital comparison is performed with the Q output of the D flip-flop 202 and the Q output of the D flip-flop 203. As a result, at the second clock pulse CK, the maximum value of the data is stored in the D flip-flop 203 and the minimum value of the data is stored in the D flip-flop 201. The third data is input to the D input of the D flip-flop 202 at the third clock, and is selected by one of the AND gates 209 to 211 and the transfer gate selected by the clock CK2, and the D flip-flops 201 to 203 are selected. The median value of the two is input to the D flip-flop 208. As a result of the above series of processing, the median value of the three conversion data A is the signal O.
It will be output as UT.

Next, FIG. 3 shows an embodiment of the noise removing circuit of the AD converter according to the second invention.

As in FIG. 2, A is the i-bit digital data of digital conversion, and OUT is the output of the result. 20
1 to 203, J1, J2, ..., Jn, and 305 are D-type flip-flops, 204 and 205 are digital comparators, 206 and 207 are AND gates, 301 and 302 are adders, and 303 is a subtractor. Three
Reference numeral 04 is a divider (a shift register can be used depending on the value of n-1).

CK is a conversion clock, and n pulses are generated for a series of conversions in this system.
AD conversion is performed once for each clock pulse. Therefore, the data converted from A is D every clock.
It is input to the D input of the flip-flop 202. PR is a preset signal, which is a pulse generated at the time of initialization of a series of conversions of this system (or after completion of conversion and before the next conversion).

CL is a clock for latching the output of the divider 304 in the D flip-flop 305. Here, since the data in this figure are all i bits, the digital comparators 204 and 205 and the adders 301 and 3
02, the subtracter 303, and the D flip-flops 201 to 203, J1 to Jn, and 305 excluding the divider 304 are i
It has a bit configuration.

The signal A is connected to the D input of the D flip-flop 202. The clock CK is a D flip-flop 202, CK inputs of J1 to Jn, and an AND gate 206
And 207. The preset signal PR is connected to the S input of the D flip-flop 201 and the R input of the D flip-flop 203. The Q output of the D flip-flop 202 is the D flip-flop 201.
Of the D comparator, the negative input of the digital comparator 204, the D input of the D flip-flop 203, the positive input of the digital comparator 205, the D flip-flop J1, and the input of the adder 302. The Q output of the D flip-flop 201 is connected to the + input of the digital comparator 204 and the input of the adder 301. D
The Q output of the flip-flop 203 is connected to the-input of the digital comparator 205 and the input of the adder 301. The output of the AND gate 206 is connected to the CK input of the D flip-flop 201. The output of the AND gate 207 is connected to the CK input of the D flip-flop 203. The output of the digital comparator 204 is connected to the input of the AND gate 206. The output of the digital comparator 205 is connected to the input of the AND gate 207. The Q outputs of J1 to Jn are adders 30
It is connected to two inputs. The Q outputs of J1 to Jn-1 are connected to J2 to Jn, respectively. The output of the adder 302 is connected to the + input of the subtractor 303. The output of the adder 301 is connected to the-input of the subtractor 303. The output of the subtractor 303 is connected to the input of the divider 304. The output of the divider 304 is the D flip-flop 3
05 D input.

The operation of this circuit is as follows. First, the D flip-flop 201 is set and the D flip-flop 203 is reset by the PR signal.
Next, from the signal A, i-bit conversion data is input n times. At each time, digital comparison between the Q output of the D flip-flop 202 and the Q output of the D flip-flop 201 and digital comparison of the Q output of the D flip-flop 202 and the Q output of the D flip-flop 203 are performed in the digital comparators 204 and 205, respectively. Done. That is, the Q output of the D flip-flop 202 and the Q output of the D flip-flop 201 are compared, and small data is sent to the D flip-flop 201 and the D flip-flop 2
The Q output of 02 and the Q output of the D flip-flop 203 are compared, and large data is stored in the D flip-flop 203. Also, the D flip-flops J1, J2, ...
Data is sequentially stored in Jn. As a result, when the data is input n times from the signal A, all the data are accumulated in the D flip-flops J1, J2, ..., Jn, and at the same time, the minimum value is stored in the D flip-flop 201 and the maximum value is stored in the D flip-flop 201. It remains in the D flip-flop 203. By passing these results through the adders 301 and 302 and the subtractor 303, the total sum obtained by removing the maximum and minimum from the n pieces of data is obtained, and K
It is possible to take an average by performing 1 / (n-2) with the divider.

Next, FIG. 4 shows a modification of the embodiment of the noise removing circuit of the AD converter according to the second invention shown in FIG.

FIG. 4 shows the n registers J1 and J of FIG.
2, ..., Jn is eliminated, the amount of logic is considerably reduced, and the circuit scale does not depend on the number n of conversions.

The signal A is connected to the D input of the D flip-flop 202. The clock CK is connected to the CK inputs of the D flip-flops 202 and 401 and the AND gates 206 and 207. The preset signal PR is the S input of the D flip-flop 201 and the D flip-flop 4
01 R input and R of D flip-flop 203
Connected to input. Q of the D flip-flop 202
The output is the D input of the D flip-flop 201, the negative input of the digital comparator 204, and the D flip-flop 203.
Of the digital comparator 205, the + input of the digital comparator 205, and the input of the adder 302. The Q output of the D flip-flop 201 is connected to the + input of the digital comparator 204 and the input of the adder 301. D
The Q output of the flip-flop 203 is connected to the-input of the digital comparator 205 and the input of the adder 301. The output of the AND gate 206 is connected to the CK input of the D flip-flop 201. The output of the AND gate 207 is connected to the CK input of the D flip-flop 203. The output of the digital comparator 204 is connected to the input of the AND gate 206. The output of the digital comparator 205 is connected to the input of the AND gate 207. The output of the adder 302 is connected to the D input of the D flip-flop 401. The Q output of the D flip-flop 401 is connected to the input of the adder 302 and the + input of the subtractor 303. The output of the adder 301 is connected to the-input of the subtractor 303. Subtractor 30
The output of 3 is connected to the input of divider 304. The output of the divider 304 is connected to the D input of the D flip-flop 305.

The operation of this circuit is as follows. First, the D flip-flop 201 is set and the D flip-flop 203 is reset by the PR signal.
Next, from the signal A, i-bit conversion data is input n times. At each time, digital comparison between the Q output of the D flip-flop 202 and the Q output of the D flip-flop 201 and digital comparison of the Q output of the D flip-flop 202 and the Q output of the D flip-flop 203 are performed in the digital comparators 204 and 205, respectively. Done. That is, the Q output of the D flip-flop 202 and the Q output of the D flip-flop 201 are compared, and small data is sent to the D flip-flop 201 and the D flip-flop 2
The Q output of 02 and the Q output of the D flip-flop 203 are compared, and large data is stored in the D flip-flop 203. The D flip-flop 401 accumulates the data obtained by sequentially adding the Q output of the D flip-flop 202 by the adder 302. As a result, when data is input n times from the signal A, the sum of all data is accumulated in the D flip-flop 401, and at the same time, the minimum value is in the D flip-flop 201 and the maximum value is in the D flip-flop 20.
It will remain in 3. These results are added to the adders 301 and 30.
2. By passing through the subtractor 303, the maximum and minimum are removed from the n pieces of data, and the K divider 1 / (n-
You can do 2) and take the average.

Next, FIG. 5 shows another modification of the embodiment of the noise removing circuit of the AD converter according to the second invention shown in FIG.

FIG. 5 shows an adder 301 and a subtractor 303 shown in FIG.
, And AND gates 209 to 211 and transfer gates 212 to 214 obtain similar results. As a result, the circuit scale is significantly reduced, and the circuit scale does not depend on the number of conversions n. Moreover, by setting the number of conversions n to 2 ⁱ −2, the K divider is realized by a simple register, and the circuit has a very small configuration.

The signal A is connected to the D input of the D flip-flop 202. The clock CK is connected to the CK input of the D flip-flop 202, the input of the AND gate 206, and the input of the AND gate 207. The preset signal PR is the S input of the D flip-flop 201,
It is connected to the R input of the D flip-flop 208 and the R input of the D flip-flop 203. The Q output of the D flip-flop 202 is the D flip-flop 201.
Of the digital comparator 204, the negative input of the digital comparator 204, the negative input of the D flip-flop 203, the positive input of the digital comparator 205, and the transfer gate 213.
Connected to the input of. The Q output of the D flip-flop 201 is connected to the + input of the digital comparator 204 and the input of the transfer gate 212. The Q output of the D flip-flop 203 is connected to the-input of the digital comparator 205 and the input of the transfer gate 214. AND gate 206
Is connected to the CK input of the D flip-flop 201. The output of the AND gate 207 is connected to the CK input of the D flip-flop 203. The output of the digital comparator 204 is the input of the AND gate 206, A
It is connected to the input of the ND gate 209, the negative input of the AND gate 210, and the negative input of the AND gate 211. The output of the digital comparator 205 is the input of the AND gate 207, the negative input of the AND gate 209, A
It is connected to the negative input of the ND gate 210 and the input of the AND gate 211. The signal CK2 is the AND gate 209
Input, AND gate 210 input, AND gate 21
1 connected to the input. The output of the AND gate 209 is connected to the gate input of the transfer gate 212. The output of the transfer gate 212 is the adder 3
02 input. The output of the AND gate 210 is connected to the gate input of the transfer gate 213. The output of the transfer gate 213 is connected to the input of the adder 302. The output of the AND gate 211 is connected to the gate input of the transfer gate 214. The output of the transfer gate 214 is connected to the input of the adder 302. The output of the adder 302 is connected to the D input of the D flip-flop 208.
The signal CL is connected to the CK input of the D flip-flop 208. The Q output of the D flip-flop 208 is connected to the input of the adder 302 and the input of the divider 304. The output of the divider 304 is connected to the D input of the D flip-flop 305. The Q output of the D flip-flop 305 outputs the signal OUT.

The operation of this circuit is as follows. First, from the preset signal PR, the D flip-flop 20
1 is set and D flip-flops 203 and 208 are reset. Next, the i-bit conversion data A is input to the D input of the D flip-flop 202 n times. At that time, in the digital comparators 204 and 205, the Q output of the D flip-flop 202 and D
A digital comparison is performed with the Q output of the flip-flop 201, and a digital comparison is performed with the Q output of the D flip-flop 202 and the Q output of the D flip-flop 203. As a result, at the second clock pulse CK, the maximum value of the data is stored in the D flip-flop 203 and the minimum value of the data is stored in the D flip-flop 201. From the 3rd clock to the nth clock, the AND gates 209 to 2 are driven by the clock CK2.
It is selected by any one of 11 and the transfer gate selected by it, the conversion result is added n-2 times by the adder 302, and the result is stored in the D flip-flop 208. Further, the average is calculated in the divider 304, stored in the D flip-flop 305, and output as the signal OUT.

Next, FIG. 6A shows a block diagram of a clock CK generator used in the first and second inventions.

Reference numeral 601 denotes an oscillator, 602 divides the oscillation to set the pulse width, and 603 denotes a counter, which sets the number of the pulses. Frequency divider 602
Output, the output of the counter 603, and the conversion request signal C
LK is connected to the input of the AND gate 604, and the AND gate 604 outputs the clock CK. Here, the oscillator 601 may be built in the LSI or externally attached. The values of the frequency divider 602 and the counter 603 may be fixed by the LSI, but can be set by a program from the outside.

As shown in FIG. 6 (b), the frequency divider 602 is used during the period when the clock is high from the rise of the conversion request signal CLK (which may be a clock given to a general AD converter which is generally commercially available at present) from the outside. The number of times the pulse CK having the set pulse width t is set by the counter 603 n
Is output once. As a result, the pulse width and the number of pulses of the conversion clock can be arbitrarily changed. By combining with the first and second inventions, the pulse width of the clock determines the noise frequency band at the time of noise removal, and the number of pulses is the average number in the second invention, that is,
It is involved in improving the S / N ratio.

Further, the first aspect of the present invention is used with FIG. 4 or FIG. 5 of the second aspect of the invention to eliminate the noise component and AD the programmable S / N ratio according to the application.
It is possible to supply a converter system.

[0040]

The AD converter according to the first aspect of the present invention is an AD converter for converting an analog signal into a digital signal and has means for outputting a median value from three AD conversion results. An AD converter that performs the removed AD conversion can be provided.

Further, since the frequency of the clock used for the conversion may be variable, it is possible to provide an inexpensive AD converter in which the frequency band of noise to be removed can be easily controlled according to the application.

An AD converter according to the second invention is an AD converter for converting an analog signal into a digital signal, and means for performing the conversion a plurality of times four times or more, and a maximum value and a minimum value from the conversion result. Since a means for averaging the results and outputting the results is provided, it is possible to provide an inexpensive and highly accurate AD converter that improves the S / N ratio of the signal after removing external noise.

Moreover, since the frequency of the clock used for the conversion may be variable, it is possible to provide an inexpensive AD converter in which the frequency band of noise to be removed can be easily controlled according to the application.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a noise removal circuit of an AD converter according to the first and second inventions.

FIG. 2 is an embodiment of the noise removing circuit of the AD converter according to the first invention.

FIG. 3 is an embodiment of the noise removing circuit of the AD converter according to the second invention.

FIG. 4 is a modification of the embodiment of the noise removing circuit of the AD converter according to the second invention.

FIG. 5 is another modification of the embodiment of the noise removing circuit of the AD converter according to the second invention.

FIG. 6 is a clock CK used in the first and second inventions.
2 is a block diagram of the generator of FIG.

[Explanation of symbols]

201-203, 208, J1-Jn, 305 D-type flip-flop 204, 205 Digital comparator 206, 207, 209-211 AND gate 212-214 Transfer gate 301, 302 Adder 303 Adder-subtractor 304 Divider (1 / n -2) 601 oscillator 602 frequency divider 603 counter 604 AND gate

Claims (4)

[Claims] 1. An AD converter for converting an analog signal into a digital signal, comprising means for outputting a median value from three AD conversion results. 2. The AD converter according to claim 1, wherein a frequency of a clock used for the conversion is variable. 3. An AD converter for converting an analog signal into a digital signal, means for performing the conversion a plurality of times four times or more, and means for averaging and outputting the result obtained by removing the maximum value and the minimum value from the conversion result. And A
D converter. 4. The AD converter according to claim 3, wherein the frequency of the clock used for the conversion is made variable.