JP4496493B2 - DA converter and AD converter - Google Patents

Description

  The present invention comprises a pulse density modulation type DA converter having an offset amount and gain adjustment function and having an arbitrary resolution whose resolution does not depend on the power of 2 and the pulse density modulation type DA converter. The present invention relates to a pulse density modulation type AD converter.

More specifically, a simple configuration having a simple configuration of an adder / subtracter having a plurality of registers, a carry signal output, and a timing control circuit without using a complicated and large-scale logic circuit such as a multiplication circuit or a division circuit. Further, the present invention relates to a pulse density modulation type DA converter that has an output offset amount and magnification adjustment function and has an arbitrary resolution that does not depend on 2 to the nth power, and is configured only by a small-scale digital circuit. The present invention relates to an AD converter configured using a type DA converter.

  Most of the measurement and control systems are operated over a long period of time, and many models have a long product life of 5 to 10 years. As shown in Fig. 2, when a processor with built-in AD converter or DA converter is used on the measurement / control system printed circuit board, an external high-precision AD converter or DA converter is installed in addition to the processor. There are very many cases. However, a processor incorporating an AD converter or DA converter requires a larger chip area than a processor with a simple specification not incorporating these, and the number of processors that can be manufactured from one wafer is reduced. However, it has the disadvantage that the price is high. In addition, because of the need to reduce the price even if the specifications become complicated, it is often the case that processors with a reduced cost by limiting the chip area to a special specification are sold in series. Therefore, the mass production effect is difficult to obtain, and the competitiveness is significantly lower than that of a general-purpose processor. As a result, there is a higher probability that production will be discontinued in the first few years after development. In other words, the long-term stable supply of devices is not performed, so that the product life is shortened and the development cost increases. Furthermore, this phenomenon is more prominent in high-precision dedicated AD converters and DA converters, and is an important issue from the viewpoint of maintaining manufacturing technology.

  In addition, when adding specifications or improving the performance of a product, there are cases where the number of AD converters or DA converters incorporated in the chip of the processor used and the bit resolution are insufficient. In this case, the cost may not match due to a change in hardware such as replacement with a higher-order chip or addition of an external IC and a change in software associated therewith. In addition, if a fine adjustment element of amplitude or offset is included for each measurement range as the function increases, a multiplexer and an electronic volume are required, and the electronic circuit becomes complicated.

As a method of realizing DA conversion without using a dedicated DA converter provided by the manufacturer, a resistor network called R-2R ladder resistor circuit for voltage division is connected to the general-purpose digital output port as shown in Fig. 3-1. Design techniques for configuring a DA converter with only general-purpose components, or connect a low-pass filter (LPF) to the pulse width modulation (PWM) output as shown in Fig. 3-2 A design technique for configuring a DA converter is known. However, when a ladder resistor is used, there is a drawback that a digital output port corresponding to a bit width is required to construct a DA converter for one channel. The DA resolution is limited to about 8 bits when the ladder resistance is made of discrete components, and about 10 bits is a practical range even when a dedicated ladder resistance array is used. In the technique using the pulse width modulation output, it can be used as a DA converter by changing the duty ratio of the pulse and passing it through a low-pass filter (low-pass filter: LPF) to extract a DC component. Although the number of DA outputs equal to the number of PWM channels can be obtained, there are many processors with a pulse duty ratio of about 10 bits, and in PWM, the information band is close to the carrier frequency of the pulse, so the SN ratio is bad. there were.
Also, as a problem common to all DA conversion methods and AD conversion methods, since the normal resolution is a unit of 2 n determined by the bit width n, a decimal number such that the resolution of one digit is exactly 1 mV or 100 μA. For example, a dedicated reference voltage source such as 2.047V is required in order to make the unit easy to represent.
JP-A-6-112833 Japanese Patent Laid-Open No. 6-112934 Japanese Unexamined Patent Publication No. 7-86948

  The problem to be solved is that the product life is inevitably shortened as a result of depending on the dedicated AD converter and DA converter, and the AD converter and DA converter are occupied by analog circuits having a large chip occupation area. Point, the point that the minimum resolution cannot be set to an arbitrary interval, the point that the output offset amount cannot be changed with the resolution fixed, and the large and complex external circuit to change the output offset amount or magnification Is a point that is necessary. In other words, the challenge is to realize a DA converter that can change the resolution, output offset amount, and magnification, with a small and simple digital circuit as the main component, and a simple general-purpose external analog circuit. It is to be. Furthermore, an AD converter having the DA converter as a constituent element is realized. That is, it is to realize an AD converter and a DA converter having a general-purpose digital circuit as a main component.

  The present invention has been made in view of these circumstances, and the pulse density modulation type is used in order to realize a DA converter having a good S / N ratio while retaining an external circuit as an analog circuit composed of only general-purpose components. The main features are that the DA conversion method is adopted and that the pulse density modulation type DA converter has a resolution that can be arbitrarily set and a structure that can change the output offset amount and the magnification. The most important feature is that the AD converter is configured by using the pulse density type DA converter, so that the resolution can be arbitrarily set and the offset and magnification can be changed.

  The pulse density modulation type DA converter according to claim 1 of the present invention is an increment register for storing a DA output target value 11 or a DA output correction target value 13 obtained by adding the DA output target value 11 and the output offset value 12. 1, the operation result storage register 2 for storing the operation result value 14, the output range specification register 3 for storing the DA output range specification value 15, the value supplied from the increment register 1 and the operation result storage register 2 are added. Then, the addition function 21 that outputs the addition value 16 and the subtraction that outputs the subtraction value 17 by subtracting the DA output range designation value 15 supplied from the output range designation register 3 from the value supplied from the operation result storage register 2 The adder / subtractor 4 having the function 22 and outputting the carry signal 18 and the logical value holding and holding the carry signal 18 after the subtraction function 22 is executed. Alternatively, the DA output register 5 that outputs the inverted logical value as the pulse density modulation output 19 and the control unit 6 that controls the timing of alternately executing the addition function 21 and the subtraction function 22 are provided. When executing 21, the addition value 16 is controlled to be stored in the operation result storage register 2 as the operation result value 14, and when the subtraction function 22 is executed, the subtraction value 17 is a positive value based on the carry signal 18. A function of converting the DA output target value 11 or the DA output correction target value 13 into a pulse density by performing control to store the subtraction value 17 as the calculation result value 14 in the calculation result storage register 2 when it is determined that there is The signal is converted into a pulse density only by changing the DA output range designation value without multiplying the DA output target value 11 or the DA output correction target value 13 by the magnification. A function for changing the magnification at the time, a function for setting the DA output range to an arbitrary natural number determined by the DA output range specification value 15, and a function for shifting the DA output by the offset amount specified by the output offset value 12 It is characterized by realization.

  The pulse density modulation type AD converter according to claim 2 of the present invention outputs the pulse density modulation type DA converter 31 according to claim 1 and the pulse density modulation type DA converter 31 according to claim 1. A noise shaping filter 32 that receives the supply of the output pulse 41 and cuts or attenuates the high-frequency component of the output pulse 41, and an analog comparator that receives the supply of the analog input and the output of the noise shaping filter 32 and performs logic determination to determine the size. 33 and an arithmetic unit 34 that increases / decreases the DA output target value 11 based on the logic output of the analog comparator 33 and supplies it to the pulse density modulation type DA converter 31 and outputs it as an AD conversion value, and performs AD conversion It is characterized by.

  The pulse density modulation type AD converter according to claim 3 of the present invention outputs the pulse density modulation type DA converter 31 according to claim 1 and the pulse density modulation type DA converter 31 according to claim 1. A noise shaping filter 32 that receives supply of the output pulse 41 and cuts or attenuates a high frequency component of the output pulse 41, an integrator 35 that receives and supplies the analog input and the output of the noise shaping filter 32, and an integrator 35 An analog comparator 33 that receives the output and outputs a binary logic based on whether the integral value is positive or negative, and pulse density modulation by increasing or decreasing the DA output target value 11 based on the logic output of the analog comparator 33 A calculation unit 36 that supplies to the DA converter 31 and outputs it as an AD conversion value is provided to perform AD conversion. It is characterized in.

  With the configuration described in claim 1 of the present invention, sufficient linearity can be obtained by equally dividing the DA output range into an arbitrary natural number determined by the DA output range designation value 15 with a simple and small-scale digital circuit. A pulse density modulation type D / A converter can be configured, and the output offset amount and magnification can be changed. Therefore, in order to convert to an analog amount with a high S / N ratio, noise consisting of external general-purpose analog components There is an advantage that only a shaping filter is required. A circuit necessary for converting the DA output target value 11 or the DA output correction target value 13 obtained by adding the DA output target value 11 and the output offset value 12 into a digital signal by pulse density modulation includes a plurality of registers, an addition / subtraction circuit, and the like. Since it can be configured by a digital circuit having only a simple timing control circuit, there is an advantage that a DA conversion function can be added without taking up a large chip occupation area. The general-purpose digital output port of a general-purpose processor can be used as a DA converter by using time-division hardware such as memory or registers, arithmetic units, and digital output ports, which are the elements that make up the processor There is an advantage of becoming. In addition to software, the means for time-sharing use of the hardware has recently been developed as devices capable of describing hardware logic such as large-scale FPGA (Field Programmable Gate Array) and CPLD (Complex Programmable Logic Device). In addition to incorporating functions as a processor, it is also possible to incorporate the configuration according to claim 1, and there is an advantage that a compatible processor can be easily realized.

  With the configuration described in claim 2 of the present invention, only analog components necessary for converting an analog signal into a digital signal are a noise shaping filter and an analog comparator, and the AD input range is equally divided with an arbitrary resolution. There is an advantage that an AD converter with good linearity can be realized. Further, there is an advantage that the input range can be changed by giving an offset amount or a magnification. Some general-purpose one-chip processors incorporate an analog comparator. When the processor according to the second aspect of the present invention is implemented, the external circuit is only a noise shaping filter composed of general-purpose analog components. There is an advantage of being able to finish

  If it is the structure of Claim 3 of this invention, it will become the structure which added the integrator to the structure of Claim 2, and the advantage that AD converter which the accumulated value of AD conversion error approaches 0 is realizable. There is. Some general-purpose one-chip processors incorporate an analog comparator. When the processor according to the third aspect of the present invention is implemented, the external circuit is integrated with a noise shaping filter composed of general-purpose analog components and an integration circuit. There is an advantage that only a vessel is required.

  The inventor of the present application has intensively studied to solve the above problems.

First, many AD converters have built-in DA converters. First, it is important to realize a DA converter with arbitrary resolution, and pulse density modulation that does not require a special analog circuit. Focused on the method. However, when pulse density modulation is performed using an arithmetic unit having a bit width n, division processing or multiplication processing is required every time the setting of the DA output target value is changed. More specifically, when the DA output range designation value, that is, the resolution designation value is m, and the DA output target value is q, it is necessary to compute an increment value based on Equation 1 if the bit width of the computing unit is n. Arise. In order to perform this calculation with high accuracy, a calculation after the decimal point is necessary, so that the processing load is heavy and the circuit scale becomes large.

Therefore, the DA output target value q is cumulatively added for each pulse output clock, the remainder obtained by dividing the cumulative addition value sum by the resolution designation value m, that is, only the remainder component, is managed, and the timing at which the quotient increases, that is, the pulse is generated. He devised a method to detect the timing to make it happen. In this method, the bit width of the arithmetic unit needs to have a width that allows an operation that is at least twice as large as the DA output range specified value m. However, when the cumulative added value sum exceeds the DA output range specified value m, the cumulative addition is performed. By subtracting the DA output range specified value m from the value sum and limiting the DA output range specified value m so that it does not exceed the DA output range specified value m, the pulse output timing of pulse density modulation can be achieved by adding and subtracting without requiring multiplication or division in the calculation. You can get it.

Furthermore, if the DA output range specified value is changed to double while the DA conversion is performed by the above-described pulse density modulation method and a predetermined waveform is output, the pulse output density is reduced by half, and the DA output range specified value is set. I thought that changing the setting to a half value would double the output density of the pulse, and I confirmed it by experiment, changing the magnification only by changing the DA output range specification value without any changes to the sample value of the output waveform It was possible to confirm that the DA output range specification value and the magnification have a reciprocal relationship.

However, in the case of realizing a function generator using DDS (Direct Digital Synthesizer), in addition to the function of changing the frequency and output amplitude of the output waveform, that is, the magnification, a signal that gives an output offset to the pulse density and changes around a predetermined value May have to be output. In such a case, the output offset value can be changed by adding the output offset value to the DA output target value and maintaining the condition that the value always exists within the range of 0 to the DA output range specified value m. . In this way, a pulse density modulation type DA converter having the configuration described in claim 1 was completed.

Furthermore, the pulse density modulation type AD converter according to claim 2 and claim 3 is completed by using the pulse density modulation type DA converter according to the configuration of claim 1 as a constituent element.

Based on the above experiments, the present inventor has completed the present invention.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

  FIG. 1 shows a block diagram of a circuit according to an embodiment of the present invention. 1 is an increment register, 2 is an operation result storage register, 3 is a DA output range specification register, 4 is an adder / subtractor, 5 is a DA output register, and 6 is a control unit that controls the timing for alternately executing the addition function and the subtraction function. is there. In the increment register 1, a DA output target value 11 or a DA output target value 13 obtained by adding the DA output target value 11 and the output offset value 12 is stored. The DA output range designation register 3 stores a DA output range designation value 15. The control unit 6 adds the value stored in the increment register 1 and the value stored in the operation result storage register 2 and controls the addition function 21 for outputting the addition value 16 and stored in the operation result storage register 2. The timing for controlling the subtraction function 22 for subtracting the value stored in the DA output range designation register 3 from the obtained value and outputting the subtraction value 17 is alternately generated and repeated.

  At the timing of controlling the addition function 21, the adder / subtractor 4 is selected to operate as an adder. The value stored in the increment register 1 and the value stored in the operation result storage register 2 are supplied to the adder / subtracter and added, and the addition value 16 as the addition result is stored in the operation result storage register 2. Next, at the timing of controlling the subtraction function 22, an operation stored in the operation result storage register 2 in order to check whether or not a condition for increasing a quotient, which is a timing at which a pulse is generated by the execution of the addition function 21, is satisfied. It is checked whether or not the result 14 exceeds the DA output range specification value 15 stored in the DA output range specification register 3. At the timing of controlling the subtraction function 22, the adder / subtractor 4 is selected to operate as a subtractor. When the DA output range designation value 15 stored in the DA output range designation register 3 is subtracted from the computation result 14 stored in the computation result storage register 2, and the subtraction value 17 that is the computation result is a positive value, the computation is performed. This indicates that the operation result 14 stored in the result storage register 2 has exceeded the DA output range specification value 15 stored in the DA output range specification register 3, indicating that it is time to generate a pulse. Yes. On the contrary, when the subtraction value 17 as the operation result is a negative value, the operation result 14 stored in the operation result storage register 2 exceeds the DA output range specification value 15 stored in the DA output range specification register 3. This indicates that there is no timing, and it is not the timing for generating a pulse. That is, when the carry signal 18 of the adder / subtracter is not generated, it indicates that the calculation result 14 is a positive value and is a timing for generating a pulse. On the contrary, when the carry signal 18 of the adder / subtracter is generated, it indicates that the calculation result 14 is a negative value, and is a timing at which no pulse is generated. Therefore, when the subtraction function 22 is controlled, the logic of the carry signal 18 is inverted and held in the DA output register 5 to be output as the pulse density modulation output 19 and when the carry signal 18 is 0. The subtraction value 17 is stored in the operation result storage register 2 so that the operation result value 14 is always kept below the DA output range specified value 15.

For example, in the case of realizing a pulse density modulation type DA converter with 1 mV resolution with a logic circuit output that operates at a power supply voltage of 5 V, the operation is as follows. Since 1 mV resolution from 0.000 V to 5.000 V is a DA converter with 5001 gradations, 5000 is stored as the DA output range designation value 15. Increment register 1 is allowed to store values from 0 to 5000. Assuming that 1000 is stored in the increment register 1, the calculation result exceeds the DA output range designation value 15 every time the addition function 21 is executed five times, and the condition for generating a pulse is satisfied. A pulse is generated at a rate of once every five times, and the high frequency component is removed or reduced by an external noise shaping filter, which is converted into an analog amount and an output of 1.000 V is obtained.

As shown in FIG. 4, PWM (Pulse Width Modulation) is a pulse modulation method in which the basic cycle of the pulse is fixed and the duty cycle ratio is changed, whereas pulse density modulation PDM (Pulse Density Modulation). Is a pulse modulation method in which a 0 or 1 pulse appears for each basic clock and a numerical value is expressed by the appearance probability. Therefore, the pulse density modulation type DA converter has a feature that the resolution can be improved by obtaining the appearance probability from the accumulated pulse for a long time.

  FIG. 5 illustrates an embodiment of a noise shaping filter used for the purpose of removing or reducing high frequency components in a pulse density modulation type DA converter. When used as a DA converter with a bandwidth of about 1 Hz with almost no change, a simple filter composed of a resistor, a capacitor and a protection diode as shown in FIG. 5A can achieve sufficient performance. it can. FIG. 6 shows an example of an actual waveform when a pulse density modulation type DA converter is realized by using a digital output of a power supply voltage of 5 V with a DA output range designation value of 15 as 5 microseconds as a basic clock. The noise shaping filter uses the simple filter shown in FIG.

  The pulse density modulation type DA converter having the configuration of FIG. 1 can be configured not only by hardware such as FPGA and CPLD, but also by using a general-purpose processor as long as the basic clock has a specification of about 5 microseconds. It can also be realized by software. The embodiment of FIG. 1 does not depend on a dedicated DA converter, and a DA having sufficient and arbitrary resolution can be configured at a low cost even with a simple external noise shaping filter having about three passive components.

  FIG. 7 shows a pulse density modulation type DA converter having the configuration of FIG. 1 configured by a digital circuit with a power supply voltage of 3.3 V. The linearity is examined and the magnification is changed by changing the DA output range designation value 15. It is the experimental result which showed that it is possible. The result of measuring the output voltage of the simple filter of FIG. 5A with the DA output range designation value 15 set to 3300, the output offset value 12 changed to 0, and the DA output target value 11 changed at 100 pitches is shown in FIG. Is shown. Although high linearity was obtained, the voltage when the DA output target value 11 was 3300 was 3.290 V, and a slight error was confirmed due to restrictions on circuit constants. When the DA output range designation value 15 is changed to 3290 to correct this error, the voltage when the DA output target value 11 is 3290 is 3.290 V as shown by Port B (after correction) in FIG. Thus, a decrease in error was confirmed at all measurement points along the way. When the DA output range specification value 15 is changed to half of 1645, the magnification is doubled, and when the DA output range specification value 15 is doubled to 6580, the magnification is halved and the DA output range specification value 15 is set to It was confirmed that the magnification was reduced to 1/5 when the magnification was increased to 16450.

  In this example, it was confirmed that the magnification can be accurately changed only by changing the DA output range designation value 15 stored in the DA output range designation register 3 without adding external parts.

  FIG. 8 is a circuit block diagram of a normal DDS (Direct Digital Synthesizer). If a normal DA converter is used to obtain an analog output, it will be stepped like the waveform illustrated in FIG. However, in the embodiment according to the prior art, the total number of samples of the sine waveform is 512, and the resolution is 12 bits. In this example, if the amplitude of the output waveform is to be changed, the sample values of all the sine waveforms must be changed by multiplying them. Further, since the output resolution is limited to 12 bits, there is a drawback that the resolution with respect to the maximum amplitude of the sine waveform is deteriorated if the waveform amplitude is reduced. Since the output offset is in units of output resolution, for example, in order to shift the offset at a pitch of 1 mV, it is necessary to adjust by an external circuit so as to be 4.095 V at the maximum amplitude.

  On the other hand, when the DA converter in FIG. 8 is replaced with the pulse density modulation type DA converter having the configuration shown in FIG. 1, the waveform illustrated in FIG. 10 is obtained. The upper part of FIG. 10 is a digital signal output of pulse density modulation, and the lower part of FIG. 10 is an analog waveform when the noise shaping filter of FIG. 3-2 is used. It was confirmed that a waveform comparable to that of a normal DA converter was obtained.

  FIG. 11 illustrates an example of a three-phase DDS employing the pulse density DA converter according to claim 1. In the case of a DDS configured using a normal DA converter, if an attempt is made to change the amplitude of the output waveform without reducing the resolution, means for changing the magnification externally, such as an electronic volume and an amplifier, must be added. . A similar problem exists when changing the output offset. Also, if you want to change the amplitude or offset of the output waveform without adding an external circuit, you can either change the value by multiplying all the sample values of the defined sine waveform by the magnification, or in real time. It is necessary to perform multiplication processing with double precision. On the other hand, in the embodiment shown in FIG. 11, the magnification is changed only by changing the DA output range designation value 15 stored in the DA output range designation register 3 without changing any defined sine waveform data. It can be done. Further, even when the output offset is changed, there is an advantage that only the addition process for storing the DA output correction target value 13 obtained by adding the output offset value 12 to the DA output target value 11 in the increment register 1 is performed. FIG. 12 illustrates an example of a waveform in which the magnification is changed only by changing the DA output range designation value 15 without changing the original waveform data. Since the output of the pulse density modulation type DA converter is a logic signal, there is an advantage that a signal having an opposite phase can be easily obtained by using the inverted logic of the output signal.

The embodiment of FIG. 13 shows the configuration of a pulse density AD converter corresponding to claims 2 and 3. 13-1 supplies the output signal of the pulse density type DA converter 31 according to claim 1 as an analog input reference signal through the noise shaping filter of FIG. 3-1, and the reference signal and the analog input are supplied. By comparing with the analog comparator, it is possible to detect whether the current DA output target value 11 or the DA output correction target value 13 is larger or smaller than the analog input. Regarding the AD value search method, many algorithms are known, such as a binary search algorithm, a successive approximation search algorithm, a negative feedback type, and a variable step negative feedback type. An AD conversion value can be obtained by executing an arbitrary search algorithm by the calculation unit 34 not shown in FIG. Processing such as having an arbitrary resolution, limiting the input range, and changing the input magnification can be executed without increasing the circuit scale.
In the embodiment of FIG. 13-2, since the AD conversion error for a long time can be further reduced, a highly accurate AD converter can be realized.

  The embodiment of FIG. 14 is an actual circuit block diagram when the pulse density modulation type DA converter according to claim 1 is constituted by a digital logic circuit, and FIG. 15 is a diagram showing its operation timing. FIG. 16 is a circuit diagram of 3 bits of the operation result storage register in FIG. When the pulse density modulation type DA converter according to claim 1 is actually designed using an FPGA or CPLD, in a device in which the bus description is not possible because the values of the two registers are selectively supplied to the input B of the adder / subtractor 4. A selector may be required as in this embodiment. In this embodiment, it is only necessary to supply control signals for SEL, CKS, and CKR from the control unit 6 in order to repeat the addition function 21 and the subtraction function 22 in two cycles. For this reason, it becomes possible to generate a pulse with a period of 25 MHz or more. Therefore, there is a specific effect that if a suitable design is performed, a signal exceeding 100 kHz can be generated.

  Measurement and control system applications include measurement objects with extremely gradual changes in temperature, humidity, etc., so there are sufficiently practical applications to implement a pulse density AD converter using a general-purpose processor. . Further, since many motor control applications have a speed of about 3600 rpm, application using a logic output of a pulse density modulation type DA is possible. Furthermore, many of the controls such as constant current charge / discharge (CC), constant voltage charge / discharge (CV), constant current constant voltage charge / discharge (CC-CV), etc., are used as charge / discharge control of the secondary battery. Since it is 10 Hz or less, it is possible to configure an AD converter or DA converter necessary for control. Furthermore, in measurement, there are applications that measure other physical quantities (voltage, current, resistance, impedance, magnetic field, electric field, sound pressure, distance, etc.) while changing current and voltage little by little. The present invention can be applied to these, and a printed circuit board with a long product life can be developed using an inexpensive general-purpose device. In addition, when a single-phase or multi-phase DDS is configured, the function to adjust the frequency, amplitude, and offset can be realized with a very low computational load, and the scale of the external circuit can be reduced to develop a low-cost product. Is possible. While incorporating general-purpose processors into FPGAs and CPLDs, it is possible to incorporate AD converters and DA converters, magnification changing functions, offset adjustment functions, DDS functions, etc., and further miniaturization and price reduction, and It is easy to develop compatible devices even if the device lifetime is short.

It is explanatory drawing which showed the block diagram of the pulse density modulation type | mold DA converter of Claim 1. Example 1 It is explanatory drawing which showed the problem which a measurement control system has. It is explanatory drawing which showed the simple DA converter by the prior art often used. It is a figure explaining the difference between a pulse width modulation (PWM) system and a pulse density modulation (PDM) system. Example 1 It is a figure which introduces the example of a noise shaping filter. Example 1 It is the figure which illustrated the actual waveform of the pulse density modulation type DA converter. Example 1 It is a figure explaining the linearity and magnification change of a pulse density modulation type DA converter. (Example 2) It is a block diagram of the structural example of normal DDS. It is a figure which illustrates the output waveform of the normal DDS using a normal DA converter. It is a figure which illustrates the waveform of a DDS using a pulse density modulation type DA converter, and a filter output waveform. It is a block diagram of 3 phase DDS using a pulse density modulation type DA converter. It is a figure which illustrates the output waveform of 3 phase DDS using a pulse density modulation type DA converter. It is a figure explaining the Example of a pulse density modulation type AD converter. It is a figure explaining the block diagram of a pulse density modulation type DA converter. It is a figure explaining the operation timing of a pulse density modulation type DA converter. It is a figure explaining the Example of the calculation result storage register | resistor of a pulse density modulation type DA converter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Increment register 2 Operation result storage register 3 DA output range specification register 4 Adder / subtractor 5 DA output register 6 Control part which controls the timing which performs an addition function and a subtraction function alternately 11 DA output target value 12 Output offset value 13 DA output DA output correction target value obtained by adding the target value and the output offset value 14 Operation result value 15 DA output range designation value 16 Addition value 17 Subtraction value 18 Carry signal 19 Pulse density modulation output 21 Increment register value and operation result storage register An addition function for adding values and outputting an addition value. 22 A subtraction function for subtracting a value of a DA output range designation register from a value of an operation result storage register and outputting a subtraction value. Type DA converter 32 Noise shaping to cut or attenuate high frequency components of output pulses Filter 33 output pulses of the pulse density modulation type DA converter 31 according to the analog comparator 34 operation unit 35 integrator 36 calculation unit 41 according to claim 1 outputs

Claims (3)

  An increment register 1 for storing the DA output target value 11 or a DA output correction target value 13 obtained by adding the DA output target value 11 and the output offset value 12; an operation result storage register 2 for storing the operation result value 14; The output range specification register 3 for storing the DA output range specification value 15, the addition function 21 for adding the values supplied from the increment register 1 and the operation result storage register 2 and outputting the addition value 16, and the operation result storage register 2 An adder / subtractor 4 having a subtraction function 22 for outputting a subtraction value 17 by subtracting the DA output range specification value 15 supplied from the output range specification register 3 from a value supplied from After executing the subtraction function 22, a logical value held by holding the carry signal 18 or its inverted logical value is output as a pulse density modulation output 19. A DA output register 5 and a control unit 6 that controls the timing of alternately executing the addition function 21 and the subtraction function 22 are provided. When the control unit 6 executes the addition function 21, the addition value 16 is used as the operation result value 14. When the subtraction function 22 is controlled and the subtraction value 17 is determined to be positive based on the carry signal 18 when the subtraction function 22 is executed, the subtraction value 17 is set to the operation result value 14. As a result, the DA output target value 11 or the DA output correction target value 13 is converted into a pulse density, and the DA output target value 11 or the DA output correction target value 13 is controlled. A function to change the magnification when converting the signal to pulse density only by changing the DA output range specification value without multiplying by the magnification, and the DA output range specification of the DA output range A function of setting an arbitrary natural number which is determined at 15, the pulse density modulation type DA converter, characterized in that to realize the function of the shift by the offset amount designated by the output offset value 12 to the DA output.   The supply of the pulse density modulation type DA converter 31 according to claim 1 and the output pulse 41 output by the pulse density modulation type DA converter 31 according to claim 1 is received and the high frequency component of the output pulse 41 is cut or attenuated. The noise shaping filter 32, the analog comparator 33 that receives the analog input and the output of the noise shaping filter 32, determines the size and outputs a logic output, and increases or decreases the DA output target value 11 based on the logic output of the analog comparator 33. Then, the pulse density modulation type AD converter is provided with an arithmetic unit 34 that supplies the pulse density modulation type DA converter 31 and outputs it as an AD conversion value, and performs AD conversion. The supply of the pulse density modulation type DA converter 31 according to claim 1 and the output pulse 41 output by the pulse density modulation type DA converter 31 according to claim 1 is received and the high frequency component of the output pulse 41 is cut or attenuated. The noise shaping filter 32, the integrator 35 that receives and integrates the analog input and the output of the noise shaping filter 32, and 2 based on whether the integration value is a positive value or a negative value upon receiving the output of the integrator 35. An analog comparator 33 that performs a value logic output, and a calculation unit 36 that increases / decreases the DA output target value 11 based on the logic output of the analog comparator 33 and supplies the DA output target value 11 to the pulse density modulation type DA converter 31 and outputs it as an AD conversion value. A pulse density modulation type AD converter characterized by performing AD conversion.

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