JPH07129428A - Asic microcomputer development supporting device - Google Patents

Abstract

PURPOSE:To reduce time and cost for reproducing a chip by providing the device for confirming a system by completing a prototype before the preparation of the chip when developing an ASIC microcomputer. CONSTITUTION:This device is provided with an ICE 13 for a CPU, user logic mounting part 14 for mounting a device realizing a user logic, real chip interface part 15 for mounting a real chip, target interface part 16 for connecting a target, and wiring part 17 for freely wiring those components, and system debugging is possible by providing a function similar to that of the chip before the chip of the ASIC microcomputer is prepared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a development support device for an ASIC microcomputer having a CPU as a core and peripheral LSIs and a user-specific random logic in one chip.

[0002]

2. Description of the Related Art An ASIC microcomputer is one in which a CPU and random logic unique to each user and, in some cases, a plurality of peripheral LSIs are integrated into one chip. ASIC
An example of an internal block diagram of the microcomputer is shown in FIG. Figure 2
Reference numeral 21 is a CPU core, 22 is a macrocell for CPU peripheral functions, and 23 is a user logic unit that can freely assemble a logic circuit.

As described above, in the ASIC microcomputer, since the CPU, the CPU peripheral LSI, and the logic circuit are separately assembled, they can be integrated into one chip, so that it is possible to reduce the size of the device, improve the reliability, and reduce the cost. In this way, the ASIC microcomputer can realize high functionality, high reliability, and low price, and therefore future growth is expected.

FIG. 3 is a development flow in the prior art when developing a device using such an ASIC microcomputer. The conventional development procedure will be described below with reference to FIG. After system design, move to individual hardware / software design. And in hardware design,
When using an ASIC microcomputer, which block is AS
Consider whether to put it in the IC microcomputer. After that, if the circuit of the user logic section is completed, simulation is performed to perform logic verification / timing verification.

When the verification of the chip of the ASIC microcomputer is completed, the chip is prepared and a sample is prepared. AS
Circuits are assembled on the printed board except for the circuits integrated as the IC microcomputer, and after the ASIC microcomputer is completed, the printed board is assembled. Therefore, verification (debugging) of the entire hardware is performed for the first time. If a defect (bug) due to the specifications of the ASIC microcomputer chip is found at that point, the chip is recreated (chip remanufacturing). When the hardware verification is completed, a connection test with software (coupling debug) is performed, and the system as a whole is verified. Here again, if a defect due to the specifications of the chip is found, it means that the chip is rebuilt.

[0006]

As described above, in the development of the ASIC microcomputer in the prior art, the debug is performed after the ASIC microcomputer chip is created. However, the systematic failure is more likely to be discovered after the process. Get higher If the systematic defect was caused by the chip, the chip had to be recreated each time in the past. Therefore, there is a problem that the development efficiency of the ASIC microcomputer is very poor, and it takes a lot of development time and cost.

It is an object of the present invention to provide an ASIC microcomputer development support device which completes a prototype before the completion of an ASIC microcomputer chip and performs function verification and software debugging in advance.

[0008]

To achieve this object, the present invention provides a debug section for debugging the microcomputer section of an ASIC microcomputer, and a user logic mounting section for mounting a device realizing the user logic. When,
A real chip interface unit for mounting an existing chip, a target interface unit for connecting to a target on which an ASIC microcomputer is mounted, a debug unit, a user logic mounting unit, a real chip interface unit and a target By providing a wiring unit capable of arbitrarily wiring between the interface units and organically connecting the respective constituent elements by the wiring unit, the system debug in which the hardware and the software are combined before the chip of the ASIC microcomputer is created. .

[0009]

According to the present invention, the wiring section connects the debug section, the user logic mounting section, the actual chip interface section, and the target interface section in the ASIC microcomputer development support device according to the ASIC microcomputer to be developed. As a result, a test environment similar to that for creating an ASIC microcomputer chip is realized, and a test up to system debug in which hardware and software are combined before the ASIC microcomputer chip is created.

[0010]

1 is a functional block diagram of an embodiment of an ASIC microcomputer development support device according to the present invention. Figure 1
In the figure, 10 is an ASIC microcomputer development support device according to the embodiment of the present invention, 11 is a host computer for controlling the ASIC microcomputer development support device 12, and 12 is an A computer.
A device in which the SIC microcomputer is mounted (hereinafter referred to as a target), 13 is an ICE for a CPU that debugs the microcomputer portion of the ASIC microcomputer, 14 is a block for mounting the user logic, and 15 is an existing existing chip. An actual chip interface section for mounting, 16 is a target interface section for in-circuiting a target circuit when there is a target circuit, and 17 is a programmable wiring section for wiring these blocks in a programmable manner.

In FIG. 1, the CPU ICE 13 is a normal CP.
ICE unit that debugs U, CP that makes ASIC
The U 131, the control unit 132, the trigger unit 133, and the trace unit 134. The CPU 131, the control unit 132, the trigger unit 133, and the trace unit 134 are respectively connected to the bus, and the control unit 132 allows the ICE to operate.
Is controlled.

That is, the control unit 132 has the trigger unit 13
Controls breakpoints, etc. by 3, and trace unit 1
The execution result of the CPU 131 is recorded by 34. In this way, the CPU ICE 13 controls the execution / stop of the CPU and enables the software debugging. In addition, the execution process of the CPU can be recorded by the trace function.

The user logic / mounting unit 14 is an ASIC.
A field programmable gate array (FPGA), which is a prototype gate array written externally, is a part that implements user logic integrated as part of a microcomputer.
y) can be implemented and the user's logic circuit can be realized. Further, for example, if this portion is configured by an SRAM-based FPGA, it becomes possible to write or change the user circuit in this device.

The actual chip mounting portion 15 is a portion which interfaces with the actual chip. With this real chip mounting unit 15, a part of the ASIC microcomputer, for example, DMAC, S
When incorporating the functions of an existing LSI such as IO, if a chip is actually present, it can be interfaced by mounting it here.

The target interface unit 16 is an AS
This is an interface with the target on which the IC microcomputer is mounted. If there is already a board on which the ASIC microcomputer is mounted, it is possible to check the entire system by connecting to this board. In other words, I for general CPU
As the CE goes in-circuit to the socket of the CPU,
In-circuit can be installed in the socket where the ASIC microcomputer should be mounted.

The programmable wiring 17 is a programmable wiring section in which internal wiring is free, so that the above-mentioned blocks can be arbitrarily connected as needed.

A specific method of using the apparatus having the above-mentioned structure will be described below. The user logic circuit is externally converted to an FPGA and mounted on the user logic mounting unit 14. If the peripheral LSI already exists as an actual chip, it is mounted in the actual chip mounting unit 15. If there is a target, it is connected to the target 12 through the target interface section 16.

The connection information between these components is given to the host 11 as a netlist, for example,
To the ASIC microcomputer development support device 10.
As a result, the internal wiring of the programmable wiring unit 17 is changed, and the respective constituent elements are organically connected to each other so that the desired ASI is obtained.
The function of the C microcomputer can be obtained. After that, ICE for CPU
The software is debugged using 13, and system debugging becomes possible.

Further, for example, the user logic mounting unit 1
By using the SRAM-based FPGA for 4, it is possible to freely rewrite the circuit in this device,
The circuit change can be reflected immediately.

Next, FIG. 4 shows a flow chart of ASIC microcomputer development when the ASIC microcomputer development support device 10 in the embodiment of the present invention shown in FIG. 1 is used.
As shown in FIG. 4, the ASIC microcomputer development support device 10
, The combined debug 300 shown in FIG.
This is possible with the combined debug 400 performed before the C microcomputer chip is created.

As described above, according to the embodiment of the present invention, since the combined debug 400 of the entire system can be performed before the chip is made, a system malfunction caused by the chip specifications can be found before the chip is made. Therefore, in the prior art, the remanufacturing of the chip generated by the debugging performed after assembling the printed board and the ASIC microcomputer chip, and the remanufacturing of the chip generated by the combined debugging of the hardware and the software after the assembly. Can be prevented.

After the chip is formed (402), the debug 404 and the combined debug 406 are performed in this embodiment as well, but these debugs are sufficient only for confirmation, and the probability that a system malfunction is hidden is low. Therefore, there is practically no need to remanufacture the ASIC microcomputer chip.

[0023]

By using the ASIC microcomputer development support device according to the present invention, it is possible to realize the same function as the chip before the chip of the ASIC microcomputer is created. The software can be confirmed, and the time and cost for remanufacturing the chip can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an ASIC microcomputer development support device according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of an ASIC microcomputer.

FIG. 3 is a development flowchart of a conventional ASIC microcomputer.

FIG. 4 is a development flow chart of an ASIC microcomputer when the ASIC microcomputer development support device of FIG. 1 is used.

[Explanation of symbols]

 10 ASIC microcomputer development support device 11 host 12 target 13 CPU ICE 14 user logic mounting part 15 actual chip mounting part 16 target interface part 17 programmable wiring part 21 CPU core 22 peripheral function macrocell 23 user logic part 31 CPU 132 ICE control 133 Trigger part 134 Trace part

Claims (1)

[Claims] 1. A debug unit for debugging a microcomputer unit of an ASIC microcomputer, a user logic mounting unit for mounting a device realizing a user logic, and an actual chip interface unit for mounting an existing chip. A target interface unit for connecting to a target on which the ASIC microcomputer is mounted, the debug unit, a user logic mounting unit, an actual chip,
The interface section and the target / interface section are provided with a wiring section capable of arbitrarily wiring, and the wiring section organically connects the respective constituent elements, so that hardware and software can be provided before the chip of the ASIC microcomputer is created. ASIC microcomputer development support device for combined system debugging.