JPH07122062A - Semiconductor memory device - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] To realize a synchronous DRAM or the like that can simultaneously perform normal read or write operation and refresh operation. A shared MOSFET N7 and N8 or ND and NE capable of dividing the memory array MARY into two at specified positions in the bit line extension direction and complementary bit lines B0 * to Bn.
A refresh for performing an autonomous refresh operation by providing two sense amplifiers SAL and SAR to which one end and the other end of * are respectively coupled and sequentially designating word lines WF0 to WFm to be refreshed in a predetermined cycle. The address of the word line designated by the control circuit and the refresh control circuit is compared with the address of the word line designated from outside to determine the division position of the memory array MARY and selectively operate the sense amplifiers SAL and SAR. And an address comparison circuit for setting the status.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a synchronous DRAM (Dynamic).
Random Access Memory: dynamic random access memory).

[0002]

2. Description of the Related Art A memory array including orthogonally arranged word lines and complementary bit lines and dynamic memory cells arranged in a lattice at intersections of the word lines and complementary bit lines is a basic constituent element. There is a dynamic RAM. In addition, such dynamic RA
A so-called synchronous DR which is constructed based on M and whose operation is synchronized in accordance with an externally supplied clock signal.
I have AM.

For the synchronous DRAM, for example, "HM5216800, HM5416800 series" issued by Hitachi, Ltd. on January 18, 1993.
Data Book ”and the like.

[0004]

SUMMARY OF THE INVENTION Synchronous DR
In AM or the like, each of the complementary bit lines forming the memory array is coupled to the corresponding unit amplifier circuit of the sense amplifier at one of them. Each unit amplifier circuit of the sense amplifier is used as an amplifier circuit for amplifying a minute read signal of a predetermined number of memory cells coupled to the selected word line into a binary read signal, and corresponding these read signals. It is also used as a so-called active restore circuit for rewriting to the memory cell. That is, in the case of the conventional synchronous DRAM or the like, only one sense amplifier is provided for each memory array, and only one of normal read or write operation and refresh operation using this sense amplifier is selective. To be executed. In other words, Synchronous D
The refresh operation of RAM, etc. is a synchronous DRAM.
It is a reason that access devices such as
The external device, that is, the access device, requires a refresh control circuit for managing the refresh cycle and the address. As a result, the amount of hardware of the system including the synchronous DRAM and the like increases and its control becomes complicated,
The cost reduction of the system is hindered, and the forced refresh operation is executed, so that the synchronous DRAM
The access efficiency of the system, etc. is reduced, and the processing capacity of the system is reduced.

An object of the present invention is to realize a semiconductor memory device such as a synchronous DRAM capable of simultaneously performing a normal read or write operation and a refresh operation. Another object of the present invention is a synchronous DRAM.
It is intended to reduce the system hardware cost including the above, simplify the control thereof, and promote the system cost reduction. A further object of the present invention is a synchronous DRAM.
It is to improve the access efficiency of the system and improve the processing capacity of the system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a switch means for dividing the memory array into two at a specified position in the bit line extension direction and a first end and a second end of the bit line are respectively coupled to a synchronous DRAM or the like which requires a refresh operation.
And a second sense amplifier, and a refresh control circuit for sequentially designating word lines at a predetermined cycle to perform an autonomous refresh operation, and a word line address designated by the refresh control circuit and designation from the outside. And an address comparison circuit for comparing the address of the word line to determine the division position of the memory array and selectively operating the first and second sense amplifiers.

[0008]

According to the above means, since two word lines can be selected in the same memory array and a normal read or write operation and a refresh operation can be executed simultaneously, an access side device such as a synchronous DRAM can be implemented. ,
The refresh control and the access restriction at the time of refresh can be released. As a result, the amount of hardware of the system including the synchronous DRAM and the like can be reduced and its control can be simplified to promote the cost reduction of the system, and the access efficiency of the synchronous DRAM and the like can be improved to enhance the processing capacity of the system. be able to.

[0009]

1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied. 2 and 3, the memory array MARY and the sense amplifier S included in the synchronous DRAM of FIG.
Circuit diagrams for one embodiment of AL and SAR are shown respectively. Based on these figures, the outline of the configuration and operation of the synchronous DRAM of this embodiment will be described first.
The circuit elements shown in FIGS. 2 and 3 and the circuit elements constituting the blocks shown in FIG.
tal Oxide Semiconductor F
field Effect Transistor: A metal oxide semiconductor field effect transistor. In this specification,
It is formed on one semiconductor substrate surface such as single crystal silicon by a manufacturing technique of an integrated circuit, which is a generic name of an insulated gate field effect transistor by referring to a MOSFET. In the following circuit diagram and connection diagram, the MOSFET with an arrow on its channel (back gate) is P
It is a channel type and is shown in distinction from an N-channel MOSFET without an arrow.

In FIG. 1, the synchronous DRAM of this embodiment has a memory array MARY, which is arranged so as to occupy most of the surface of a semiconductor substrate, as its basic constituent element. As shown in FIG. 2, this memory array MARY has m + 1 word lines W0 to W0 arranged in parallel in the vertical direction of the drawing.
Wm and n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction (here, for example, the non-inverted bit line B0T and the inverted bit line B0B are combined to form a complementary bit line B0 *. Represented by *, and a non-inverted signal, etc. that is selectively set to high level when it is validated is denoted by T at the end of its name and selected when it is validated. Inverted signals and the like that are set to a low level are represented by adding B at the end of their names. Furthermore, the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn * are
As will be described later, it is divided by a plurality of shared MOSFETs, but is referred to as a unit in the memory array). At the intersection of these word lines and complementary bit lines, there are (m + 1) × (n +) consisting of an information storage capacitor Cs and an address selection MOSFET Qa.
1) Dynamic memory cells are arranged in a grid.

The word lines W0 to Wm forming the memory array MARY have X address decoders X below them.
It is coupled to D and above it is coupled to refresh X address decoder XDF as refresh word lines WF0 to WFm. In addition, complementary bit lines B0 * to
Bn * is a sense amplifier S at one end, that is, on the left side.
The sense amplifier SAR is coupled to the corresponding unit circuit of the AL (first sense amplifier), and the other end, that is, the right side.
It is coupled to the corresponding unit circuit of the (second sense amplifier). Needless to say, the word lines W0 to Wm and the refresh word lines WF0 to WFm are the same, but in the following description, the word line selected in the normal read or write mode and the selected state in the refresh mode are selected. Another name is intentionally used to identify the word line that is being used.

In this embodiment, the memory array MAR
Y is an N-channel type total of m × (n + 1) pairs of shared MOSFETs N7 and N8 provided so as to divide complementary bit lines B0 * to Bn * in memory cell units.
To ND and NE (switch means). The gates of these shared MOSFETs are commonly coupled row by row by n + 1 pairs, and the corresponding shared control signal lines S0 to S are connected.
Refresh X address decoder XD via m-1
Bound to F. Here, the shared control signal lines S0 to S
m-1 is a shared MOSFET that is higher than the power supply voltage of the circuit when the synchronous DRAM is deselected.
When the synchronous DRAM is set to a high level higher than the threshold voltage of N7 to NE and the synchronous DRAM is in the selected state, it is alternatively set to the low level like the ground potential of the circuit under a predetermined condition described later.

The X address decoder XD has an i + 1 bit internal address signal X0 from the X address buffer XB.
To Xi are supplied, and an internal control signal XDG (not shown) is supplied from the timing generation circuit TG. Further, the X address buffer XB is time-divisionally supplied with the X address signals AX0 to AXi via the address input terminals A0 to Ai, and the timing generation circuit TG supplies the internal control signal AXL (not shown). On the other hand, the refresh X address decoder XDF includes a refresh control circuit RC.
To the internal address signals R0 to Ri, and the timing generation circuit TG supplies the internal control signals XFL and XFR. Further, the refresh control circuit RC is supplied with the internal control signal CC from the timing generation circuit TG,
The output signal, that is, the internal control signal RF is supplied to the timing generation circuit TG. Further, to the sense amplifiers SAL and SAR, the n + 1-bit bit line selection signals YS0 to YSn are commonly supplied from the Y address decoder YD, and the internal control signals PAL and PAR are respectively supplied from the timing generation circuit TG. Y address decoder Y
An internal address signal Y0 to Yi of i + 1 bits is supplied to D from the Y address buffer YB, and an internal control signal YDG (not shown) is supplied from the timing generation circuit TG. Further, the Y address buffer YB has Y address signals AY0 to AY via address input terminals A0 to Ai.
i is supplied in a time division manner, and an internal control signal AYL (not shown) is supplied from the timing generation circuit TG.

Here, the X address buffer XB has address input terminals A0 to Ai when the synchronous DRAM is selected in a normal read or write mode.
The X address signals AX0 to AXi supplied via the above are fetched and held according to the internal control signal AXL, and the internal address signals X0 to Xi are formed based on these X address signals and supplied to the X address decoder XD. . At this time, the X address decoder XD is selectively activated by receiving the high level of the internal control signal XDG, decodes the internal address signals X0 to Xi, and outputs the corresponding word lines W0 to Wm of the memory array MARY. Alternately set to high level. The internal address signals X0 to X0
Xi is also supplied to one input terminal of the address comparison circuit AC.

On the other hand, the refresh control circuit RC sequentially and alternately selects a refresh timer circuit for activating a refresh mode at a predetermined cycle and a word line to be refreshed in this refresh mode, that is, refresh word lines WF0 to WFm. And a refresh address counter for designating. Among these, the refresh timer circuit sets the internal control signal RF to the high level at a preset predetermined cycle, and requests the timing generation circuit TG to start the refresh mode. In addition, the refresh address counter receives the rising edge of the internal control signal CC supplied from the timing generation circuit TG at the start of the refresh mode and performs a step operation to form the internal address signals R0 to Ri to generate a refresh X signal. It is supplied to the address decoder XDF. The high level of the internal control signal RF is discriminated by the timing generation circuit TG at the rising edge of the clock signal CLK as will be described later, and in response thereto, the refresh mode is started. The internal control signal CC is temporarily set to the high level immediately after the refresh mode is started. Further, the internal address signals R0 to Ri output from the refresh control circuit RC are the address comparison circuits AC.
Is also supplied to the other input terminal of.

The address comparison circuit AC has internal address signals X0 to Xi output from the X address buffer XB in the normal read or write mode.
And the internal address signals R0 to Ri output from the refresh control circuit RC in the refresh mode are compared and collated, and the output signal, that is, the internal control signals XL and A.
M and XR are alternatively set to a high level under a predetermined condition. That is, in the address comparison circuit AC, the binary values of the internal address signals X0 to Xi are the internal address signals R0 to Ri.
Is less than the binary value of the word lines W0 to W specified by the internal address signals X0 to Xi.
When m is arranged on the left side of the refresh word lines WF0 to WFm designated by the internal address signals R0 to Ri, that is, on the younger side, the internal control signal XL is alternatively set to the high level.

On the other hand, in the address comparison circuit AC, the binary values of the internal address signals X0 to Xi are the internal address signals R0 to R0.
When it is larger than the binary value of Ri, in other words, the word line W0 designated by the internal address signals X0 to Xi
When Wm to Wm are arranged on the right side of refresh word lines WF0 to WFm designated by internal address signals R0 to Ri, that is, on the old side, internal control signal XR is alternatively set to the high level. Further, the internal address signals X0 to X0
When the binary value of Xi matches the binary value of the internal address signals R0 to Ri, in other words, internal address signal X0
When word lines W0 to Wm designated by Xi and refresh word lines WF0 to WFm designated by internal address signals R0 to Ri are the same,
The internal control signal AM is alternatively set to the high level. In addition,
When the normal read or write mode and the refresh mode are independently executed without conflict, the internal control signals XL and AM and XR are all kept at the low level.

The output signal of the address comparison circuit AC, that is, the internal control signals XL, AM and XR are supplied to the timing generation circuit TG. When the internal control signal XL is alternatively set to the high level, the timing generation circuit TG sets the internal control signal XFL to the high level at a predetermined timing and then simultaneously sets the internal control signals PAL and PAR at a predetermined timing. The internal control signal I is set to high level and slightly delayed.
Set OL to high level. When the internal control signal XR is alternatively set to the high level, the internal control signal XFR is set to the high level at a predetermined timing, and then the internal control signals PAL and PAR are set to the high level at the predetermined timing at the same time. After a delay, the internal control signal IOR is set to the high level. On the other hand, when the internal control signal AM is set to the high level, the timing generation circuit TG sets the internal control signal IOL to the high level with a slight delay after setting only the internal control signal PAL to the high level at a predetermined timing. Both internal control signals XFL and XFR are kept at low level. Further, when the refresh mode is independently executed without competing with the normal read or write mode and the internal control signals XL, AM and XR are both set to the low level, the internal control signals XFL and XF are not particularly limited.
R is simultaneously set to the high level at a predetermined timing and only the internal control signal PAL is set to the high level, but the internal control signals PAR, IOL and IOR are all kept at the low level.

Refresh X address decoder XDF
Receives the high level of the internal control signal XFL or XFR, and is selectively brought into an operating state.
i is decoded to selectively set the corresponding refresh word lines WF0 to WFm of the memory array MARY to the high level, and the shared control signal lines S0 to Sm-
1 is set to a low level such as the ground potential of the circuit alternatively under a predetermined condition. That is, the refresh X-address decoder XDF has shared control signal lines S0 to Sm adjacent to the left side of the refresh word lines WF0 to WFm which should be alternatively set to high level when the internal control signal XFL is set to high level. -1 is alternatively set to the low level, and when the internal control signal XFR is set to the high level, the shared control signal lines S0 to Sm-1 adjacent to the right side thereof are alternatively set to the low level. When the refresh mode is executed independently without conflicting with the normal read or write mode and the internal control signals XFL and XFR are simultaneously set to the high level, the refresh X address decoder X
DF selectively sets the refresh word lines WF0 to WFm corresponding to the internal address signals R0 to Ri to the high level, but leaves the shared control signal lines S0 to Sm-1 all at the high level.

As described above, the shared control signal lines S0 to S0
Sm-1 is supplied to the gates of the corresponding shared MOSFETs N7 to NE of the memory array MARY. When the internal control signal XFL is independently set to the high level, in the memory array MARY, the word lines W0 to Wm corresponding to the internal address signals X0 to Xi are alternatively set to the high level. Further, the refresh word lines WF0 to WFm corresponding to the internal address signals R0 to Ri are alternatively set to the high level, and the shared control signal lines S0 to Sm-1 adjacent to the left side of the refresh word line are alternatively selected. Is set to low level. As a result, the corresponding n + 1 pairs of shared MOSFETs are turned off, and the memory array MARY
To the divided left side internal address signals X0 to Xi.
Is divided into two in a form including a word line designated by and a refresh word line designated by internal address signals R0 to Ri on the right side. It goes without saying that the divided complementary bit lines B0 * to Bn * on the left side of the memory array MARY are coupled to the corresponding unit circuits of the sense amplifier SAL, and the complementary bit lines B0 * to Bn on the right side are connected.
* Is coupled to the corresponding unit circuit of the sense amplifier SAR.

Similarly, when the internal control signal XFR is independently set to the high level, the word lines W0 to Wm corresponding to the internal address signals X0 to Xi in the memory array MARY.
Is alternatively set to the high level. In addition, the refresh word line WF0 corresponding to the internal address signals R0 to Ri
To WFm are alternatively set to the high level, and the shared control signal line S0 adjacent to the right side of the refresh word line is
~ Sm-1 is alternatively set to the low level. As a result,
The corresponding n + 1 pairs of shared MOSFETs are turned off, and the memory array MARY includes the word line designated by the internal address signals X0 to Xi on the divided right side thereof and the word line designated by the internal address signals R0 to Ri on the left side thereof. It is divided into two parts including the word line for refresh. The divided left complementary bit lines B0 * to Bn * of the memory array MARY are coupled to the corresponding unit circuits of the sense amplifier SAL, and the right complementary bit lines B0 * are connected.
* To Bn * are coupled to the corresponding unit circuits of the sense amplifier SAR.

On the other hand, when the internal control signals XFL and XFR are simultaneously set to the high level, in the memory array MARY, only the refresh word lines WF0 to WFm corresponding to the internal address signals R0 to Ri are alternatively set to the high level. The shared control signal lines S0 to Sm-1 are all kept at the high level. Therefore, the memory array MA
RY is not divided into two, and complementary bit lines B0 * to Bn * are simultaneously coupled to the corresponding unit circuits of sense amplifiers SAL and SAR. At this time, the internal control signal PAL is set to the high level, and the internal control signals PAR, IOL, and IOR are all kept at the low level, so that the n + 1 memory cells coupled to the refresh word line selected are selected. The amplification operation of the small read signal output is
It is performed only by the corresponding unit circuit of the left sense amplifier SAL.

Next, the sense amplifier SAL includes n + 1 unit circuits provided corresponding to the complementary bit lines B0 * to Bn * of the memory array MARY, and each of these unit circuits is illustrated in FIG. As described above, the unit amplifier circuit is formed by cross-coupling a pair of CMOS inverters including the P-channel MOSFET P1 and the N-channel MOSFET N1 and the P-channel MOSFET P2 and the N-channel MOSFET N2, and the N-channel type switch MOSFETs NF and NG. Of these, the sources of the MOSFETs P1 and P2 forming each unit amplifier circuit are commonly coupled to the common source line SPL, and then the gates thereof receive the inverted signal of the internal control signal PAL by the inverter V1, that is, the inverted internal control signal PALB. It is coupled to the circuit power supply voltage through a channel type drive MOSFET P5. In addition, MOSFET N1
The sources of N and N2 are commonly coupled to a common source line SNL, and then have their gates receiving an internal control signal PAL.
It is coupled to the circuit ground potential via a channel type drive MOSFET N5. Switch MOSFE of each unit circuit
The gates of TNF and NG are commonly connected to each other, and the corresponding bit line selection signal YS is output from the Y address decoder YD.
0 to YSn are supplied.

Similarly, the sense amplifier SAR includes n + 1 unit circuits provided corresponding to the complementary bit lines B0 * to Bn * of the memory array MARY, and each of these unit circuits is illustrated in FIG. So that P-channel MOSFET P3 and N-channel MOSFET N3
And a unit amplifier circuit in which a pair of CMOS inverters composed of a P-channel MOSFET P4 and an N-channel MOSFET N4 are cross-coupled, and a pair of N-channel type switch MOSFETs NH and NI.
Of these, MOSFET P3 that constitutes each unit amplifier circuit
The sources of P4 and P4 are commonly coupled to the common source line SPR, and then have their gates inverted by the inverter V2, that is, the inverted internal control signal PARB.
Is coupled to the circuit power supply voltage through a P-channel drive MOSFET P6 which receives the signal. In addition, MOSFETN
The sources of 3 and N4 are commonly coupled to the common source line SNR and then coupled to the ground potential of the circuit through an N-channel drive MOSFET N6 which receives the internal control signal PAR at its gate. Switch MOSF of each unit circuit
The gates of ETNH and NI are commonly connected, and Y
The corresponding bit line selection signal Y from the address decoder YD
S0 to YSn are supplied.

As a result, the sense amplifiers SAL and SA are
The unit amplifier circuits forming each unit circuit of R are selectively and simultaneously activated by setting the corresponding internal control signal PAL or PAR to the high level, and the selected word line of the memory array MARY is activated. W0 to Wm or n + 1 memory cells coupled to refresh word lines WF0 to WFm and corresponding complementary bit lines B0 *
A minute read signal output via Bn * is amplified to be a high level or low level binary read signal. Further, the switch MOSFETs NF and NG and NH and NI which form each unit circuit of the sense amplifiers SAL and SAR correspond to the corresponding bit line selection signals YS0 to YS0.
When Sn is set to the high level, it is selectively turned on, and the corresponding pair of complementary bit lines B0 * to Bn * and complementary common data line CDL * of the memory array MARY are selectively turned on.
Alternatively, the CDR * is selectively connected.

The Y address buffer YB is supplied with Y address signal AY via address input terminals A0 to Ai.
0 to AYi are fetched and held according to the internal control signal AYL, and internal address signals Y0 to Yi are formed based on these Y address signals and supplied to the Y address decoder YD. The Y address decoder YD is selectively operated in response to the high level of the internal control signal YDG, decodes the internal address signals Y0 to Yi, and selectively turns the corresponding bit line selection signals YS0 to YSn high. Level. These bit line selection signals are supplied to the corresponding switch MOSFETs of the sense amplifiers SAL and SAR as described above.

The complementary common data lines CDL * and CDR * to which the designated complementary bit lines B0 * to Bn * of the memory array MARY are selectively connected are coupled to the data input / output circuit IO. The data input / output circuit IO includes the internal control signals IOL and I from the timing generation circuit TG.
OR is supplied.

The data input / output circuit IO includes two write amplifiers and two main amplifiers provided corresponding to the complementary common data lines CDL * and CDR *, and one data input buffer and one data output buffer. . Of these, the output terminal of each write amplifier and the input terminal of the main amplifier are associated with the corresponding complementary common data line CDL *.
Alternatively, they are commonly linked to CDR *. The input terminal of each write amplifier is commonly coupled to the output terminal of the data input buffer, and the output terminal of each main amplifier is commonly coupled to the input terminal of the data output buffer. Further, the input terminal of the data input buffer is the data input terminal Din
And the output terminal of the data output buffer is coupled to the data output terminal Dout.

The data input buffer of the data input / output circuit IO takes in the write data supplied through the data input terminal Din when the synchronous DRAM is selected in the normal write mode, and stores it in two write amplifiers. introduce. At this time, each of the write amplifiers is selectively activated by setting the corresponding internal control signal IOL or IOR to the high level, and the write data transmitted from the data input buffer is used as a predetermined complementary write signal. Then, the corresponding complementary common data line CDL * or CDR
Writing from * to one selected memory cell of the memory array MARY via the sense amplifier SAL or SAR.

On the other hand, each main amplifier of the data input / output circuit IO has a corresponding internal control signal IOL when the synchronous DRAM is selected in the normal read mode.
Alternatively, when the IOR is set to the high level, it is selectively brought into an operating state, and the corresponding complementary common data line CDL * or C from one selected memory cell of the memory array MARY.
The binary read signal output via DR * is further amplified and transmitted to the data output buffer. This read data is sent from the data output buffer to the data output terminal ou.
It is output to the outside of the synchronous DRAM via t.

The timing generation circuit TG has a chip selection signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB which are externally supplied as start control signals.
And the internal control signals XL, AM and XR supplied from the address comparison circuit AC, the various internal control signals are selectively formed and supplied to the respective parts of the synchronous DRAM. The logic levels of the activation control signal and the internal control signal are determined at the rising edge of the clock signal CLK supplied from the outside, whereby the operation of the synchronous DRAM is synchronized with the clock signal CLK.

FIG. 4 shows a signal waveform diagram of an embodiment of the read mode of the synchronous DRAM of FIG. Further, FIG. 5 shows a connection diagram of the memory array and the sense amplifier in the cycle A of the read mode of FIG. 4, and FIG. 6 shows a connection diagram of the memory array and the sense amplifier in the cycle B. Based on these figures, the outline and characteristics of the read mode and refresh mode of the synchronous DRAM of this embodiment will be described. Note that, in FIGS. 4 and 5, the unit amplifier circuits forming the unit circuits of the sense amplifiers SAL and SAR are shown as USA0 to USAAn. Also,
The cycle A of FIGS. 3 and 4 illustrates the case where the normal read operation for the word line W1 and the refresh operation for the refresh word line WF0 are simultaneously performed, and the cycle B of FIGS. 3 and 5 illustrates the word line W0. An example is shown in which a normal read operation for the refresh word line WF1 and a refresh operation for the refresh word line WF1 are simultaneously performed. Hereinafter, a specific description will be made along these examples.

In FIG. 4, the synchronous DRAM of this embodiment is selectively brought into the selected state when the chip selection signal CSB is brought to the low level at the rising edge of the clock signal CLK. At this time, if the row address strobe signal RASB is at low level, the internal control signal AXL is set to high level, and the address input terminals A0 to A
X address signal AX0 which is time-divisionally supplied via i
.About.AXi are taken into the X address buffer XB and become internal address signals X0 to Xi. When the column address strobe signal CASB is at low level, the internal control signal AYL is at high level, and the address input terminal A
Y address signals AY0 to AYi which are time-divisionally supplied via 0 to Ai are taken into the Y address buffer YB and become internal address signals Y0 to Yi. In the case of this embodiment, the X address signals AX0 to AXi are a combination that specifies the word line W1 in cycle A and a combination that specifies the word line W0 in cycle B. Further, the Y address signals AY0 to AYi are a combination that specifies the bit line selection signal YS1 or the complementary bit line B1 * in cycle A, and the bit line selection signal YS0 or the complementary bit line B0 * in cycle B.
Is a combination that specifies.

On the other hand, inside the synchronous DRAM,
Immediately before the start of the cycle A, the output signal of the refresh control circuit RC (not shown), that is, the internal control signal RF is set to the high level, and a request to start the refresh mode is issued to the timing generation circuit TG. Internal control signal R
The high level of F is determined by the timing generation circuit TG at the rising edge of the clock signal CLK, and in response to this, the internal control signal CC is temporarily set to high level. In the refresh control circuit RC, the internal control signal CC
The refresh address counter is incremented in response to the rising edge of, and the count value, that is, the internal address signal R
0 to Ri are the combination that specifies the refresh word line WF0 in cycle A, and the combination that specifies the refresh word line WF1 in cycle B.

In cycle A, word line W1 designated by internal address signals X0 to Xi is arranged on the right side of refresh word line WF0 designated by internal address signals R0 to Ri, that is, on the old side. Therefore, the address comparison circuit AC sets the internal control signal XR to the high level and the internal control signal XL to the low level. As a result, the internal control signal XFL is individually set to the high level at a predetermined timing, the internal control signal XDG (not shown) is set to the high level, and the internal control signals PAL and PAR are simultaneously set to the high level with a slight delay. As a result, as shown in FIG. 5, the word line W1 is selectively set to the high level by the X address decoder XD, and the refresh word line WF0 is alternatively set to the high level by the refresh X address decoder XDF. Then, the shared control signal line S0 adjacent to the right side thereof is alternatively set to the low level.

In the memory array MARY, in response to the low level of the shared control signal line S0, the corresponding n + 1 pairs of shared MOSFETs N7 and N8 are simultaneously turned off, whereby the memory array MARY is refreshed to the word line WF0 and the word line W1. Is divided into two. Further, when the high level of the word line W1 is received, the corresponding n + 1 memory cells are brought into the selected state, and the minute read signal according to the data held in these memory cells is transmitted to the corresponding complementary bit lines B0 * to Bn *. It is transmitted to the corresponding unit circuit of the sense amplifier SAR through the divided right side. Further, when the high level of the refresh word line WF0 is received, the corresponding n + 1 memory cells are brought into the selected state, and the minute read signal according to the data held in these memory cells is transmitted to the corresponding complementary bit lines B0 * to Bn. It is transmitted to the corresponding unit circuit of the sense amplifier SAL via the divided left side of *.

The minute read signal transmitted to each unit circuit of the sense amplifier SAR is amplified by the high level of the internal control signal PAR, and becomes a binary read signal. Then, the bit line selection signal YS1 is selectively set to the high level while being rewritten in the corresponding memory cell as it is, so that the sense amplifier SAR selectively outputs the data via the complementary common data line CDR *. It is transmitted to the corresponding main amplifier of the input / output circuit IO. This read data receives the high level of the internal control signal IOR, is further amplified by the corresponding main amplifier, and is output from the data output buffer to the outside of the synchronous DRAM via the data output terminal Dout. On the other hand, the minute read signal transmitted to each unit circuit of the sense amplifier SAL is amplified when the internal control signal PAL is set to the high level, and becomes a binary read signal. Then, the data is rewritten into the corresponding memory cell as it is, whereby the refresh operation for the refresh word line WF0 is realized.

Next, in cycle B, word line W0 designated by internal address signals X0 to Xi is arranged on the left side of refresh word line WF1 designated by internal address signals R0 to Ri, that is, on the younger side. Therefore, the address comparison circuit AC sets the internal control signal XR to the low level, and instead sets the internal control signal XL to the high level. As a result, the internal control signal XFR is individually set to the high level at a predetermined timing, the internal control signal XDG is set to the high level, and the internal control signals PAL and PAR are simultaneously set to the high level with a slight delay. As a result, as shown in FIG. 6, the X address decoder X
The word line W0 is selectively set to the high level by D, and the refresh word line WF1 is selectively set to the high level by the refresh X address decoder XDF, and the shared control signal line S adjacent to the left side of the refresh word line WF1 is set to the high level.
0 is alternatively set to low level.

In the memory array MARY, in response to the low level of the shared control signal line S0, the corresponding n + 1 pairs of shared MOSFETs N7 and N8 are simultaneously turned off, whereby the memory array MARY is set to the word line W0.
And the refresh word line WF1 are divided into two. Further, the corresponding n + 1 memory cells are brought into a selected state in response to the high level of the word line W0, and a minute read signal according to the data held in these memory cells is transmitted to the corresponding complementary bit lines B0 * to Bn *. It is transmitted to the corresponding unit circuit of the sense amplifier SAL via the divided left side. Further, when the high level of the refresh word line WF1 is received, the corresponding n + 1 memory cells are brought into a selected state, and a minute read signal according to the data held in these memory cells is transmitted to the corresponding complementary bit lines B0 * to Bn. It is transmitted to the corresponding unit circuit of the sense amplifier SAR through the divided right side of *.

The minute read signal transmitted to each unit circuit of the sense amplifier SAL is amplified by the high level of the internal control signal PAL and becomes a binary read signal. Then, the bit line selection signal YS0 is selectively set to the high level while being rewritten in the corresponding memory cell as it is, so that the data is selectively output from the sense amplifier SAL via the complementary common data line CDL *. It is transmitted to the corresponding main amplifier of the input / output circuit IO. The read data receives the high level of the internal control signal IOL, is further amplified by the corresponding main amplifier, and is output from the data output buffer to the outside of the synchronous DRAM through the data output terminal Dout. On the other hand, the minute read signal transmitted to each unit circuit of the sense amplifier SAR is amplified by the high level of the internal control signal PAR and becomes a binary read signal. Then, the data is rewritten into the corresponding memory cell as it is, whereby the refresh operation for the refresh word line WF1 is realized.

As described above, in the synchronous DRAM of this embodiment, the total m is provided so that the memory array MARY can be arbitrarily divided into two at specified positions in the bit line extension direction.
It includes x (n + 1) pairs of shared MOSFETs N7 and N8 to ND and NE, and sense amplifiers SAL and SAR provided at one end, that is, the left side and the other end, that is, the right side of the complementary bit lines B0 * to Bn *. Further, a refresh control circuit RC for sequentially designating the refresh word lines WF0 to WFm in a predetermined cycle to perform an autonomous refresh operation, an internal address signal R0 to Ri output from the refresh control circuit, and an X address buffer. Internal address signals X0-X0 input via XB
An address comparison circuit AC for comparing the Xi and Xi to determine the division position of the memory array MARY and selectively activate the sense amplifiers SAL and SAR. However, in the synchronous DRAM of this embodiment, two word lines are simultaneously selected in the memory array MARY, and a total of 2 × (n +) connected to these word lines is selected.
1) Since the minute read signals output from the memory cells can be simultaneously amplified by the sense amplifiers SAL and SAR, the normal read or write operation and the refresh operation can be simultaneously executed, and the synchronous DRAM can be executed. The access side device can be released from refresh control and access restrictions at the time of refresh. As a result, it is possible to reduce the amount of hardware of the system including the synchronous DRAM and simplify the control thereof, to promote the cost reduction of the system, to improve the access efficiency of the synchronous DRAM, and to enhance the processing capacity of the system. It is possible.

As is apparent from the above description, the reason why the present invention is realized as a synchronous DRAM is that the normal read or write mode and the refresh mode are both executed in synchronization with the clock signal CLK. is there. This means that the refresh operation is not started during the normal read or write operation, or the normal read or write operation is not started during the refresh operation. In addition, the normal read or write mode start request and the refresh mode start request, which are asynchronously generated, can be synchronized with each other and the conflict can be accurately controlled.

By applying the present invention to a semiconductor memory device such as a synchronous DRAM as shown in this embodiment, the following operational effects can be obtained. That is, (1) Synchronous DR requiring refresh operation
The AM or the like is provided with a switch means for dividing the memory array into two at a designated position in the bit line extension direction, and first and second sense amplifiers to which one end and the other end of the bit line are respectively coupled, Memory for comparing the address of the word line specified by the refresh control circuit and the address of the word line specified from the outside with the refresh control circuit for performing the autonomous refresh operation by sequentially specifying the word lines in the cycle By providing an address comparison circuit for determining the division position of the array and selectively operating the first and second sense amplifiers, two word lines are selected in the same memory array. ,
The effect that the normal read or write operation and the refresh operation can be simultaneously executed is obtained.

(2) According to the above item (1), the access side device such as the synchronous DRAM can be freed from refresh control and access restriction at the time of refresh. (3) According to the above items (1) and (2), it is possible to reduce the amount of hardware of the system including the synchronous DRAM and simplify the control, thereby promoting the cost reduction of the system. can get. (4) According to the above items (1) and (2), the access efficiency of the synchronous DRAM and the like is improved, and the synchronous DRA
The effect that the processing capability of the system including M and the like can be enhanced is obtained.

The invention made by the inventor of the present invention has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous DRAM can have a so-called multi-bit configuration in which a plurality of bits of storage data are simultaneously input or output, and the memory array MARY.
Further, it is possible to provide a plurality of banks each including a direct peripheral circuit. Further, the X address decoder XD and the refresh X address decoder XDF can be integrated, and two Y address decoders YD may be provided corresponding to the sense amplifiers SAL and SAR. Complementary bit lines B0 * to Bn * of memory array MARY and complementary common data line CDL
Switch MOSFETs NF and NG and NH and NI for selectively connecting * and CDR *
May be controlled by individual bit line selection signals.
In this case, the complementary common data lines CDL * and CDR can be commonly coupled above, for example, so that the write amplifier and the main amplifier of the data input / output circuit IO can be shared. Data input terminal Di
The n and the data output terminal Dout can be shared as a data input / output terminal, and it is not necessary to adopt a so-called address multiplex method as an address input method. Further, the block configuration of the synchronous DRAM and the names and combinations of the activation control signal, the address signal, and the internal control signal can adopt various embodiments.

In FIG. 2, the arrangement of the memory cells in the memory array MARY can be set arbitrarily. Further, the shared MOSFET for dividing the memory array MARY into two can be provided corresponding to, for example, a word line group in which eight lines are grouped, as shown in FIG. In this case, the probability that two word lines are simultaneously selected from the same word line group must be designed so as not to affect the refresh operation of the synchronous DRAM. In FIG. 3, each unit circuit of the sense amplifiers SAL and SAR includes a bit line precharge circuit for precharging the non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to Bn * to a predetermined level. You can Also, the drive MOSFET P
5, P6, N5 and N6 are a plurality of drive MOSFETs which are in a parallel form and are sequentially turned on after a predetermined time.
Can be replaced with Furthermore, the memory array MA
Various embodiments can be adopted for the specific circuit configuration of the RY and the sense amplifiers SAL and SAR, the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like.

In FIG. 4, the synchronous DRAM is
A clock enable signal for selectively enabling the clock signal CLK can be provided. Further, when the normal read or write mode or the refresh mode is individually executed, only the right sense amplifier SAR may be in the operating state. Further, the specific timing relationship of the start control signal and the internal control signal, the logic level, etc. are not restricted by this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM which is the background field of application has been described.
The present invention is not limited to this, and for example, a normal dynamic RA is provided on condition that competition between the normal read or write mode and the refresh mode is controlled.
Pseudo-static type R which can be applied to M and has a basic structure of synchronous DRAM or dynamic type RAM.
It can also be applied to various memory integrated circuits such as AM, and logic integrated circuit devices having these memory integrated circuits built therein.
INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device that requires at least a refresh operation of held data, and a device and a system including such a semiconductor memory device.

[0049]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a switch means for dividing the memory array into two at a specified position in the bit line extension direction and a first end and a second end of the bit line are respectively coupled to a synchronous DRAM or the like which requires a refresh operation.
And a second sense amplifier, and a refresh control circuit for sequentially designating word lines at a predetermined cycle and performing an autonomous refresh operation, and a word line address designated by the refresh control circuit and designation from the outside. The same memory by providing an address comparison circuit for comparing the address of the word line to determine the division position of the memory array and selectively putting the first and second sense amplifiers into the operating state. Since two word lines can be simultaneously selected in the array and a normal read or write operation and a refresh operation can be executed at the same time, an access side device such as a synchronous DRAM can be accessed for refresh control and refresh. You can free yourself from the constraints. As a result, the amount of hardware of the system including the synchronous DRAM and the like can be reduced and its control can be simplified to promote the cost reduction of the system, and the access efficiency of the synchronous DRAM and the like can be improved to enhance the processing capacity of the system. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.

2 is a circuit diagram showing a first embodiment of a memory array included in the synchronous DRAM of FIG.

3 is a circuit diagram showing an embodiment of a sense amplifier included in the synchronous DRAM of FIG.

4 is a signal waveform diagram showing an embodiment of a read mode of the synchronous DRAM of FIG.

5 is a connection diagram of a memory array and a sense amplifier in cycle A of the read mode of FIG.

FIG. 6 is a connection diagram of a memory array and a sense amplifier in cycle B of the read mode of FIG.

7 is a circuit diagram showing a second embodiment of a memory array included in the synchronous DRAM of FIG.

[Explanation of symbols]

MARY ... Memory array, XD ... X address decoder, XDF ... Refresh X address decoder, XB ... X address buffer, RC ... Refresh control circuit, AC ... Address comparison circuit, SA
L, SAR ... Sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO ...
Data input / output circuit, TG ... Timing generation circuit. Cs ... Information storage capacitor, Qa ... Address selection MOSFET, W0-Wm (WF0-WFm) ...
Word line, S0 to Sm-1 ... Shared control signal line,
B0 * to Bn * ... Complementary bit lines. CDL *, CDR * ... Complementary common data line, YS0
YSn ... Bit line selection signal, SPL, SPR, SN
L, SNR ... Common source line. USA0 to USAn ... Sense amplifier unit amplifier circuit. P1 to P6 ... P channel MOSFET, N1 to N
M ... N-channel MOSFET, V1-V2 ... Inverter.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Masashi Ozeki 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Inventor Hiratsuru ELS Engineering Co., Ltd. (72) Toshikazu Kawamoto Kodaira, Tokyo 5-20-1, Josuihoncho, Ichi-shi Hitate Cho-LS Engineering Co., Ltd.

Claims (3)

[Claims] 1. A switch means capable of dividing the memory array into two parts at designated positions in the bit line extension direction, and first and second sense amplifiers to which one end and the other end of the bit line are coupled, respectively. The normal read or write operation by the first or second sense amplifier, and the second or first
2. A semiconductor memory device capable of simultaneously performing a refresh operation by the sense amplifier. 2. The semiconductor memory device according to claim 1, wherein a refresh control circuit for sequentially designating word lines at a predetermined cycle and performing an autonomous refresh operation, an address of the word line designated by the refresh control circuit, and an external device. And an address comparison circuit for comparing the address of a designated word line to determine the division position of the memory array and selectively putting the first and second sense amplifiers into an operating state. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is present. 3. The semiconductor memory device comprises a synchronous D
3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a RAM, and the normal read or write operation and refresh operation are simultaneously started according to a predetermined clock signal supplied from the outside. .