JPH0712144B2 - Microwave analog divider - Google Patents

Description

TECHNICAL FIELD The present invention relates to a microwave analog frequency divider.

[Prior art and its problems]

Microwave communication devices, radar devices, measuring devices, etc. require local oscillators with good frequency stability. Particularly in recent years, the demand for this type of stabilized oscillator has rapidly increased with the practical use of direct satellite broadcasting. For this reason, research and development of stabilized oscillators having a configuration suitable for mass production are being actively carried out in various places. Although the mass production price can be reduced by using the monolithic IC configuration, in order to stabilize the local oscillation frequency with the monolithic IC configuration, the local oscillation frequency is divided and the result of phase comparison with a stable frequency is sent to the local oscillator. The method of feeding back is considered to be the most suitable. To realize this method, a frequency divider operating at a local oscillation frequency (microwave band) is required. Conventionally, an analog frequency divider has been used for this purpose, but the drawback is that the frequency division band is narrow.

FIG. 1 is a block diagram of an analog frequency divider conventionally used. In the figure, 5 is a terminal for inputting a frequency-divided signal, 1 is a mixer, 2 is a filter for passing signals of / 2 or less, 3 is an amplifier for amplifying signals of / 2, and 4 is a frequency divider of / 2. A signal output terminal 6 is a feedback circuit. With this configuration, a / 2 signal appears in the feedback loop.

In such a conventional analog divider, the feedback loop
Although the / 2 oscillator circuit is configured, in order to be able to oscillate, the phase delay including mixer 1, filter 2, amplifier 3 and feedback circuit 6 must satisfy the oscillation condition of / 2. I won't. For this reason, the frequency range that satisfies the oscillation conditions is narrow, and the ratio band is no more than about 20%.

Here, the fractional band is defined by the following equation when the frequency of the frequency-divided signal is f1 and the frequency of the frequency-divided signal is f2.

Ratio band = (f1−f2) / [(f1 + f2) / 2] [Object of the invention] The object of the present invention is to solve the drawback of the conventional analog frequency divider that the frequency dividing band is narrow, and to provide a microwave analog having a wide band. It is to provide a frequency divider.

[Structure of Invention]

The present invention relates to a first dual gate FET whose source is grounded.
A resistance circuit whose one end is grounded is provided in parallel with the drain electrode of the second drain electrode, and the drain electrode is AC-connected to the second gate electrode of the second dual gate FET whose drain is grounded.
The source electrode of the dual-gate FET is provided with a resistance circuit whose one end is grounded to take out the output, and the source electrode of the second dual-gate FET is connected to the first gate of the first dual-gate FET to form a resistance feedback circuit. And a terminal for inputting frequency-divided signals having mutually different phases to the second gate of the first dual-gate FET and the first gate of the second dual-gate FET. It is a circulator.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a high frequency equivalent circuit of a microwave analog frequency divider showing an embodiment of the present invention. In FIG. 2, the drain electrode 1 of the first dual gate FET 11 in which the source electrode 13 is grounded.
2 is provided with a parallel resistor 17, and the drain electrode 12 is
Second dual-gate FET 1 with drain electrode 21 grounded
8 to the second gate electrode 20. The source electrode 22 of the second dual gate FET 18 is provided with a resistor 23 whose other end is grounded in series, and the source electrode 22 and the first gate electrode 14 of the first dual gate FET 11 have a resistor between them. 2
It is tied with 4. Reference numerals 16 and 25 are terminals for inputting divided signals having different phases. The terminal 16 is connected to the second gate electrode 15 and the terminal 25 is connected to the first gate electrode 19.

The output of the divided signal is taken out from the source electrode 22 of the second dual gate FET 18.

The present invention will now be described with reference to FIG. The dual gate FET shown in FIG. 2 is equivalent to two vertically stacked single gate FETs as shown in FIG.
Therefore, when it is disassembled and described, it becomes as shown in FIG.
The gates 16 and 25 (the second gate of the first dual gate FET of the present invention and the first gate of the second dual gate) are transfer gates, and the gate 14 (the first gate of the first dual gate FET). Is the inverter input terminal, gate 2
0 (the second gate of the second dual gate FET) is the buffer input terminal. Dual gate FET2 in this figure
Paying attention to, the buffer amplifier is composed of a single-gate FET having a gate 20 and a load resistor 23, but a single-gate FET having a gate 25 forming a transfer gate is formed inside the buffer amplifier.

Returning to FIG. 2, the operation of the present invention will be described.

Here, the first gate electrode 14 of the first dual gate FET 11 is
If a positive-phase signal appears, a reverse phase appears on the drain electrode 12, a reverse phase also appears on the source electrode 22 of the second dual gate FET 21, and this reverse phase returns to the first gate electrode 14. To be done. FIG. 4 is a diagram for explaining the relationship between the input voltage v1 and the output voltage v2. Corresponding to FIG.
v1 and v2 indicate the voltage between the terminal 14 and the ground and the voltage between the terminal 20 and the ground, respectively. gm is the first of dual gate FET1
The transconductance of the gate, j is an imaginary unit. At this time, v2 / v1 = -gmR / (1 + jωRC), and when ω is sufficiently smaller than 1 / RC, v2 / v1 = -g
It becomes mR and the opposite phase can be maintained on the output side. When ω becomes large and the cutoff frequency ωRC = 1, v2 / v1 = -gm / (1 + j) and the output deviates from the complete opposite phase. If the gain of the feedback circuit is greater than 1, this circuit will oscillate. Gate length is 1.0
When using a GaAs dual gate FET of about μm to 0.5 μm
Up to about 6 GHz, in the source grounded circuit, a signal with almost the opposite phase of the input appears on the output side, and with the drain grounded circuit, a signal in the same phase as the input appears on the output side, and the gain is 5 dB when the source is grounded. In the case of grounded drain, the circuit can oscillate because it can be about 0 dB. Therefore, the circuit in Fig. 2 has Ga
It is possible to oscillate from low frequency up to about 6GHz by using As dual gate FET. F / 2 (f
If the feedback gain of the signal of the frequency-divided signal) is 1 or more, the signal of f can be divided. In the circuit of the present embodiment, since the feedback gain is sufficiently obtained up to 6 GHz, the frequency can be divided up to 12 GHz. Therefore, when mixing is performed using the gate terminals 16 and 25, in this circuit, = 6 GHz to 12 GHz.
Frequency division becomes possible by performing the same operation as the conventional circuit of Fig. 1 over one octave of GHz. The frequency dividing operation of this embodiment will be described with reference to the drawings. Figure 3 shows a dual gate
It is a figure for demonstrating operation | movement of FET.

The operation of the dual gate FET of FIG. 3 (A) is equivalent to the operation of stacking the two single gate FETs of FIG. 3 (B). In this figure, when a large signal is input to the second gate and the drain current is turned on / off, it is shown in FIG. 3 (C).
As shown in FIG. 5, it becomes a cascade connection circuit of the amplifying transistor and the switch. This circuit has a mixer function and outputs the sum and difference frequencies of the signals applied to the first and second gates. Therefore, FIG. 3 (A) can be represented as the mixer of FIG. 3 (D).

That is, the load on the drain terminal 12 in FIG.
And a second gate input capacitance (C) of the dual gate FET 18 in a parallel circuit. This RC parallel circuit becomes a low-pass filter, and the voltage gain is cut off at the frequency of fc = 1 / (2πRC).

Although this fc is determined by the values of R and C, it is usually necessary to increase R to increase the gain and to increase the gate width of the dual gate FET in order to secure the output current to some extent. Therefore, C does not become so small. Normal Ga
When AsFET is used, fc is about 6 GHz.

The dual gate FET 18 serves as a source follower amplifier circuit having the terminal 20 as an input terminal, and serves as a buffer amplifier circuit. When this circuit is fed back to the input side via the resistor 24, it becomes a so-called one-stage ring oscillator, and this feedback loop can oscillate at 6 GHz or less, which has a sufficient gain. Thus, FIG. 2 operates as an analog frequency dividing circuit. Since terminal 16 and terminals 20 and 19 have an opposite phase relationship, in order to strengthen the divided signal, 16 and
25 must be out of phase with each other.

The frequency-divided signals input to the terminals 16 and 25 may have opposite phases up to about 12 GHz. However, as described above, the oscillation frequency of the feedback loop shown in FIG. 2 can be made higher than 6 GHz if the proper phase relationship is maintained instead of the perfect opposite phase. This means that the maximum dividing frequency will be 12 GHz or higher. Unlike a digital circuit, in an analog circuit, continuous oscillation becomes possible if the feedback loop gain is 1 or more and positive feedback is achieved. 6 GHz here means a 3 dB gain reduction frequency, and at this time, loop gain> 1. Therefore, it is possible to cause oscillation by maintaining an appropriate phase relationship with respect to the minute signal.

〔The invention's effect〕

In this embodiment, since the signal of f / 2 can exist from DC to 6 GHz, the frequency f of the divided frequency is 6 GHz <f <12 GHz. Therefore, the frequency division band is 6 to 12 GHz, which is one octave.
The bandwidth of one octave is (12-6) / [(12 + 6) / 2] = 6/9 = 67%. The conventional analog frequency divider is designed with an LC resonator for f / 2, and the ratio band is about 20%, depending on the number of LC stages. According to the present invention, the frequency division ratio band of the microwave analog frequency divider, which is about 20% at the maximum, can be expanded to one octave (ratio band 67%) or more. It has the effect that it can be widely applied to various microwave systems such as ICs for commercial use.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional microwave analog frequency divider, and FIG. 2 is a block diagram of a microwave analog frequency divider showing an embodiment of the present invention. FIG. 3, FIG. 4, and FIG. 5 are views for explaining the present invention. 11 …… First dual gate FET, 12 …… Drain electrode, 13 …… Source electrode, 14 …… First gate electrode, 15 ……
2nd gate electrode, 16 ... Input terminal, 17 ... Parallel resistance, 18
...... Second dual gate FET, 19 ...... First gate electrode, 20 ...... Second gate electrode, 21 ...... Drain electrode, 22 ...
… Source electrode, 23 …… resistor, 24 …… resistor, 25 …… input terminal

Claims (1)

[Claims] 1. A first dual-gate FE whose source is grounded.
A resistance circuit whose one end is grounded is provided in parallel with the drain electrode of T, and the drain electrode is AC-connected to the second gate electrode of the second grounded drain dual-gate FET. The source electrode is provided with a resistance circuit with one end grounded to take out the output, and the source electrode of the second dual gate FET is used as the first dual gate FET.
A terminal for inputting divided signals having different phases to the second gate of the first dual gate FET and the first gate of the second dual gate FET by connecting to the first gate of Microwave analog frequency divider characterized by having.