[go: up one dir, main page]

JPH0697101A - Fabrication of thin film transistor - Google Patents

Fabrication of thin film transistor

Info

Publication number
JPH0697101A
JPH0697101A JP4269290A JP26929092A JPH0697101A JP H0697101 A JPH0697101 A JP H0697101A JP 4269290 A JP4269290 A JP 4269290A JP 26929092 A JP26929092 A JP 26929092A JP H0697101 A JPH0697101 A JP H0697101A
Authority
JP
Japan
Prior art keywords
thin film
film
substrate
tft
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4269290A
Other languages
Japanese (ja)
Inventor
Masamune Kusunoki
雅統 楠
Koji Mori
孝二 森
Nobuaki Kondo
信昭 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP4269290A priority Critical patent/JPH0697101A/en
Publication of JPH0697101A publication Critical patent/JPH0697101A/en
Pending legal-status Critical Current

Links

Landscapes

  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To fabricate a TFT element having improved electric characteristics and reliability efficiently by performing a step for heat treating an amorphous semiconductor thin film with optical energy prior to formation of gate dielectric film and crystalizing the amorphous semiconductor thin film in an atmospheric gas having low thermal conductivity which allows removal of impurities from the film surface. CONSTITUTION:TFT elements are formed on a substrate 1 at least the surface thereof is composed of a dielectric material. The fabrication method comprises a step for heat treating an amorphous semiconductor thin film 2 with optical energy prior to formation of a gate dielectric film 7 thus crystalizing the thin film 2 and the step is carried out in an atmospheric gas having low thermal conductivity which allows removal of impurities from the surface of the thin film 2. For example, an a-Si film 2 is deposited on an insulating substrate 1 which is then transferred into halogen gas atmosphere 4. The substrate 1 is then irradiated with ArF excimer laser beam 5 from above with the temperature of the substrate 1 being sustained at 150 deg.C in order to remove impurities from the surface of the film 2 and to crystalize the a-Si film 2 thus obtaining poly-Si 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【技術分野】本発明は、高性能化した薄膜トランジスタ
(TFT)素子を効率良く製造する方法に関するもので
ある。特に素子の高性能化と製造効率化を図る為のもの
である。
TECHNICAL FIELD The present invention relates to a method for efficiently manufacturing a high performance thin film transistor (TFT) element. In particular, it is intended to improve the performance of the device and improve the manufacturing efficiency.

【0002】[0002]

【従来技術】近年、液晶ディスプレイにおいてはその大
面積化と駆動素子の高速化の要請が高まっている。大面
積化のためのディスプレイ基板は、安価なガラス基板が
好ましく、駆動素子の高速化にはアクティブマトリック
ス方式を用いるのが良い。そのアクティブマトリックス
方式を実現するには基板上に薄膜トランジスタ(以下、
TFTと略称する。)を形成しなければならない。従来
技術ではガラス基板上にダメージのないプロセス温度で
形成されるTFTは、主にa−Siを活性層に持つTF
Tであったが、最近になってa−Siを短波長のパルス
レーザを用いてレーザアニールすることによって、より
高速駆動が可能なポリSiTFTができるようになって
いる。例えば、特開昭62−36854号においては、
ガラス基板上または、熱酸化したSiウエハ上にa−S
iを形成した後にレーザアニールにより結晶化してい
る。パルスレーザによるアニールでは、被照射膜の溶融
固化時間はnsecオーダーと非常に短いために膜は溶
融状態から急速に固化し膜中の結晶粒径も数百nmとな
り、それ以上は大きくすることができないので、移動度
などの薄膜の電気的特性にも限界がある。そこで被照射
膜の溶融固化時間を何らかの方法で長くすることにより
結晶粒径を大きくする方法が求められてきた。一方、T
FTを形成する場合、ゲート絶縁膜と半導体薄膜との界
面には、TFTの電気特性や信頼性上の問題となるアル
カリ金属や重金属などの物質が存在している場合があ
り、その不純物を除去することが必要となる。先行技術
では、ゲート絶縁膜デポ前に多結晶シリコン表面を洗浄
する工程が含まれていない場合には、多結晶シリコン/
ゲート絶縁膜界面に不純物が存在している可能性が大き
く、さらに界面特性向上のためのレーザ照射を行っても
その不純物が界面付近に拡散し、TFT特性の依頼性が
低下する原因となりうる。またウエットクリーニングな
どで表面クリーニングを行うとしても基板の大面積化に
よる薬品量の増大、廃液処理の困難性、工程の自動化の
要請などから薬液を使うウエットクリーニングには不便
な点がある。それに代わる技術としてドライクリーニン
グがある。しかしこれまではプラズマやイオンなどを利
用して行ってきたが制御性は十分と言えず、さらに損傷
や二次汚染の問題がある。そこで低ダメージの表面クリ
ーニング方法の開発が求められてきた。
2. Description of the Related Art In recent years, there has been an increasing demand for a liquid crystal display having a large area and a high speed driving element. The display substrate for increasing the area is preferably an inexpensive glass substrate, and it is preferable to use the active matrix method for speeding up the driving element. To realize the active matrix method, a thin film transistor (hereinafter,
It is abbreviated as TFT. ) Must be formed. In the conventional technology, a TFT formed on a glass substrate at a process temperature without damage is mainly a TF having an a-Si active layer.
However, recently, by annealing the a-Si with a pulsed laser having a short wavelength, it is possible to obtain a poly-Si TFT capable of driving at a higher speed. For example, in JP-A-62-36854,
A-S on a glass substrate or a thermally oxidized Si wafer
After i is formed, it is crystallized by laser annealing. In the annealing by the pulsed laser, the melting and solidification time of the irradiated film is very short on the order of nsec, so that the film rapidly solidifies from the molten state and the crystal grain size in the film becomes several hundreds nm, and it is possible to make it larger than that. Therefore, there is a limit to the electric properties of the thin film such as mobility. Therefore, there has been a demand for a method of increasing the crystal grain size by lengthening the melt-solidification time of the irradiated film by some method. On the other hand, T
In the case of forming FT, substances such as alkali metal and heavy metal, which pose a problem on the electrical characteristics and reliability of the TFT, may exist at the interface between the gate insulating film and the semiconductor thin film, and the impurities are removed. Will be required. In the prior art, if the step of cleaning the polycrystalline silicon surface before the gate insulating film deposition is not included, the polycrystalline silicon /
Impurities are likely to be present at the interface of the gate insulating film, and even if laser irradiation for improving the interface characteristics is performed, the impurities diffuse near the interface, which may cause a decrease in the TFT characteristic requirements. Even if surface cleaning is performed by wet cleaning or the like, wet cleaning using a chemical solution is inconvenient due to an increase in the amount of chemicals due to an increase in the area of the substrate, the difficulty of waste liquid treatment, and the demand for automation of the process. Dry cleaning is an alternative technology. However, until now, plasma and ions have been used, but the controllability is not sufficient, and there are problems of damage and secondary pollution. Therefore, development of a low-damage surface cleaning method has been required.

【0003】[0003]

【目的】本発明は、電気的特性と信頼性を向上させた薄
膜トランジスタ(TFT)素子を効率的に製造する方法
の提供を目的とする。
An object of the present invention is to provide a method for efficiently manufacturing a thin film transistor (TFT) element having improved electrical characteristics and reliability.

【0004】[0004]

【構成】本発明は、前記従来技術の問題点を解消するた
めに、絶縁基板上に形成された非晶質半導体薄膜を熱伝
導率(k)が低いガス雰囲気中、好ましくは熱伝導率
(k)が0.01(W・m-1・K-1、0℃での値)以下
の低いガス中においてパルス的なレーザによりレーザア
ニールすることで、前記非晶質半導体薄膜が溶融し固化
する過程で発生する熱の伝導を悪くし前記薄膜中の温度
変化を緩やかにすることができ、その結果アニール後の
前記薄膜中の結晶粒径を従来のものと比べて大きくする
ことができる。また、前記アニール時の雰囲気ガスとし
て、熱伝導率(k)が前記の0.01以下の値であり、
かつゲート絶縁膜と半導体薄膜との界面に存在した場合
にTFTの電気特性や信頼性上の問題となるアルカリ金
属や重金属粒子など(例えば、Fe、Cu、Ni、C
r、Mg、Al、Na、Ca)を膜表面から除去するこ
とのできる物質を用いれば、薄膜の結晶化と膜表面のク
リーニングを同時に行うことができ、製造工程の簡単化
が画れるだけでなく、TFTの電気的特性は向上し、半
導体/ゲート絶縁膜界面の洗浄度も向上するので素子の
信頼性も向上する。このような雰囲気ガスとしては、例
えば以下の表1に示すような塩素ガスやフレオンガスが
挙げられる。なお表1中の値は、0℃での値である。
According to the present invention, in order to solve the above-mentioned problems of the prior art, an amorphous semiconductor thin film formed on an insulating substrate is heated in a gas atmosphere having a low thermal conductivity (k), preferably the thermal conductivity (k). The amorphous semiconductor thin film is melted and solidified by laser annealing with a pulsed laser in a low gas whose k) is 0.01 (W · m −1 · K −1 , value at 0 ° C.) or less. The conduction of heat generated in the process can be deteriorated and the temperature change in the thin film can be made gentle, and as a result, the crystal grain size in the thin film after annealing can be made larger than that of the conventional one. The thermal conductivity (k) of the atmosphere gas at the time of annealing is 0.01 or less, and
Moreover, when present at the interface between the gate insulating film and the semiconductor thin film, alkali metal or heavy metal particles (eg Fe, Cu, Ni, C, etc.) which pose a problem in the electrical characteristics and reliability of the TFT.
If a substance capable of removing (r, Mg, Al, Na, Ca) from the film surface is used, crystallization of the thin film and cleaning of the film surface can be performed at the same time, which simplifies the manufacturing process. In addition, the electrical characteristics of the TFT are improved, and the cleaning degree of the semiconductor / gate insulating film interface is also improved, so that the reliability of the device is also improved. Examples of such an atmosphere gas include chlorine gas and freon gas as shown in Table 1 below. The values in Table 1 are values at 0 ° C.

【表1】 一般に結晶化プロセスにおいては、その波長に対する膜
の光吸収率と、その波長をもった光エネルギーが熱エネ
ルギーになった時の膜中の熱伝達の制御が重要になって
いる。a−Si:H膜の結晶化には400nm以下の波
長が必要となり、基板に対する熱的ダメージを少なくす
るには、パルス照射が都合よい。またハロゲンを活性化
するには、400nm以下の波長が必要となる。以上の
事柄を考えると、エキシマレーザは全ての条件を満足す
るので好ましいものではあるが、光エネルギーとしては
上記のレーザ光以外に、例えば低圧Hgランプ、重水素
ランプ等が挙げられる。ここで述べた低圧Hgランプや
重水素ランプをシャッターなどで照射をパルス的に行え
ば、結晶化プロセスにおいてパルスレーザと同様な効果
が期待できる。
[Table 1] Generally, in the crystallization process, it is important to control the light absorptance of the film with respect to the wavelength and the control of heat transfer in the film when the light energy having the wavelength becomes heat energy. Crystallization of the a-Si: H film requires a wavelength of 400 nm or less, and pulse irradiation is convenient for reducing thermal damage to the substrate. Further, a wavelength of 400 nm or less is required to activate halogen. Considering the above matters, the excimer laser is preferable because it satisfies all the conditions, but as the light energy, in addition to the above laser light, for example, a low pressure Hg lamp, a deuterium lamp and the like can be mentioned. If the low-pressure Hg lamp or the deuterium lamp described here is irradiated in a pulsed manner with a shutter or the like, an effect similar to that of a pulsed laser can be expected in the crystallization process.

【0005】以下図面に基づいて本発明の実施例を説明
する。図1の(a)〜(f)は、本発明による多結晶シ
リコンTFT素子の作製プロセスの各工程を示し、図2
の(a)〜(c)は、本発明における非晶質のシリコン
上の不純物除去と非晶質シリコンの結晶化の概念を模式
的に表す図である。 実施例1 (1) まず有機洗浄をした絶縁基板上1にプラズマC
VD法によりa−Si膜2を膜厚1000Å堆積させ
た。堆積条件は基板温度250℃、真空度1×10-5
orrである〔図1(a)参照〕。 (2) 次に基板1をハロゲンガス雰囲気(5N純度の
塩素ガス、20torr、50sccm)4に移動させ
る〔図1(b)参照〕。 (3) そして上記雰囲気中の基板を150℃に保ち、
基板に対して上方からArfエキシマレーザ(波長19
3nm、半値幅10nsec)5をレーザパワー550
mJ/cm2、ショット数20ショットの照射条件によ
り膜上の不純物除去と非晶質シリコンの結晶化を行っ
た。その結果多結晶シリコン6を得た〔図1(c)参
照〕。 (4) 次に基板1上に基板温度450℃にして常圧C
VD法によりゲート絶縁膜7を膜厚1500Å堆積させ
た〔図1(d)参照〕。 (5) さらに基板1を室温に保ち、真空度1×10-5
torrの状態で前述のArfエキシマレーザを照射す
ることにより多結晶シリコン6とゲート絶縁膜7との界
面特性を向上させた〔図1(e)参照〕。 (6) 最後に公知技術によりソース/ドレインのコン
タクト形成、不純物導入、活性化、ゲート電極、ソース
/ドレイン電極形成、層間絶縁膜形成を経てMOSTF
T素子を形成した結果、良好な電気特性と高い信頼性を
得ることができた〔図1(f)参照〕。
An embodiment of the present invention will be described below with reference to the drawings. 1 (a) to 1 (f) show each step of the manufacturing process of the polycrystalline silicon TFT element according to the present invention, and FIG.
(A) to (c) of FIG. 3 are diagrams schematically showing the concept of removing impurities on amorphous silicon and crystallization of amorphous silicon in the present invention. Example 1 (1) First, plasma C was applied on an insulating substrate 1 that had been organically cleaned.
An a-Si film 2 having a film thickness of 1000 Å was deposited by the VD method. The deposition conditions are a substrate temperature of 250 ° C. and a vacuum degree of 1 × 10 −5 t.
orr [see FIG. 1 (a)]. (2) Next, the substrate 1 is moved to a halogen gas atmosphere (5N purity chlorine gas, 20 torr, 50 sccm) 4 [see FIG. 1 (b)]. (3) And keeping the substrate in the above atmosphere at 150 ° C.
Arf excimer laser (wavelength 19
3 nm, half width 10 nsec) 5 laser power 550
Impurities on the film were removed and amorphous silicon was crystallized under the irradiation conditions of mJ / cm 2 and 20 shots. As a result, polycrystalline silicon 6 was obtained [see FIG. 1 (c)]. (4) Next, the substrate temperature is set to 450 ° C. and the atmospheric pressure C is applied to the substrate 1.
A gate insulating film 7 having a film thickness of 1500 Å was deposited by the VD method [see FIG. 1 (d)]. (5) Further, the substrate 1 is kept at room temperature and the degree of vacuum is 1 × 10 −5.
The interface characteristics between the polycrystalline silicon 6 and the gate insulating film 7 were improved by irradiating the Arf excimer laser in the state of torr [see FIG. 1 (e)]. (6) Finally, according to a known technique, MOSTF is performed through source / drain contact formation, impurity introduction, activation, gate electrode, source / drain electrode formation, and interlayer insulating film formation.
As a result of forming the T element, good electric characteristics and high reliability could be obtained [see FIG. 1 (f)].

【0006】[0006]

【効果】(1) 非晶質シリコンが出発膜なのでデポ温
度(基板温度)を多結晶シリコンのデポ温度(〜600
℃以上)よりも低温(300℃〜R.T.)にできるた
め基板選択の自由度が向上する。 (2) 非晶質半導体薄膜の熱処理と、該薄膜上の不純
物除去を同一系内で同時に処理することにより、プロセ
ス工程の低減が画られ、かつ信頼性の向上した素子が提
供される。 (3) 熱伝導率(k)が0.01(W・m-1・K-1
0℃での値)以下の範囲にある雰囲気ガスを使用するこ
とにより、結晶粒径を大きくでき、電子特性の向上した
素子が得られる。 (4) 雰囲気ガスとしてハロゲンガスを選択し、この
ガスにレーザエネルギーを与え活性化させることで膜表
面の金属粒子などの不純物が効率的に除去される。
[Effects] (1) Since amorphous silicon is the starting film, the deposition temperature (substrate temperature) is set to that of polycrystalline silicon (up to 600).
Since the temperature can be lower than 300.degree. C.) (300.degree. C. to RT), the degree of freedom in substrate selection is improved. (2) By simultaneously performing the heat treatment of the amorphous semiconductor thin film and the removal of impurities on the thin film in the same system, the number of process steps can be reduced and an element with improved reliability can be provided. (3) Thermal conductivity (k) is 0.01 (W · m −1 · K −1 ,
By using an atmosphere gas in the range of (value at 0 ° C.) or less, the crystal grain size can be increased and an element with improved electronic characteristics can be obtained. (4) A halogen gas is selected as an atmospheric gas, and laser energy is applied to this gas to activate it, whereby impurities such as metal particles on the film surface are efficiently removed.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1の(a)〜(f)は、実施例1における多
結晶シリコンTFT素子の作製プロセス(1)〜(6)
の各工程の素子の構造を模式的に示す図である。
1A to 1F are manufacturing processes (1) to (6) of a polycrystalline silicon TFT element according to a first embodiment.
It is a figure which shows typically the structure of the element of each process of.

【図2】図2の(a)〜(c)は、本発明における非晶
質シリコン上の不純物除去および該非晶質シリコンの結
晶化の概念を模式的に示す図である。
2 (a) to 2 (c) are diagrams schematically showing the concept of removing impurities on amorphous silicon and crystallization of the amorphous silicon according to the present invention.

【符号の説明】[Explanation of symbols]

1 絶縁基板 2 非晶質シリコン 3 不純物層 3′ 不純物 4 雰囲気ガス 5 レーザ光 6 多結晶シリコン 7 ゲート絶縁膜 8 ゲート電極 9 層間絶縁膜 10 ソース/ドレイン電極 11 ハロゲン分子 11′ ハロゲン化合物 11″ 活性化ハロゲン 1 Insulating Substrate 2 Amorphous Silicon 3 Impurity Layer 3'Impurity 4 Atmospheric Gas 5 Laser Light 6 Polycrystalline Silicon 7 Gate Insulating Film 8 Gate Electrode 9 Interlayer Insulating Film 10 Source / Drain Electrode 11 Halogen Molecules 11 ′ Halogen Compound 11 ″ Active Halogenated halogen

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも表面が絶縁物質である基板上
に薄膜トランジスタ(TFT)素子を形成する方法にお
いて、該方法がゲート絶縁膜形成前に非晶質半導体薄膜
を光エネルギーを用い熱処理して該薄膜を結晶化する工
程を含み、かつ該工程を前記薄膜の膜面から不純物を除
去することのできる低熱伝導率の雰囲気ガス中で行うこ
とを特徴とする薄膜トランジスタ素子(TFT)の製造
法。
1. A method of forming a thin film transistor (TFT) element on a substrate having at least a surface of an insulating material, the method comprising heat-treating an amorphous semiconductor thin film using light energy before forming a gate insulating film. A method of manufacturing a thin film transistor element (TFT), which comprises the step of crystallizing the step of: and performing the step in an atmosphere gas of low thermal conductivity capable of removing impurities from the film surface of the thin film.
【請求項2】 請求項1における非晶質半導体薄膜を熱
処理する際の雰囲気ガスの熱伝導率(k)が以下の範囲
にあることを特徴とする薄膜トランジスタ素子(TF
T)の製造法。 k≦0.01 (W・m-1・K-1、0℃での値)
2. A thin film transistor element (TF) characterized in that the thermal conductivity (k) of an atmospheric gas when heat treating the amorphous semiconductor thin film according to claim 1 is in the following range.
Manufacturing method of T). k ≦ 0.01 (W · m −1 · K −1 , value at 0 ° C)
【請求項3】 請求項1または2における雰囲気ガスが
ハロゲンを含有するガスであることを特徴とする薄膜ト
ランジスタ素子(TFT)の製造法。
3. A method of manufacturing a thin film transistor element (TFT), wherein the atmosphere gas according to claim 1 or 2 is a gas containing halogen.
【請求項4】 光エネルギーを用いる熱処理が、400
nm以下の波長による光で行われることを特徴とする請
求項1記載の薄膜トランジスタ素子(TFT)の製造
法。
4. The heat treatment using light energy is 400
The method for manufacturing a thin film transistor element (TFT) according to claim 1, wherein the method is performed with light having a wavelength of nm or less.
【請求項5】 光エネルギーを用いる熱処理が、エキシ
マ・レーザによるアニールであることを特徴とする請求
項1記載の薄膜トランジスタ素子(TFT)の製造法。
5. The method of manufacturing a thin film transistor element (TFT) according to claim 1, wherein the heat treatment using light energy is annealing by an excimer laser.
JP4269290A 1992-09-11 1992-09-11 Fabrication of thin film transistor Pending JPH0697101A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4269290A JPH0697101A (en) 1992-09-11 1992-09-11 Fabrication of thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4269290A JPH0697101A (en) 1992-09-11 1992-09-11 Fabrication of thin film transistor

Publications (1)

Publication Number Publication Date
JPH0697101A true JPH0697101A (en) 1994-04-08

Family

ID=17470291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4269290A Pending JPH0697101A (en) 1992-09-11 1992-09-11 Fabrication of thin film transistor

Country Status (1)

Country Link
JP (1) JPH0697101A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366010B1 (en) * 1997-04-25 2003-02-19 샤프 가부시키가이샤 Crystallization method of thin semiconductor film and laser beam radiation apparatus used therefor
US6939816B2 (en) * 2000-11-10 2005-09-06 Texas Instruments Incorporated Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100366010B1 (en) * 1997-04-25 2003-02-19 샤프 가부시키가이샤 Crystallization method of thin semiconductor film and laser beam radiation apparatus used therefor
US6939816B2 (en) * 2000-11-10 2005-09-06 Texas Instruments Incorporated Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface

Similar Documents

Publication Publication Date Title
KR100581626B1 (en) Method of forming semiconductor thin film on plastic substrate and plastic substrate
JP3586558B2 (en) Method for reforming thin film and apparatus used for implementing the method
JP3165304B2 (en) Semiconductor device manufacturing method and semiconductor processing apparatus
JPH08330598A (en) Treatment method of semiconductor film and manufacture of semiconductor device
JP3221251B2 (en) Amorphous silicon crystallization method and thin film transistor manufacturing method
JPH05326429A (en) Method and apparatus for laser treatment
JPH0697101A (en) Fabrication of thin film transistor
KR100305255B1 (en) Method for manufacturing a poly-crystal silicon thin film
JPH0917729A (en) Manufacture of semiconductor device
JPH05198507A (en) Manufacture of semiconductor
JPH0955509A (en) Manufacture of semiconductor device
JP3404928B2 (en) Manufacturing method of thin film integrated circuit
JP3032542B2 (en) Method for manufacturing thin film transistor
JP2001127301A (en) Semiconductor device and manufacturing method therefor
JP3612018B2 (en) Method for manufacturing semiconductor device
JP3612009B2 (en) Method for manufacturing semiconductor device
JP4016539B2 (en) Thin film semiconductor manufacturing apparatus and thin film semiconductor manufacturing method
JPH09232584A (en) Method of manufacturing semiconductor device
JPH09246182A (en) Semiconductor device and manufacture thereof
JPH08139331A (en) Method of manufacturing thin film transistor
JP2004356637A (en) Tft and manufacturing method therefor
JPH08293464A (en) Manufacture of semiconductor substrate and semiconductor device
JPH04180624A (en) Formation of pattern
JPH05335337A (en) Manufacture of thin-film transistor
JP3407842B2 (en) Method for manufacturing thin film transistor

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 9

Free format text: PAYMENT UNTIL: 20070814

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080814

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 10

Free format text: PAYMENT UNTIL: 20080814

FPAY Renewal fee payment (prs date is renewal date of database)

Year of fee payment: 11

Free format text: PAYMENT UNTIL: 20090814

LAPS Cancellation because of no payment of annual fees