JPH0696530A - Device for clock control of optical disk apparatus - Google Patents

Abstract

PURPOSE:To prevent the pulling-out of synchronism by a method wherein the phase difference between a channel clock and the position of a pit is detected and the channel clock is controlled by selecting one out of a plurality of pieces of phase-difference information. CONSTITUTION:When a select signal from a comparator 20 is decided, one set is selected from phase-comparison result signals by a selector 40. Phase information PU and PD which have been selected are sent to a charge pump 41, converted into an analog signal corresponding to the sign and the magnitude of a phase shift and moves a channel clock (CHCLK) as an output from a VCO 43 to a direction eliminating the phase shift. When this operation is repeated, it is possible to obtain the channel clock (CHCLK) which is synchornized with a pit string on a disk.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control device for an optical disc device for recording and reproducing information on an optical recording medium (optical disc or the like).

[0002]

2. Description of the Related Art In an optical disk drive using a sample servo type optical disk, the position of a clock pit for timing extraction in a servo area provided on the disk is detected, and a PLL is constructed for this detection signal. Generate a clock. This clock serves as a reference for all the operations of the drive, such as the timing for detecting a tracking error, the timing for reading an access code for track count during seek, and the data write / read.

Japanese Patent Laid-Open No. 3-266263 discloses a control method of a reference clock in which intensity signals of reflected light are sampled at timings immediately before and immediately after a clock pit and the clock phase is corrected so that both are equal. It is disclosed.

[0004]

In the sample servo system, all the operations are performed based on the above-mentioned reference clock, so that the reference clock is generated even when tracking is not performed, that is, even during seek. Must be in sync.

However, during seek, the spot does not always pass over the track in the servo area, so that the degree of modulation of the reflected light intensity at the clock pit is lower than that in the tracking state. .

As disclosed in Japanese Patent Laid-Open No. 3-266263,
When detecting the phase shift of the reference clock from the difference in the reflected light intensity immediately before and immediately after the clock pit, if the modulation degree of the reflected light intensity decreases, the sensitivity and accuracy of the phase shift detection decrease, and the clock However, there is a drawback that the synchronization deviation of the becomes large.

Further, in order to improve the characteristics of data read, the NA of the objective lens is changed to narrow the spot diameter, or a short wavelength light source for high density recording and reproduction is used to use a light spot smaller than before. When a conventional disk is accessed by using the conventional method, the spot diameter becomes smaller with respect to the size and interval of the clock pits, and the degree of modulation of reflected light tends to decrease. In particular, when the spot diameter on the disk becomes small to some extent, when the light spot moves between tracks, the reflected light intensity does not change even at the clock pit position, and it becomes impossible to detect the phase shift of the clock, resulting in loss of synchronization. It may cause it.

As a phase shift detection method other than the above, a timing indicating a peak position of the reflected light intensity, that is, a central position of the pit is obtained from the differential waveform of the reflected light intensity and is generated based on this signal and a clock. There is a method of knowing the phase shift from the time difference from the signal. Also in this case, if the modulation degree of the reflected light intensity in the clock pits decreases between tracks, binarization (peak detection) fails and the phase shift amount cannot be detected. Even if binarization is possible, Since the accuracy of detecting the peak position relatively decreases, there is a problem that clock synchronization becomes unstable.

Further, if there is a defect in the clock pit, even during the tracking servo, there is a possibility that the phase shift of the clock cannot be detected and the synchronization is lost due to the defect.

The present invention has been made in view of the above circumstances. When the spot diameter is small and the spots are located between the tracks, the reflected light intensity signal cannot be sufficiently modulated at the clock pit, or when the pit is not formed. Provided is a clock control device for an optical disk device, which can always generate a stable channel clock even when there is a physical defect in the track, and can prevent loss of synchronization during tracking servo, seek, etc. With the goal.

[0011]

A clock controller for an optical disk apparatus according to the present invention irradiates a light beam onto an optical disk in which a servo area consisting of a plurality of pits is intermittently provided on an information track. A clock control device of a sample servo type optical disc device for detecting a specific pit among the plurality of pits by detecting the intensity of reflected light from the optical disc of the light beam and generating a channel clock based on the detected pit. Any one of a phase difference detecting means for independently detecting a timing shift between the pit position and the channel clock in at least two pits of the plurality of pits in the servo area, and a plurality of outputs of the phase difference detecting means And selecting means for selecting and outputting one of the channels, and based on the output of the selecting means, the channel Perform phase control of the lock.

Since the channel clock is controlled based on the phase shift information detected in at least two pits of the plurality of pits in the servo area, the channel clock can always be corrected by the accurate phase shift information, and the synchronization can be achieved. The deviation can be reduced.

[0013]

1 to 6 relate to a first embodiment, and FIG.
4 is a block diagram showing the configuration of pits in the servo area of a sample servo type optical disc, FIG. 2 is a block diagram showing the configuration of a clock control device, FIG. 3 is a circuit diagram showing the detailed configuration of the waveform shaping circuit of FIG. 2, and FIG. 2 is a circuit diagram showing a detailed configuration of the channel clock generating means in FIG. 2, FIG. 5 is a timing diagram showing timings of respective signals when an optical spot passes through a servo area almost right above a track, and FIG. 6 is during seek. FIG. 6 is a timing chart showing the timing of each signal when a light spot passes between tracks.

FIG. 1 shows an example of a servo area of a sample servo type optical disk, and the upper part of the drawing corresponds to the outer peripheral side of the disk.

In FIG. 1, 1 represents the center of the track. Reference numeral 2 is an access code for speed detection and track counting by reading during a seek.
It is a Gray code in which 2 bits out of 1 are 1.
Generally, the pattern changes every two tracks, and the pattern repeats to return to the original pattern on 16 tracks.

Reference numeral 3 is a clock pit, and drive synchronization is established based on this clock pit. 4 and 5
Is a wobbled pit for detecting a tracking error, which is provided on the inner circumference and the outer circumference of the disc with a displacement of about 1/4 track pit. When the laser spot passes through each wobbled pit, the intensity signal of the reflected light is sampled, and the difference from the track center can be known by taking the difference. Hereinafter, for convenience, 4 will be referred to as wobbled pit A and 5 will be referred to as wobbled pit B.

In the sample servo type optical disc, the area is intermittently set to 1 at the entire circumference of the disc in such a case.
There are about 1500 to 2000 places per lap.

FIG. 2 is a block diagram of the clock controller of the first embodiment. Parts that are not directly related to clock generation,
For example, the tracking error signal generator is the same as the known means, and therefore its description is omitted.

The clock control device, as shown in FIG.
Reflected light intensity signal detection means 11 for detecting the intensity of the reflected light from an optical disc (not shown) and converting it into a reflected light intensity signal (SRF) which is an electric signal, and the reflected light intensity signal (SR).
F) peak is detected and reflected light intensity binarized signal (DSR)
F), and a channel clock generating means 1 for generating a channel clock (CHCLK) based on the reflected light intensity binarized signal (DSRF).
3, a timing signal generating means 14 for generating various timing signals based on the channel clock (CHCLK), an A / D converter 15 for A / D converting the reflected light intensity signal (SRF), A plurality of latches 16 for storing the A / D conversion result of the A / D converter 15
It is composed of a storage means 19 composed of 18 and a comparator 20 for comparing the stored contents of the latches 16-18.

FIG. 3 is a detailed diagram of the waveform shaping means 12 of FIG.

As shown in FIG. 3, the waveform shaping means 12 includes
A differentiating circuit 21 for differentiating the reflected light intensity signal (SRF),
The differential signal from the differentiating circuit 21 is set to zero level (GN
D) and a comparator A22 that generates a binarized signal that becomes H when the level exceeds the zero level, and the reflected light intensity signal (SRF) is compared with a predetermined reference voltage. Comparator B that generates a binarized signal
23, A of comparator A22 and comparator B23
And an AND element 24 that takes ND.

In such a waveform shaping means 12,
Even in the flat portion of the reflected light intensity signal (SRF), many zero crosses are generated in the differential waveform due to noise, so that the output of the comparator A22 changes frequently. On the other hand, when the reflected light intensity signal (SRF) drops due to the pits and the amount of the drop falls below the reference voltage, the reflected light intensity signal (SRF) is input to the negative terminal of the comparator B23.
Output becomes H. However, the rising or falling edge of the binarized signal obtained by the comparator B23 does not represent the center of the pit. Therefore, the output of the comparator A22 and the comparator B23
By ANDing the output with the AND element 24,
The output of the AND element 24 becomes H when the reflected light intensity signal (SRF) is equal to or lower than the reference voltage and the differential signal is positive. That is, the rising edge of the AND element 24 represents the portion where the reflected light intensity signal (SRF) has dropped most, that is, the center of the pit.

FIG. 4 is a detailed diagram of the channel clock generation means 13 of FIG.

As shown in FIG. 4, the channel clock generating means 23 receives the reflected light intensity binarization signal (D) from the timing signal generating means 24 in response to the gate signal (WPAGATE).
AND gate 3 for generating a signal / WPA signal in which only the portion corresponding to the wobbled pit A4 is extracted from (SRF)
1, a phase comparator (PC) 32 for detecting the phase difference between the WPA signal and the reference signal (WPAREF) sent from the timing signal generating means 23, and a delay line (DL) 33. Is equipped with. Similarly, the gate signal (CPGAT) is generated from the timing signal generating means 24.
A signal / CP obtained by extracting only the portion corresponding to the clock pit 3 from the reflected light intensity binarized signal (DSRF) by E).
An AND gate 34 for generating a signal, and a phase comparator (P. 3) for detecting the phase difference between the CP signal and the reference signal (CPREF) sent from the timing signal generating means 23.
C. ) 35 and a delay line (DL) 36. Further, similarly, the timing signal generating means 2
AND gate 37 for generating a signal / WPB signal by extracting only the portion corresponding to the wobbled pit B5 from the reflected light intensity binary signal (DSRF) by the gate signal (WPBGATE) from 4 and the WPB signal and timing signal generation. The reference signal (WPBRE sent from the means 23)
F)) phase detector (PC) 38 for detecting the phase difference
And a delay line (DL) 39.

Further, the channel clock generation means 23 is
A selector (SEL.) 40 that selects any one of the outputs of the three delay lines 33, 36, and 39, and a charge pump (CP) that generates an analog voltage according to the phase shift signal detected by the phase comparator. .) 41 and the PLL
A loop filter (LF) 42 for improving the characteristics of (Phase Locked Loop) and a channel clock (C
VCO (Voltage-Controlled Osc) that generates HCLK
illator) 43.

The operation will be described below with reference to the operation waveforms in FIG. When the light spot passes through the servo area almost right above the track, the reflected light intensity signal (SRF)
Shows a waveform with a large drop, especially in the portion of the clock pit 3, as shown in FIG. When the reflected light intensity binarized signal (DSRF) whose rising edge corresponds to the bottom of the reflected light intensity signal (SRF) is obtained from the differential waveform of this waveform,
A waveform as shown in FIG. 5B is obtained.

On the other hand, from the VCO 43, FIG.
As shown in (3), it is assumed that the channel clock (CHCLK) whose phase is slightly behind the pit position is output.

First, the timing signal generating means 14 outputs a gate signal (WPAGATE), and the AND gate 31 converts the reflected light intensity binarized signal (DSRF) into a reflected light intensity binarized signal corresponding to the wobbled pit A4. A part of (DSRF), for example, a part of pulse a is shown in FIG.
It is extracted as a WPA signal as in (5). The extracted WPA signal is sent from the timing signal generating means 24 and is a reference timing signal (WPAREF) which is a reference timing signal of the wobbled pit A4 generated based on the channel clock (CHCLK) and a phase comparator 32. At, the phase relationships are compared.

The phase comparator 32 outputs a U1 signal indicating that it is necessary to advance the phase of the channel clock (CHCLK) when the detected WPA signal leads the reference signal (WPAREF) in phase. However, in the opposite case, the signal D1 indicating that the phase needs to be delayed is output. In this case, since the WPA signal leads the phase, the U1 signal is output for the time t corresponding to the amount of phase advance as shown in FIG. 5 (7). The D1 signal remains L. These signals are delayed by the delay line 33 for a time corresponding to, for example, about 8 clocks, and are made into the DU1 signal and the DD1 signal. It is necessary that the delay amount here is such that at least the change point due to the phase comparison result of the U1 or D1 signal is after the time when the wobbled pit B5 appears. (Because it is necessary to leave the phase comparison result until the determination is made, delay is applied.) Similarly, the gate signal (CPGATE) is output corresponding to the clock pit 3 and the reflected light intensity binarization corresponding to the clock pit 3 is performed. AND of part of the signal (DSRF)
U2 and D2 are the comparison results extracted by the gate 34 as the CP signal and compared in phase relation with the reference signal (CPREF) which is the reference timing signal by the phase comparator 35.
It is output as a signal. The U2 and D2 signals are delayed by the delay line 36 to become the DU2 and DD2 signals. The amount of delay here is set so that the changed portion of the phase comparison result of the DU2 or DD2 signal becomes substantially the same position as the DU1 and DD1 signals.

Further, in the wobbled pit B5 by the same method, the position of the pit and the channel clock (CH
CLK), the phase difference from the reference signal (WPBREF) which is the reference timing signal generated is detected, and the DU3 and DD3 signals are obtained as the phase comparison result.

The set of DU1 and DD1 signals, the set of DU2 and DD2 signals, and the set of DU3 and DD3 signals thus obtained all represent the phase shift between the channel clock and the pit position on the disc. .

In parallel with the above operation, the reflected light intensity signal (SRF) is sampled by the A / D converter 15 according to the channel clock (CHCLK).
Converted, wobbled pit A4, clock pit 3,
The conversion result at wobbled pit B5 is 16
It is stored in 17 and 18. The latch timing is performed by the timing signal from the timing signal generating means 23 delayed by the delay of A / D conversion with respect to each reference signal. The comparator 20 includes latches 16, 17 ,.
The stored value of 18 is searched for the one holding the minimum value, that is, the deepest modulated one, and the select signal (SEL) corresponding to the latch is output. In this case, since there are three latches, this select signal requires at least 2 bits. As shown in FIG. 5A, since the reflected light intensity signal (SRF) at the clock pit 3 is the smallest, '2' is output as the select signal (SEL) indicating the clock pit 3.

When the select signal (SEL) from the comparator 29 is confirmed, the selector 40 outputs the phase comparison result signals DU1 / DD1, DU2 / DD2, DU3.
One set is selected from / DD3. here,
Since the select signal (SEL) is "2", the phase comparison result / DU2 / DD2 pair in the clock pit is selected. The selected phase information PU and PD are sent to the charge pump 41 and converted into an analog signal according to the sign and magnitude of the phase shift, and the VCO 43 is driven via the loop filter 42 for improving the loop characteristics. The voltage becomes a voltage, and the channel clock (CHCLK) that is the output of the VCO 43 is moved in the direction to eliminate the phase shift. By repeating this operation, the channel clock (CHCLK) synchronized with the pit string on the disc can be obtained.

FIG. 6 shows a case where a light spot passes between tracks, such as during seek. In contrast to FIG. 5, FIG. 6 shows the case where the channel clock leads the pits on the disc. As shown in FIG. 6, when the light spot is between the tracks, a reflected light intensity signal (SRF) that hardly drops in the clock pit 3 portion as shown in FIG. 6A is obtained. Then, in the reflected light intensity binarized signal (DSRF), a pulse corresponding to a clock pit is omitted (FIG. 6 (2)). In binarization, it is necessary to extract the bottom of the reflected light intensity signal (SRF) (the portion corresponding to the center of the pit), so the differential waveform of the reflected light intensity signal (SRF) is compared with the zero level, but only the differential waveform. When the binarization is performed with, the zero cross of the differential signal due to noise or the like occurs in the part without the pit (the flat part of the reflected light intensity signal (SRF)), and the binarized signal is output. The intensity signal (SRF) itself is also compared with a certain reference level, and the reflected light intensity signal (SR
The binary signal of the differential signal is output only when F) is equal to or less than a certain value. For this reason, when the reflected light intensity signal (SRF) is shallowly modulated as shown in FIG. 6A, a dropout occurs in the reflected light intensity binarization signal (DSRF).

Since the reflected light intensity binarization signal (DSRF) corresponding to the clock pit 3 is missing, U2 and D2 which are the phase comparison results at the clock pit 3 are shown in FIG.
5) and (16) are incorrect. However, in the present embodiment, since the phase comparison result at the pit where the reflected light intensity signal (SRF) is the smallest is adopted, the phase comparison result at the wobbled pit A4 (the delay of DU1 and DD1 which are signals) and the channel clock (CHCLK) which is a VCO output is controlled based on the information, so that it is not affected by the omission of the reflected light intensity binary signal (DSRF). Become.

As described above, in this embodiment, the pit positions at the wobbled pit A4, the clock pit 3, and the wobbled pit B5 and the channel clock (CHCLK).
Since the channel clock (CHCLK) is controlled based on the phase comparison result of the pit in which the reflected light intensity signal (SRF) is deeply modulated, which is the most accurate phase comparison result, the pit is always highly accurate. The channel clock (CHCLK) can be synchronized with. In addition, even if the spot during the seek is located just between tracks, even if the reflected light intensity binarization signal (DSRF) in the clock pit (CHCLK) is missing, the accurate phase comparison result can be used to detect the clock. It is possible to control and maintain synchronization.

7 and 8 relate to the second embodiment, and
FIG. 8 is a block diagram showing a configuration of a clock control device, and FIG. 8 is a timing diagram showing timings of respective signals when a light spot passes through a servo area almost right above a track.

The second embodiment is a case where the phase shift between the pit position on the disc and the channel clock is detected by another method.

In FIG. 7, blocks common to FIG. 1 are given the same numbers. In FIG. 7, 21 is a reflected light intensity signal detecting means for detecting the intensity of reflected light from the disc and outputting it as an electric signal, 25 is an A / D converter, 44 is a phase difference between a pit on the disc and a channel clock (CHCLK). Is detected and outputs a value corresponding to the phase difference, 45 is a D / A converter, 42 is a loop filter for improving the characteristics of the PLL, 43 is a VCO, and 46 is a timing signal generating means. .

The phase difference detecting means 44 is A /
Nine latches 51 to 59 for storing the D conversion result, subtractors 60 to 62 for obtaining the phase shift amount between the channel clock and the pit position in each pit, and one of the three subtractor outputs is selected and output. Selector 63, latch 52
It is composed of a comparator 64 which finds one of the stored contents of 55 and 58 which holds the minimum value. Latches 51-5
The timing of 9 is performed by the timing signal from the timing signal generating means 46 delayed by the delay of A / D conversion with respect to each reference signal.

The reflected light intensity signal (SRF) is sampled and A / D converted by the A / D converter 25, and the channel clock (CHCLK) immediately before the wobbled pit A4 is instructed by the timing signal from the timing signal generating means 46. The data is stored in the latches 51 to 59 in order from the sample value at the rising edge of. The latch 59 uses the channel clock (CHCL) immediately after the wobbled pit B.
The sample value at the rising edge of K) will be retained. Here, A / D conversion is performed with 8 bits, and as a result, sample values as shown in FIGS.
It is assumed that the data is stored in 1 to 59. The conversion result is hexadecimal (8
Since it is a bit, it is expressed as OOH ~ FFH), and the larger number indicates the side with more reflected light.

Channel clock (CHCL in each pit
The amount of phase shift between K) and the pit position is the difference between the sample value at the rise of the clock immediately before the pit (the rise immediately before the rise corresponding to the pit) and the sample value at the rise of the clock immediately after the pit. You can know it by taking it. For example, in clock pit 3, the sample value of the immediately preceding clock is FOH and the sample value of the immediately following clock is 80H, so the difference 70H is the amount that represents the phase shift (PE2 in Fig. 8 (12)).
signal). If the clock is ahead of the pit position as shown in FIG. 8, this value will be positive, and if the clock is late, it will be negative. The wobbled pits A4 and B5 can also know the phase shift amount in the same manner, and the wobbled pit A4 has a value of 10H and the wobbled pit BD5E has a value of 90H.

From the three phase comparison results for each pit thus obtained, the phase comparison result for the pit having the smallest sample value of the reflected light intensity signal (SRF) at the pit center is the final phase. It is selected as the comparison result.
In the example of FIG. 8, the sample value (latch 52,
55, 58) are 90H, 50H, and 20H, respectively, and the wobbled pit B5 is the smallest, so the value of PE3 is selected as the phase comparison result and output to the D / A converter 45. To do. The D / A-converted phase shift signal becomes the drive voltage of the VCO 43 via the loop filter 42, and the output channel clock (CHCL
K) is driven in the direction to eliminate the phase shift.

As described above, in the method of detecting the phase difference between the channel clock and the pit position from the value of the reflected light intensity signal sampled at the timing immediately before and after the pit, the reflected light intensity signal (SRF) is also detected. Since the channel clock (CHCLK) is controlled by using the phase shift amount in the pit most deeply modulated, it is possible to always obtain a stable channel clock (CHCLK).

Further, in such a phase difference detection method, when the modulation degree of the reflected light intensity signal is lowered, not only the accuracy of phase comparison is lowered but also the detection gain is lowered, and as a result, the loop gain fluctuates and the PLL is changed. However, according to the synchronizing circuit of the present embodiment, since the phase difference information in the pit having the largest modulation degree is used, it is possible to reduce the variation in the detection gain of the phase difference. It is possible to stabilize the PLL.

9 and 10 relate to the third embodiment, and FIG. 9 is a block diagram showing the configuration of the clock control device, FIG.
FIG. 3 is a circuit diagram showing a configuration of a defect detection circuit.

In the first and second embodiments described above, one of the three phase difference information obtained by the clock pit and the two wobbled pits is selected, but the determination is made based on the level of the reflected light intensity signal. The third embodiment is a clock control device that determines the phase difference information to be selected by another method.

The clock controller of the third embodiment, as shown in FIG. 9, has the A / D converter 25 and the latch 2 shown in FIG.
6 to 28, defect detectors 71 to 73 and a decoder 74 are provided instead of the comparator 29 to select signals (S
EL), and the select signal (S
The operation other than the EL) determination method is the same as in the first embodiment.

As a defect detecting means, a simple one as shown in FIG. 10 can be considered. FIG. 10 shows a defect detection circuit for the wobbled pit A4. A gate signal which becomes active in the vicinity of the wobbled pit A4 is connected to the clock enable terminal, and a reflected light intensity binarized signal (DSRF) which is a binarized signal of the reflected light intensity signal (SRF) is connected to the clock terminal. It is composed of a D flip-flop 80 whose input is connected to a positive power supply. Gate signal (WPAG
If there is a rising edge in the reflected light intensity binarization signal (DSRF) while ATE) is active, / Q
The output defect detection signal (WPADEF) becomes L, and if there is no rise in the gate, the defect detection signal (WPADEF)
PADEF) remains H. When there is a pit defect, the bottom of the reflected light intensity signal does not appear at the pit position and the reflected light intensity binarization signal (DSRF) is not output in many cases, so the pit defect should be detected by the circuit of FIG. You can The / Q output indicates an inverted output of the Q output.

If a similar circuit is prepared for the clock pit 3 and the wobbled pit B5 as well, it is possible to know whether or not there is a defect for each pit (instead of the gate signal (WPAGATE), the gate is used in the clock pit 3). Signal (CPGATE), the gate signal (WPBGATE) in the wobbled pit B, the D flip-flop 80
Connect to the clock enable terminal of.

Which one is selected from the phase shift information obtained in each pit is determined by a signal representing the result of defect detection in each pit, WPADEF, CPDEF, WPBDEF.
The combination is determined by the decoder 74. The operation of the decoder 74 may be to select the last pit among the pits having no defect as shown in the truth table of FIG. 11, for example. This is because the later pits have a shorter delay time from the detection to the use as the final phase difference information, so that the dead time for the PLL is reduced and the operation becomes more stable. When there is no defect in the wobbled pit B5 (WPBDEF = L), the value of the select signal (SEL) is set to 3 so as to use the phase comparison result in the wobbled pit B5. If the wobbled pit B5 has a defect, the select signal (SEL) = 2 is set to select the phase difference information in the clock pit 3, and if the clock pit 3 also has a defect, the wobbled pit A4 The select signal (SEL) = 1 is set so as to select the phase difference information in 1. If the wobbled pit A4 also has a defect, it is regarded as an error and the updating of the phase difference information in the servo area is stopped, and the previous phase difference information is used as it is until the next servo area. Should be done.

The decoder 74 may include a logic circuit that satisfies the following truth table, or may use a ROM.

[0053]

[Table 1] As described above, in the present embodiment, the channel clock (CHC) is calculated by using the phase difference information between the channel clock (CHCLK) and the pit position in the pit which has no pit defect.
Since LK) is controlled, a stable clock can be generated without being affected by pit defects.

Further, by combining the third embodiment with the first or second embodiment, the modulation degree of the reflected light intensity signal (SRF) was the highest among the pits in which no pit defect was detected (the level was low). It is also possible to use the result of phase comparison at the pit.

In the above description, the clock pit and the two wobbled pits were selected as a total of three pits, and one of them was selected. However, other pits that appear at a fixed cycle are provided. The pit can be used for phase comparison. It is also possible to use fewer pits (wobbled pit A, wobbled pit B, etc.).

Further, instead of selecting one from a plurality of phase comparison results and using it for controlling the channel clock, the control can be performed by using the average value thereof.

[0057]

As described above, according to the present invention,
The phase difference between the channel clock and the pit position is detected in the multiple pits provided in the servo area of the sample servo system optical disk, and one of these multiple phase difference information is selected to control the channel clock. Therefore, when the spot diameter is small and the spots are located between the tracks, the reflected light intensity signal cannot be sufficiently modulated in at least one of the plurality of pits provided in the servo area. Even if there is a physical defect in the pit, it is possible to always generate a stable channel clock and prevent out-of-synchronization during tracking servo and seek.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a pit configuration of a servo area of an optical disk of a sample servo system according to a first embodiment.

FIG. 2 is a block diagram showing a configuration of a clock control device according to the first embodiment.

FIG. 3 is a circuit diagram showing a detailed configuration of the waveform shaping circuit of FIG. 2 according to the first embodiment.

FIG. 4 is a circuit diagram showing a detailed configuration of the channel clock generation means of FIG. 2 according to the first embodiment.

FIG. 5 is a timing chart showing the timing of each signal when the light spot according to the first embodiment passes through the servo area almost directly above the track.

FIG. 6 is a timing chart showing the timing of each signal when a light spot passes between tracks, such as during seek according to the first embodiment.

FIG. 7 is a block diagram showing a configuration of a clock control device according to a second embodiment.

FIG. 8 is a timing chart showing the timing of each signal when the light spot according to the second embodiment passes through the servo area almost directly above the track.

FIG. 9 is a block diagram showing a configuration of a clock control device according to a third embodiment.

FIG. 10 is a circuit diagram showing a configuration of a defect detection circuit according to a third embodiment.

[Explanation of symbols]

 3 ... Clock pit 4 ... Wobbled pit A 5 ... Wobbled pit B 11 ... Reflected light intensity signal detection means 12 ... Waveform shaping means 13 ... Channel clock generation means 14 ... Timing signal generation means 15 ... A / D converter 19 ... Storage Means 20 ... Comparator

Claims (5)

[Claims] 1. A light beam is applied to an optical disc having servo areas intermittently provided on an information track, and the intensity of the reflected light from the optical disc is detected. In a clock control device of a sample servo type optical disc device which detects a specific pit among the plurality of pits and generates a channel clock with the pit position as a reference, a pit position in at least two pits of the plurality of pits in the servo area. A phase difference detecting means for independently detecting a timing shift between the channel clock and the channel clock, and a selecting means for selecting and outputting any one of the plurality of phase difference detecting means outputs, and the output of the selecting means A clock control device for an optical disk device, which controls the channel clock based on Place 2. The phase difference detecting means detects a time shift between a pit position reference signal generated based on the channel clock and a pit position obtained from the reflected light intensity. The clock control device for an optical disk device according to claim 1. 3. The phase difference detection means detects a time shift between the pit position and the channel clock based on a difference between the reflected light intensities immediately before and after the pit position. The clock control device for an optical disk device according to claim 1, which is characterized in that. 4. The clock control device for an optical disk device according to claim 1, wherein the selection means determines the output of the phase difference detection means to be selected based on the reflected light intensity at each pit. 5. The selection means determines the phase difference detection means output to be selected based on the output of the defect detection means for determining whether or not each pit has a defect.
The clock control device of the optical disk device according to claim 1.