JP2685478B2 - Information recording / reproducing method, information recording carrier, and information recording / reproducing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention uses a record carrier in which servo areas and data areas are alternately arranged in a track shape, and servo is performed by servo signals intermittently obtained from the servo areas. The present invention relates to an information recording / reproducing method by a sampling servo, which records and reproduces information in a data area by using a radiation beam while performing, and particularly generates a clock signal from a preformatted signal in the servo area, and based on the clock signal. The present invention relates to an information recording / reproducing method by embedded clocking for recording / reproducing information.

The invention also relates to an apparatus for carrying out this method and an information record carrier on which information is recorded and reproduced by the above method.

[Prior Art] Conventionally, in a CD player or an optical disk file device, it has been general to perform light spot control such as tracking and focusing by a continuous control method. On the other hand, recently
An optical disk file system based on a sampling control system has been proposed (hereinafter referred to as a sample servo system). The outline of this method will be described with reference to the drawings. FIG. 2 shows an outline of the sample servo type optical disk 1. 1000 rounds per track in the sample servo method
Each servo segment 4 is divided into a servo area 2 and a data area 3 as shown in FIG. Therefore, in the information recording layer of the optical disk, servo areas and data areas are alternately arranged in a track shape extending in the circumferential direction. In the sample servo system, the tracking signal is provided from the wobble pit row 5 provided in the servo area 2 so as to be distributed to the left and right with respect to the track center 7, and the clock signal is provided in the servo area 2 along the track center. Get from Pit 6. Wobble pit 5 and clock pit 6 are preformatted in the servo area,
Data is recorded / reproduced in / from the data area 3 by using a servo signal and a clock signal intermittently obtained from these pits. In the sample servo method, the data area and servo area are completely separated. Therefore, when recording and reproducing the data pits in the data area, the servo signal is not affected by the interference of the recorded data, so that the servo system is stable, and therefore the optical system can be simplified. References on the sample servo system include pages 165 to 170 of Nikkei Electronics No.410 (December 15, 1986).

[Problems to be Solved by the Invention] Here, the embedded clocking method performed by the sample servo method will be described with reference to FIGS. 3 and 4. FIG. FIG. 4 is a block diagram of an embedded clocking system clocking circuit, and FIG. 3 is a time chart thereof. When the light spot is on the track center 7, a signal such as S1 is obtained by the photodetector (not shown) as the reflected light intensity change. Signal S1
Through the peak detector 10, the peak position of the signal S1, that is, the pit position is output as the signal S2. As an example of a method of realizing the peak detector, there is a method of using a differential circuit. The buried clocking method is a method to embed a temporally N ₁ equal portions N ₁ clocks between two adjacent clock pits 6. Therefore, the pulse signal corresponding to the clock pit 6 from the signal "S1"
S3 is extracted by clock pit extractor 11 and it is PLL circuit 1
2 is used to generate a clock signal S4 having a frequency N ₁ times that and synchronized with the signal S3. The pattern of the pit arrangement in the servo area 2 is a pattern out of modulation that does not appear in the data area 3. In this way, the clock pit extractor 11 can be realized by a method of measuring the passage time between pits and performing pattern matching. PLL circuit 1
The basic configuration of 2 is the same as that of a general frequency synthesizer, and includes a phase comparator 13, a low-pass filter 14, a VCO (voltage controlled oscillator) 15 and a 1 / N ₁ frequency divider (N ₁ is an integer). And the output, N _{1 of the} clock pit pulse S3
A clock signal S4 having a doubled frequency is 1 data segment
4 is equally divided into 1 / N ₁ , and even if there is eccentricity or rotation fluctuation in the disk, one servo block is accurately divided into N equal parts.

The present invention relates to a clocking system in a sample servo system information recording / reproducing method.

An object of the present invention is to record the data pits actually recorded when the data pits are recorded in the data area based on the clock signal generated from the pre-formatted pre-pits like the clock pits in the servo area. Between the position of the additional data pit) and the clock signal,
An information recording / reproducing method capable of accurately reading the write-once data pits based on the clock signal even if a deviation occurs due to an electrical delay of a circuit system, a recording material, a recording condition, etc., an apparatus for implementing this method, and It is to provide an information record carrier on which information is recorded and reproduced by this method.

MEANS FOR SOLVING THE PROBLEM The present invention relates to a first region having at least pre-pits provided in advance at an equal interval in time and in a form capable of being optically detected, and an optical beam by a radiation beam. Using a record carrier in which second areas in which information can be recorded in a detectable form are alternately arranged in a track shape, a clock signal is generated based on the reproduction signal from the prepit, and based on this clock signal. An information signal is recorded in the second area, the clock signal generated based on the reproduction signal from the pre-pit is delayed in charge, and recorded in the second area by using the delayed clock signal. The additional write data pit which is the generated information signal is reproduced.

According to one feature of the present invention, the delay amount is feedback-controlled so that the phase difference between the delayed clock signal and the reproduction signal from the write-once data pit is detected and the phase difference is minimized. According to another feature of the present invention, an additional write synchronization pit is recorded at the beginning of the data pit sequence when the additional write data pit is recorded, and a reproduction signal from the additional write synchronization pit and a reproduction signal from the prepit are recorded during reproduction. Detect the phase difference with the clock signal generated based on
A delay amount that minimizes the phase difference is applied to the clock signal to create a data pit string reproduction clock signal, and the delayed write clock signal is used to reproduce additional write data pits.

When the reproduction signal of the write-once data pit is used for the phase comparison with the clock signal, it is necessary that the reproduction waveform contains the clock component in all or in part.

[Operation] According to the present invention, when the write-once data pits recorded in the second area are played back, the clock signal generated based on the playback signal from the pre-pits is delayed, so that the write-once data pits and the pre-format are formed. The phase difference can be canceled during and the reliability of the additional data pit demodulation can be improved,
Also, the compatibility between the record carrier and the recording / reproducing device can be improved.

[Embodiment] First, prior to the description of an embodiment of the present invention, a problem to be solved by the present invention regarding an embedded clocking system will be described.

In the embedded clocking system, data pits are recorded and reproduced in the second area by using the clock signal generated by the reproduction signal from the pre-pits pre-formatted in the first area. Such problems arise. This will be described with reference to FIG. FIG. 5 shows a reproduced signal waveform when the light spot 41 traces a track having a pit pattern as shown in the uppermost stage, and the signal S1 shows the waveform before the additional write data pit 9 is recorded, and the signal S1 '. Indicates after the write-once data pit is recorded. The pit string indicated by 8 is a preformatted data pit that is formed at the same time as the pits 5 and 6 in the servo area 2 when the disc such as address information is created. In the embedded clocking, the PLL servo system works so that the edge (the rising edge in this example) of the generated clock signal S4 coincides with the peak of the clock pit 6. Since the edge of the clock signal S4 coincides with the center position of the preformatted pits (5, 6, 8), there is no problem in reproducing the preformatted data pit string 8. On the other hand, when recording the data pit 9, the clock signal
Perform with S4. If the write-once pit 9 is written at the timing of the rising edge of the clock signal S4, the center of the actually recorded write-once pit 9 may deviate from the rising edge of the clock S4 by Δt. This Δt
Varies depending on the electrical delay of the circuit system, recording material, recording conditions, and the like. Therefore, the clock signal S4
When the additional write data pit string 9 is reproduced as it is, correct reading is hindered.

It is an object of the present invention to provide an optical disc file system capable of reproducing data correctly even if there is such a deviation Δt between the clock signal and the write-once pit position.

FIG. 6 is a block diagram showing the concept of the present invention, which is characterized in that a clock generating section 200 for additional write data pits is added. By delaying the clock signal S4 generated from the pre-format pit, for example, the clock pit formed in advance in the first area, by the delay circuit 19 by Δt time, the clock shift between the write-once data pit and the pre-format pit is generated. Then, the clock signal S5 for the additional write data pit is obtained, the reproduction signal corresponding to the additional write data pit 9 is extracted from the reproduction signal S1 by the data area extractor 17, and the clock signal S5 is generated by the demodulator 18 for the data pit. The additional write data pit is demodulated by using this. In the present invention, instead of simply applying a fixed delay, the phase comparator 36 detects the phase difference between the write-once pit string and the delayed clock S5, and the delay amount is set so that the difference is minimized. It has feedback control.

FIG. 1 is a diagram showing a schematic configuration of an apparatus for carrying out recording / reproduction according to the present invention. The disc 101 is composed of, for example, a transparent substrate and a recording layer formed thereon, and is rotationally driven by a motor 102. The light spot from the optical head 103 is focused on the recording layer via the transparent substrate. The optical head 103 is configured to be movable in the radial direction of the disc 101.
In the recording layer of the disc 101, virtual tracks extending in the circumferential direction are provided in a spiral shape or a concentric shape, and one track is 1000 to 15 as described in FIG.
It consists of about 00 servo segments 4. As shown in FIG. 3, each servo segment 4 includes a servo area 2 in which wobble pits 5 and clock pits 6 for tracking are preformatted, and a data area 3 in which data pits are recorded by a light spot. . In addition,
As shown in FIG. 5, pits 8 for address information etc.
May be pre-formatted similarly to the pre-pits 5 and 6 of the servo area 2.

In the optical head 103, a light beam from a laser light source 104 made of, for example, a semiconductor laser is collimated by a lens 105 and is focused as a minute spot on the disk 101 by an objective lens 108 via a beam splitter 106 and a mirror 107.

The reflected light from the disc 101 is reflected by the objective lens 108 and the mirror 1.
The beam is separated from the light beam from the light source 104 by the beam splitter 106 via 07, is taken out, is condensed by the lens 109, and is photoelectrically converted by the photodetector 110. The output of the photodetector 110 is amplified by the amplifier 19 to obtain the reproduction signal S ₁ . The reproduction signal S1 is input to the focus shift / track shift signal detection unit 131, and the focus shift and the track shift are intermittently detected at the timing when the light spot passes through the focus shift detection unit and the track shift detection unit in the servo area 2. Then, the detected defocus and track deviation are held to obtain a continuous defocus signal and track deviation signal. As the defocus detection, as described in USP 4,561,082, a method of providing a non-recording area for focusing in the servo area and detecting the defocus in a sampled manner is used. The track deviation is detected by using the fob pit 5 in the servo area. The detection method is SPIE Vol.529 Optical M
ass Strage (1985) pp.84-88 and pp140-144. Since the sample servo method is weak against erroneous samples due to defects, etc., USserial No.72,09
It is preferable to take measures against false sampling as proposed in 5, filed on July 10, 1987.

Further, the reproduction signal S1 is converted by the peak detector 10 into a signal S2 indicating the peak position. The signal S2 is input to the clock pit extractor 11, the pulse signal S3 corresponding to the clock pit 6 is extracted, and input to the PLL circuit 12. PLL
The circuit 12 generates a clock signal S4 having a frequency N ₁ times that of the pulse signal S3 and synchronized with the signal S3. The clock signal S4 is supplied to the modulation circuit 121 and used as a recording clock for the additional write data pits. The modulation circuit 12 supplies a pulse signal corresponding to the recording data to the laser driving circuit 123 at the timing of the clock signal S4, and supplies a recording pulse current corresponding to the recording data to the laser light source 104, so that a data pit is formed in the data area 3. To form. The clock signal S4 is supplied to the preformat section demodulation circuit 113,
It is also used as a playback clock for preformatted pits. The pre-format section extraction circuit 111 uses the reproduction signal S
It is for extracting only the reproduction signal corresponding to the preformat section from 1. It should be noted that the preformatted portion extraction circuit 111 also outputs a gate signal indicating the preformatted portion, and this gate signal is supplied to the modulation circuit 121, and the recording pulse is prohibited from being input to the laser driver 123 during that period. , It is used to prevent additional write data pits from being recorded in the pre-format portion. In the present embodiment, the reproduction signal S1 is supplied to the pre-format portion extraction circuit 111, but if the pre-format is recorded by the pit position method that gives information to the center position of the pit, the peak detector 10 The output signal S2 can be used.

Reference numeral 200 denotes a clock generator for additional write data, which delays the clock signal S4 by Δt time to cancel the phase shift between the additional write data pit recorded in the data area 3 and the clock signal S4, and The reproduction clock S5 is generated. Details of these will be described later. The data approximate area extraction circuit 117 is for extracting a reproduction signal corresponding to the additional write data pit 9 from the reproduction signal S1. When the write-once data pit is recorded by the pit position method, the signal S2 may be used.

Next, with reference to FIG. 7, an embodiment of the clock generating section 200 for additional write data pits will be described. The data clock generation unit 200 of this embodiment is composed of a variable delay element 20 with a tap, a selector 21, a phase comparator 22, 1 / n frequency dividing circuits 23 and 24, and an up / down counter 25. The variable delay element with taps has an output terminal (tap) with a delay time that differs by ΔZ.
Here is an example. In this embodiment, the clock S4 obtained from the PLL circuit 12 is input to the delay element 20 to generate eight clocks each having a phase difference of Δτ.
The clock that most closely matches the phase of the reproduced signal by is selected by the data selector 21 and operates so as to be the output S5. In this embodiment, the write-once data pit 9 is assumed to be recorded by the pit position system as shown in FIG. The pulse signal S6 which has detected the peak of the additional data pit 9 and the signal S5 which is currently selected by the selector 21 are input to the phase comparator 22, and the phase relationship with S5 is compared only when the pulse S6 is input. To be done. Phase comparator
22 has two output terminals, and if the result of the comparison is that it is advanced, one that outputs pulses from the other output terminal is used. . The output of the phase comparator 22 is connected to the up / down counter 25, and the indicated value of the counter 25 is transferred to the data selector 21.
Connect to the select input of. Therefore, due to the output of the phase comparator 22, that is, the delay / advance, the instruction value of the up / down counter 25 changes, and the clock S5 selected by the data selector 21 changes. The frequency dividers 23 and 24 that are inserted between the phase comparator 22 and the up / down counter 25 function as a low-pass filter of one value, and are "advanced".
Alternatively, one output is generated when n "delayed" pulses are generated. By doing so, the clock S5 is prevented from changing excessively due to the influence of noise or the like. Note that 23 and 24 do not necessarily have to be frequency dividers, and, for example, only when pulses of the same polarity (“advance” or “delay”) are continuously obtained by a predetermined number of pulses,
It may be of the type that produces output. FIG. 8 shows a specific example of the phase comparator 22. FIG. 8 (a) is a block diagram of the D type flip-flop 2.
7,28, one-shot multivibrator 29, and AND
It is composed of circuits. 8 (b) and 8
FIG. 8C is a time chart explaining the operation of the circuit of FIG. (B) is the pulse of the write-once data pit
When the phase of clock S5 is ahead of S6,
A pulse is obtained at S11. (C) is the case where the phase of the clock S5 is delayed, and a pulse is obtained at S10. The pulse width of the one-shot multivibrator 29 is clock S5.
Set the length to more than half cycle and less than one cycle.

The above is the description of the first embodiment of the present invention. In this method, if the step width Δτ of the delay element 20 is made fine, precise phase matching is possible. It is also possible to preset a standard corresponding number in the up / down counter 25 in advance so that the optimum delay amount is quickly converged. This preset does not need to be performed very often, and may be performed when the disk is replaced or immediately after access.

The embodiment of FIG. 7 shows an example of the case where a modulation method is used in which the recording pits are written on the optical disc at relatively large intervals with respect to the diameter of the light spot.
FIG. 9 shows a recording method in which the distance between the data pits is relatively smaller than the diameter of the light spot 41, that is, the reproduction signal S1
Above (S14) is shown an embodiment for the case where a modulation method is adopted in which individual pits are not decomposed. An example of such a modulation method is 4-15 modulation. The uppermost row of FIG. 9 shows that additional write data pits 91 to 93 are recorded on the track center line 7, where 91 is a single pit, 92 is a row of 2 consecutive pits, and 93 is 3 pits. The following pit row is shown. In this example, as shown in S12 (solid line) in FIG. 9, two consecutive pit rows 92 and 3
The continuous pit row is for the case where individual pits are not decomposed on the reproduced signal. To reproduce these additional data pit strings, the reproduction clock signal S5
Must have an edge at the center of each pit. To reproduce these write-once data pit sequences, FIG. 10 shows a block diagram of an embodiment of the invention for obtaining the correct data clock signal S5 from these pit sequences. The basic idea is the same as that of the embodiment of FIG. 7, but the difference is that the function of selecting only the single pit 91 from which the clock component is easily extracted from the reproduced waveform S12 is added. . The operation of this embodiment will be described with reference to the time chart of FIG. The signal S12 (analog signal) obtained by extracting only the reproduction signal of the data area by the data area extractor 17 is delayed by the delay element 37 for the time T. This time T is equal to or longer than the time required to identify the single pit 91 or the other, and may be about 1 to 2 clocks. The signal S14 (digital signal) is obtained by peak-detecting the delayed signal S13 by the peak detector 10 '. The signal S14 includes the peak of a single pit as well as the peak of two consecutive pits. For example, since a beak appears in the middle of two consecutive pits, the phase is different from the peak. Therefore, since it is not suitable for clock generation, only the peak of the single pit 91 is selected. This sorting is done with a single pit window generator 38. The selection method includes, for example, a method of binarizing the signal S12 with an appropriate threshold value and measuring the pulse width thereof. That is, if the pulse width is less than or equal to a predetermined width, the single pit 91 is determined. When it is identified as a single pit, a window pulse S15 is generated. AND circuit 3 for signals S14 and S15
By taking the logical product at 9, a signal S16 indicating only the peak position of a single pit is obtained. By inputting the signal S16 to the phase comparator 22 as in FIG. 7, a clock signal S5 in phase with the write-once pit can be obtained. The demodulator 18
The data input of is to take the output of the delay notice 37. Next, another example of the write-once data clock generator will be described with reference to FIG. In this example, without using the delay element 20 as in the embodiment of FIG. 7 or FIG. 10, a clock that is N ₂ times the clock frequency that is actually required is generated by the PLL circuit, and it is 1 / when N ₂ frequency-divided, a method of selecting an optimum from the clock having a frequency division possible N ₂ kinds of phase generated by the timing. Note that N ₂ is 8 in FIG.
And Reference numeral 300 in FIG. 11 is a clock generator for write-once data, which is the same as that in the embodiment of FIGS.
2. In addition to the frequency dividers 23 and 24 and the up / down counter 25, the digital comparator 32 and the counters 33 and 31 are included. The VCO 15 generates a clock having a frequency eight times as high as the clock required as the clock S4, inputs the output to the 3-bit counter 31, and outputs the 1/8 frequency output to 1 / N _{1 of the} PLL _12.
It is returned to the frequency divider 16 and used as the clock signal S4 for preformatting. Also, 1/2 which is the indicated value of the counter 31,
1/4, 1/8 3-bit output is up / down counter 25
Is input to the digital comparator 32 for comparison with the 3-bit output of the above, and the comparator 32 outputs a pulse only at the timing when both inputs become equal. On the other hand, the clock signal of 8 times frequency generated by VCOL15 is also input to the counter 33, and the output of 1/8 frequency division thereof is used as the target clock signal S5. Here, the pulse from the comparator 32 is the counter 33
When it is applied to the load terminal of, the counter 33 is loaded with a preset 3-bit 0, and counting is performed by using it as an initial value. That is, in FIG. 11, the phase is selected by obtaining the timing of dividing the clock by 8 times from the output of the comparator 32. The operation of the phase comparison unit is the same as that of the above-mentioned embodiment. By presetting a value corresponding to the standard phase difference between the signal S4 and the signal S5 in the up / down counter 25, the pull-in time can be shortened.

Since this example does not use a delay element, it can be realized at low cost. Although the number of phases is set to 8, it goes without saying that it can be increased to 16,32.

FIG. 12 is a block diagram of another example of the write-once data clock generator. In this example, a voltage-controlled delay element 34 whose delay amount can be continuously varied is used as a delay element. The clock generator 400 compares the phase of the output S5 from the voltage controlled delay element 34 and the reproduction signal by the write-once data pit with the phase comparator 22, inputs the UP / DOWN output to the charge pump 35, and advances the phase. , Delay is output as an analog signal corresponding to positive and negative voltages. By using the output of the charge pump 35 as a control voltage for the variable delay element 34 after removing the high frequency component by the low pass filter 36, a control system for controlling the delay amount according to the phase difference can be configured. Here, the operating point (center delay amount) of the voltage controlled delay element is preferably set to the standard delay amount.

In this example, since the delay amount can be continuously changed, fine phase matching can be performed.

The clock generators 300 and 40 shown in FIGS.
With respect to 0, the modification in the case of the modulation method as shown in FIG. 9 is also possible.

In the above example, from the reproduction signal itself of the additional write data pit,
By detecting the delay amount of the phase, correcting the phase of the additional write data clock 85, and presetting the standard delay amount in advance, it is possible to accelerate the initial delay amount adjustment time of the additional write data clock S5. As explained, the beginning of the recorded data unit (the beginning of the data sector) when additionally writing data pits
In addition, by recording a short training area or synchronization pattern for initial adjustment of the delay amount (for example, about one pit or several pits), the phase error between the two is detected in the training area, and the error is minimized. Therefore, the read reliability of the write-once data pit can be further improved.

FIG. 13 shows an example of a track structure for explaining the concept. With the sample servo method, 10 to 10
Servo segments 4 of about 0 are combined into one data recording / reproducing unit, that is, a data sector 57, and header information 8 such as a sector address is preformatted as a header block in the data area 3 of the head servo segment 55. deep. Then, each data area 3 in the area 56 consisting of the second or third servo segment in each sector is set as an area in which user data is recorded. In this example, when the additional write data pit 9 is recorded in each data area 3 in the area 56, the additional write data pit 9
Prior to the recording of, for example, an additional write synchronization pit 54 is recorded in the data area 3 of the head servo segment 55 of the data selector 57 as indicated by diagonal lines, and at the time of reproduction, a reproduction signal of this additional write synchronization pit 54 is used, The phase difference from the clock signal S4 is detected, and the clock signal S5 that cancels the phase difference is generated. The additional write data pit 9 is demodulated by the clock signal S5.

FIG. 14 is a block diagram showing the example.
By determining the recording position of the additional write synchronization pit 54 in advance at the end of the header, the additional write synchronization pit 54 can be extracted from the signal S2 after peak detection by the additional write synchronization pit extractor 58. A phase difference detector 59 detects the phase difference Δt between the timing at which the additional write pit 54 appears and the embedded clock signal S4, and the delay amount variable element 19 adjusts the phase of the clock signal S4 so as to minimize the phase difference. As a result, the clock signal S5 whose phase matches the subsequent write-once data pit sequence 9 is obtained. By demodulating the write-once data pits using this clock signal S5, highly reliable data reproduction becomes possible.

The example of FIG. 14 is shown in the block diagram of FIG.
This will be described in detail using the time chart of FIG. First
The circuit configuration will be described with reference to FIG. Playback signal S1 to Fi
The embedded clock signal S4 is obtained in the same manner as g.7. As the clock S5 for additional write data pits, the clock signal S4 is input to the delay element 20 to obtain a large number of clocks S21 having a phase difference of Δτ, and the clock S5 whose phase most matches the additional write data pit row is selected by the selector 21. It is obtained by selecting in. In order to make that selection, in this example, the reproduction timing of the write-once synchronous pit is detected by the sync window generator 50 and the AND circuit 51. here,
A case where one phase is selected from eight different phases will be described. First, the timing of the write-once synchronous pit obtained as the signal S23 sets the latch register 52 to which the clocks of eight different phases are input. This latch register
The output S22 of 52 is determined by the decoder 53 which phase is closer to the additional write synchronization pit, the clock of that number is selected by the selector 21, and is used as the additional write pit clock S5 for demodulating the data signal.

Next, the operation will be described with reference to the time chart of FIG. In FIG. 16, # 0 to # 7 are outputs S21 of the delay element 20, and in this example, one cycle T is divided into eight equal phases Δτ. Here, it is assumed that the additional write synchronization pit 54 appears at the timing shown in the uppermost row of FIG. Note that, in FIG. 16, the size of the additional write synchronization pit 54 is drawn smaller than the clock cycle T for the sake of convenience of the drawing, but in reality, it is about the same as or larger than T. Now, the center point of the pit 54 is detected by the peak detector 10, passes through the window 50, and is input to the clock terminal of the latch register 52. The latch register 52 holds the states of the eight clocks when the rising edge of the signal S23 is input. In this example, # 1 to # 7 hold the value of 11000011,
This is $ C3 in hexadecimal display. In this case, the phase of the write-once pit string is closest to the phase of the clock of # 1 or # 2. Here, it is assumed that the phase of 0 at the point where the value of the latch register 52 changes from 1 to 0 is selected. Therefore,
Input the instruction value of the latch register 52 to the decoder 53,
In the case of the timing shown in the example of FIG. 16, “011” is output from the decoder 53 corresponding to # 2. Then, if the output of the decoder 53 is input to the selector 21, # 2
A clock with this phase is selected and the clock with this phase
Data will be demodulated using S5. In addition,
The duty ratios of the clocks # 0 to # 7 do not necessarily have to be 50%, and T need not be equally divided. For example, the range of the phase etc. Δt with the additional write pit is T
If it is smaller than the above, the range of Δt should be properly divided.

FIG. 17 shows a development of the example of FIG. 15, and its time chart is shown in FIG. Although the basic principle of this example is the same as that of FIG. 15, by using a plurality of delay elements hierarchically, it is possible to perform measurement with fine resolution over the entire range of T. The operation is specified by using the time chart of FIG. In this example as well, the input is the signal indicating the peak timing of the clock signal S4 generated in the PLL system 12 and the additional write synchronization pit, as in FIG.
S23, and the output is the signal S5 obtained by delaying S4 according to the phase shift of the write-once pit. The clock signal S4 is input to the latch register 521 and the delay element 201 as in FIG. 15, and the phase shift information is held at the timing when the latch register 521 is latched by the signal S23. In this example, Δτ ₁ = T / 4, and the latch register 521
The phase shift information with T / 4 accuracy is measured. On the other hand, the delay element 201 is an element that delays with a step width of Δτ _1/2 , and by inverting one of two adjacent output signals and then performing a logical product, Δτ ₁ / 2
Four signals S44 to S47 having a pulse width of By obtaining the logical sum of these four signals by the OR circuit 61, a signal S48 having a cycle of T / 4 = Δτ ₁ is obtained as its output. That is, the delay element 201 and the logic circuits 60 and 61 can obtain a signal having a frequency four times the input frequency.
Then input to the delay element 202 to similarly _{Δτ 2 = Δτ 1/4 =} T / 16 and S48, the phase of three different signal by S51~S53
Generate. By latching these at the same time as the register 521 with the latch register 522 by the timing signal S21, the information of the phase shift with the accuracy of Δτ ₂ is held in the latch register. That is, the latch register 521
In this case, the upper digit information regarding the phase shift amount of the write-once pit is held, and the information held in the latch register 522 corresponds to the lower digit. It will be possible to measure over a range. Specifically, the value of the register 521 is decoded by the decoder 531 and the selector 211 selects the clock signal S211 of the phase for which the phase shift amount with the accuracy of Δτ ₁ should be corrected as in the example of FIG. Next, S211 is input to the delay element 202 'having a step width of Δτ ₂ . On the other hand, the phase shift information of Δτ ₂ precision held in the latch register 522 is decoded by the decoder 532, and the clock S211 corrected at the Δτ ₁ level by the decoded value is ΔΔ
Signals S54 to S56 and S211 4 delayed by τ ₂
One signal is selected from the signals. The signal S5 selected in this manner becomes a clock whose phase shift is corrected with Δτ ₂ accuracy, that is, with accuracy of T / 16. In the present embodiment, by increasing the total number of delay lines, it is possible to easily improve the measurement accuracy, and since all of them can be constituted by digital circuits, there are advantages that they are suitable for integration into an integrated circuit.

In order to select the optimum clock, it is not always necessary to check all the bits, and it is sufficient to detect the position where consecutive 0s change to 1 (or vice versa) in the indicated value of the latch register. Therefore, the decoder 53 is a general ROM (R
ead only Memory). When the ROM is used, any output can be instructed for all combinations of the instruction values of the latch register, so that it is possible to deal with a case where an error in the instruction value of the latch register is taken into consideration. This example is characterized by the fact that the phase matching is possible regardless of the information modulation method, as compared with the example of FIG. In the above, one write-once synchronous pit 54 is shown as an example. However, as shown in FIG. 17, a plurality of (n) write-once synchronous pits are provided and the phase is selected n times to select the phase clock with the highest frequency. It is also preferable to further improve reliability by doing so. Further, a plurality (n) of additional write synchronization pits 54 are provided, and the feedback correction using the up / down counter described in FIGS. 7, 10, 11 and 12 is performed only during the period of the n additional write synchronization pits. It is also possible to select by.

Also, although an example in which an additional write synchronization pit is provided at the beginning of each sector is shown here, an additional write synchronization pit can be provided at the beginning of each segment if the data capacity can be reduced. The process is exactly the same.

[Effect of the Invention] According to the present invention, it is possible to correct the shift between the write-once pit and the clock generated by the embedded clocking method by the feedback loop. According to the first feature,
Since the correction is performed by the average value of a large number of write-once pits, the information is less likely to be affected by the noise of the disc and the circuit, and the information can be reproduced stably and with high accuracy.

Furthermore, according to another feature, a phase difference between the clock signal generated from the pre-formatted pits and the additional write pit row is instantaneously corrected by adding and recording a very small number of synchronization marks immediately before the additional write data. Data can be reproduced with a clock having an optimum phase. Therefore, according to the present invention, the reliability and compatibility of the device can be significantly improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an apparatus for carrying out the recording / reproducing method of the present invention, FIG. 2 is a diagram showing an outline of an optical disk of a sample servo system, and FIG. 3 is a diagram showing an outline of an embedded clocking system. 4, FIG. 4 is a block diagram thereof, FIG. 5 is a diagram for explaining problems of the embedded clocking system, FIG. 6 is a block diagram for explaining the concept of the present invention, and FIG. 7 is for additional write data according to the present invention. FIGS. 8 (a) to 8 (c) are views for explaining an example of the clock generator, FIGS. 9 (a) to 9 (c) are views for explaining the configuration and operation of the phase comparator used in the present invention.
7 is a waveform diagram and a block diagram showing a modified example of FIG. 7 when the modulation system is different, FIG. 11 is a block diagram for explaining another example of the write-once data clock generator, and FIG. 12 is a write-once data. FIG. 13 is a block diagram for explaining another example of a clock generator for use in recording, FIG. 13 is a diagram for explaining an example of a track in which a write-once synchronization pit is recorded on a record carrier of the present invention, and FIG. 14 is for write-once data according to the present invention. FIG. 15 is a block diagram for explaining another example of the clock generator, FIG. 15 is a block diagram showing details thereof, FIG. 16 is its time chart, and FIG.
A block diagram showing details of further development of the example of the figure,
FIG. 18 is a time chart for explaining the operation of FIG. 17, and FIG. 19 is a diagram showing an example of a track format when a plurality of write-once synchronizing pits are provided in the record carrier of the present invention.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Takeuchi 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Saito 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Home Appliances Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuo Takasugi 1-280, Higashi Koikekubo, Kokubunji, Tokyo Metropolitan Research Laboratory, Hitachi, Ltd.

Claims (8)

(57) [Claims] 1. A clock signal is generated based on the timing of a reproduction signal from pre-formatted pre-pits on a recording layer of a record carrier, and an information signal is recorded and reproduced on the recording layer based on the clock signal. An information recording / reproducing method, wherein at least a part of the signal recorded at the time of recording the information signal is separated from the reproduction signal from the recording layer, and based on the phase difference between the clock signal and the separated signal. Generates a data clock that minimizes the phase difference,
An information recording / reproducing method, characterized in that the information signal is demodulated based on the data clock. 2. The information recording / reproducing method according to claim 1, wherein the part of the signals is the information signal. 3. The information recording / reproducing according to claim 1, wherein the part of the signals is a write-once information synchronizing signal recorded prior to the recording of the information signal when the information signal is recorded. Method. 4. A first area having at least pre-pits provided in advance in a form that can be optically detected at equal intervals in time, and information is recorded in a form that can be optically detected by a radiation beam. A record carrier in which the second areas that can be formed are alternately arranged in a track shape, and a clock signal is generated based on a reproduction signal from the prepit, and an information signal is generated in the second area based on the clock signal. Is recorded, the clock signal generated based on the reproduction signal from the pre-pit is delayed by a predetermined amount, and the information signal recorded in the second area is reproduced using the delayed clock signal. An information recording / reproducing method characterized by the above. 5. The phase difference is detected by detecting a phase difference between the delayed clock signal and a reproduced signal from at least a part of the information signal recorded in the second area. 5. The information recording / reproducing method according to claim 4, wherein the feedback control is performed so as to minimize. 6. When recording the information signal, synchronization information is recorded in at least one of the second areas prior to the recording of the information signal, and the number of information signals recorded in the second area is reduced. 6. The information recording / reproducing method according to claim 5, wherein a reproduction signal of the synchronization information is used as a reproduction signal from one part. 7. A method for recording and reproducing information on a record carrier by the information recording / reproducing method according to claim 1 or 4,
Irradiation means for irradiating the record carrier with a radiation beam, means for generating a clock signal by a reproduction signal from a prepit formed on the record carrier, and means for recording an information signal on the record carrier by the clock signal, A means for giving a predetermined amount of delay to the clock signal, and a phase difference between the delayed clock signal and a reproduced signal from at least a part of the information signal is detected to minimize the phase difference. An information recording / reproducing apparatus comprising means for controlling a fixed amount of delay and means for reproducing the information signal by the delayed clock signal. 8. An information record carrier capable of recording and reproducing information by the information recording / reproducing method according to claim 1 or 4, in a form that can be optically detected at equal intervals in time. The first regions having at least pre-pits provided in advance and the second recordings on which the information signals can be recorded in a form optically detectable by the radiation beam are alternately arranged in a track shape, and the second regions are formed. An information record carrier, wherein a part of the area is an area for recording synchronization information prior to recording of the information signal when recording the information signal.