JPH0695683B2 - Jitter suppression mechanism - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a jitter that is superimposed on the transmission frame length in a ring type local area network (LAN) in which each station has an independent clock and transmits line data. It is related to the Jitter suppression mechanism.

[Conventional technology]

Jitter is a fluctuation in the position of a signal pulse or transmission data on the time axis, and is caused by noise generated on a signal line or an internal cause of a device that transmits, receives, or relays signal pulses or data. Is. A conventional technique will be described below by taking as an example a case where a jitter occurs due to the clock of a station transmitting data and the clock of a station receiving data not being synchronized.

FIG. 4 is an explanatory diagram of a system configuration of FDDI-II, which is being standardized by ANSI (American National Standards Institute) as an example of a ring-type LAN in which each station independently has a clock and transmits line data. , (11) in the figure is a ring LAN
(12) is the physical layer of the FDDI-II protocol (hereinafter referred to as PHY), and (13) is
The upper layer above the PHY, (14), is a transmission line connecting each station. In FDDI-II, each station has an independent clock while transmitting packet data and line data. For this data transmission, a transmission frame with a fixed length of 125 μs called a cycle (20) is continuously circulated on the ring. The format of the cycle (20) is AN
It is determined by SI as shown in Fig. 5. In FDDI-II, one bit is 8 ns, and a 40 ns bit sequence having a meaning of 5 bits is called a symbol, and a symbol pair consisting of 2 symbols is called a byte. Therefore, 1 cycle is 125us / 40ns = 3125
It is a symbol, which corresponds to a nominal 3125 symbols (1562.5 bytes). The cycle is divided into three areas. There is a (JK) symbol pair as the SD (start delimiter) (22) at the beginning of the cycle header (21), and the packet and line data in the SDU (service data unit) area (23). Are transmitted, and the preamble area (24) consists of 5 symbols, and each symbol is filled with an idle symbol (I: 5 bit is '1'). Also, Cycle Hedda (21)
And SDU area (23) are 3120 symbols (1560 bytes) in total.

In this system, the clocks of each station are asynchronous and have a frequency error within the allowable range. For this reason, a bit error or duplication occurs due to a quantization error when sampling the data transmitted by the upstream station with the clock of the own station, and a symbol (or byte) is generated due to a quantization error when further converting this to a symbol (or byte). (Byte) is missing or duplicated. In order to protect the transmission data from such a defect, data loss or duplication is controlled by the PHY (12) so that it occurs in the preamble area (24). As a result, the length of the preamble area (24) expands and contracts every time the cycle passes through the station, and the length of the entire cycle also expands and contracts. This is the jitter that is superimposed on the cycle length.
FIG. 6 is a block diagram showing the internal structure of the PHY (12). First, the input serial bit string (31) based on the clock of the upstream station is the elastic buffer (32).
At the station, the clock is sampled by the clock of its own station, but there is a possibility that bit-wise jitter will occur here. Next, the S / P (serial / parallel) converter (33) parallelizes the signals. Since symbols (or bytes) are lost or duplicated in this process, the cycle length jitter at the output of the S / P converter (33) has already been superimposed on the input serial bit string (31) due to the cause before the upstream station. The size is the same as the existing jitter, which is obtained by sampling the reception station and by parallelizing.
In this way, since jitter is added each time the cycle passes through each station, if the number of stations on the ring increases, the data in the SDU area (23) as well as the data in the SDU area (23) will continue to be generated when symbols are missing. May be lost. In order to avoid this, the jitter suppression mechanism (40) is required at the position shown. In the parallelized cycle, the data of the cycle header (21) and the SDU area (23) other than the SD (22) are read, written or exchanged according to the purpose and need in the upper layer (13), and the cycle length is saved. As it is, it returns to PHY (12). The cycle passed from the upper layer (13) is suppressed by the jitter suppression mechanism (40) by the method described later, and then output to the serial bit string (36) by the P / S (parallel / serial) converter (35). It is converted and sent to the downstream station as a cycle (20).

For example, FDDIHYBRID is one of the above-mentioned jitter suppression mechanisms.
In RING CONTROL REV1.0 (X3T9.5, AUGUST 12,1988), a target smoother is proposed, and this standard presupposes processing of symbol width. FIG. 7 is a block diagram showing the structure of this target smoother. In the figure, (40) is the target smoother, and the input symbol string (41) is input to the buffer (42) that can adjust the delay amount in symbol units. It is also input to the control circuit (43). The control circuit (43) applies a control signal (44) to the buffer (42) when the preamble area (24) exists in the buffer (42) and adjusts the delay amount by a method described later to output the output symbol string ( Adjust the cycle length in 45).

Next, referring to FIG. 8 and FIG. 9, the jitter suppression mechanism (40)
A method for suppressing jitter will be described.

FIG. 8 is a view for explaining the internal structure of the buffer (42). In the figure, (B1), (B2), (B3), and (B4) are four buffer elements that store each symbol, and (R
0), (R1), (R2), (R3), and (R4) are routes through which each symbol flows, and (S1), (S2), (S3), and (S4) are route switched by a control signal (44). It is a switch.

FIG. 9 is a flow chart showing the operation of the control circuit (43). Out-ct in the figure is the counter for the number of symbols output as the output symbol string (45), and Hi-ct is the buffer (42).
Current delay amount (in symbol units), Hi-max is buffer (4
2) Maximum delay amount, that is, capacity. In this example, since there are four buffer elements, Hi-max = 4.

Now, the operation will be explained using this flow chart.

Steps (201) to (202) are a buffer initialization process.

Step (201): Buffer initialization is activated by the first SD ((J) symbol) input after reset.

Step (202): Buffer initialization. The delay amount (Hi-ct) of the buffer (42) is initialized to half the maximum delay amount (Hi-max). In this example, Hi-ct = 2. A change in Hi-ct means switching the switch. When Hi-ct = 2, S3
Each symbol connected to the R2 side and input will pass through B1 and B2,
Output through R2.

Steps (203) to (206) are the relay processing of the cycle header (21) and the SDU area (23).

Step (203): The SD (J) symbol is relayed and out
-Count with ct.

Step (204): Step (205) for each symbol input
Perform (206).

Step (205): Relay input symbols, Out-ct
To count.

Step (206): It is judged whether or not the symbol to be input next is in the preamble area (24), and the preamble area (2
If it is 4), the process branches to the pre-ampoule removal process below step (207).

Steps (207) to (212) are preamble deletion processing when there are too many preamble symbols.

Step (207): clear out-ct in preparation for counting the preamble length to be output as the output symbol string (45).

Step (208): The step (209) and subsequent steps are performed for each symbol input of the preamble area (24).

Step (209): It is judged whether or not the input symbol is in the preamble area (24). If the (J) symbol comes, since the (J) symbol belongs to the cycle header area (21) of the next cycle, the process branches to the preamble insertion process of step (213) and below.

Step (210): If the preamble length output as the output symbol sequence (45) has already reached the target value of 5 symbols and the delay amount (Hi-ct) of the buffer (42) can be reduced, the step (211) )I do.

Step (211): Decrease the delay amount (Hi-ct) of the buffer (42) by one symbol. If the previous Hi-ct is changed from 2 to 1 by this process, S2 is connected to the R1 side, and the subsequent symbols are output through B1 and R1. At this time, one symbol of the preamble area (24) in B2 is deleted, and as a result, the output preamble length becomes one symbol shorter.

Step (212): Relay input symbols, out-ct
To count.

FIG. 10 is a diagram showing the state of this symbol removal processing, in which the length of the target smoother (40) in the state of Hi-ct = 2
In this example, a cycle of 3126 symbols is input. Since Hi-ct = 2 in the figure, the symbols are output from B2 from (a) to (e). However, paying attention to (f), although the symbol I ₆ (idle symbol) is input in step (208), it is determined in step (210) that the preamble 5 symbols have already been output, and step (211)
In order to reduce the buffer delay amount (Hi-ct) by 1 symbol, the symbol I _{6 of} B2 is deleted. The subsequent symbols J, K, A, ... Are directly output from B1.

Next, the preamble insertion processing will be described.

Steps (213) to (214) are the process of inserting the primamble.

Step (213): If the preamble length output as the output symbol sequence (45) has not reached the target value of 5 symbols and the delay amount (Hi-ct) of the buffer (42) can be increased, step (214) )I do.

Step (214): Increase the delay amount (Hi-ct) of the buffer (42) by 1 symbol. If the previous Hi-ct is 2, this process will turn it into 3. Therefore, the subsequent symbols are B1, B2,
It will be output via B3 and R3. However, at this time, the symbols in the preamble area (24) in B2 are moved from B2 to B3 and output from R2 at the same time, so that one symbol is duplicated. As a result, the output preamble length becomes one symbol longer.

FIG. 11 is a diagram showing the state of symbol insertion processing, where H
i-ct = 2 target smoother (40) with length 3124
In this example, the symbol cycle is input. Paying attention to (e) in the figure, it is determined that the (J) symbol is input in step (208) and the preamble outputs only 4 symbols in step (213). In step (214), the delay amount (Hi-ct) of the buffer is increased by 1 symbol, so Hi-ct = 3, and I4 is output from R2 and simultaneously moved to B3 and is output again and the symbol I ₄ (idle Symbols) are duplicated. Subsequent symbols J, K, A,
Is output via B1, B2, B3, R3.

Figure 12 shows a target smoother with Hi-max set to 4 (40)
It is a figure which shows the jitter suppression effect by. The horizontal axis is the number of cycles relayed after reset, and the vertical axis is the SD input (output) time and the actual SD input (output) assuming that the input / output force cycle length is constant and the target value is 3125 symbols. ) This is the deviation from the time, which corresponds to the jitter amplitude. The subscripts beside the blot points indicate the input cycle length (indicated in () is the output cycle length).

When the first cycle in the figure is input, Hi-ct is initialized to 2 by the first (J) symbol that is input after reset (B
1 → B2 → R2). Since a cycle having a length of 3126 symbols is input in the state of Hi-ct = 2, a cycle of a length of 3125 symbols is output as a result of the symbol deletion processing, and Hi-ct is reduced to 1 ( B1 → R1). In the second cycle of the figure, since the cycle of length 3126 symbols is input in the state of Hi-ct = 1, the result of the symbol deletion processing is
A cycle of length 3125 symbols is output and Hi-ct is reduced to 0 (R0). In the 3rd and 4th cycles of the figure, since the cycle of length 3126 symbols is input in the state of Hi-ct = 0,
Since the condition of Hi-ct> 0 in step (210) cannot be satisfied (that is, there are no more buffers left), symbol deletion is not executed, 3126 symbols in length are output, and Hi-ct is 0. There is. That is, all the symbols pass through R0 and are output. In the fifth cycle of the figure, since a cycle of length 3124 symbols is input in the state of Hi-ct = 0, the result of the symbol insertion processing is that a cycle of length 3125 symbols is output and Hi-ct is 1 Increase (B1 → R1). Similarly, the target smoother (4
Following the operation of 0), the output jitter is as shown in the figure.

From these results, the target smoother (40) has the effect of reducing the absolute value of its amplitude at the peak point (inflection point) of the input jitter by half the capacity (Hi-max) of the buffer (42). I understand.

[Problems to be Solved by the Invention]

Since the conventional jitter suppressing mechanism as described above processes the symbol width, the circuit operating speed is 40 ns per clock. If a circuit is configured with elements that operate at this speed, there is a problem that power consumption and surface area increase, and the cost also increases. For this purpose, for example, the processing unit may be set to two symbols instead of one symbol, but since the nominal cycle length is an odd number of 3125 symbols, the processing data width is expanded to operate. There was a problem that the speed could not be reduced.

The present invention has been made in order to solve the above problems, and an object thereof is to obtain a jitter suppressing mechanism that can operate at low speed by expanding the processing data width while having the same jitter suppressing effect as the conventional one. To do.

[Means for Solving the Problems]

The jitter suppressing mechanism according to the present invention stores the previously output data length in its control circuit, and selects the target value of the next output data length from the predetermined length or more or the following based on the stored information. It has a means.

[Action]

In the present invention, whether the previously output data length is longer or shorter than a predetermined length (for example, 3125 symbols) is stored, and the target value of the data length to be output next is a predetermined length (contrast to that indicated by the stored information). (3125 symbols) shorter or longer. Therefore, no matter how many symbols the processing data width is, by alternately outputting cycles longer or shorter than 3125 symbols by a fraction obtained by dividing 3125 symbols by the processing data width, the same jitter suppression as in the past can be suppressed. The processing data width can be set to 2 symbols or more while having an effect.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of the present invention.
0) is a jitter suppressing mechanism that performs processing of byte width (2 symbol width), and the input byte string (41) is input to a buffer (42) that can adjust the delay amount in byte units and to a control circuit (43). Is also entered. The control circuit (43) applies a control signal (44) to the buffer (42) when the preamble area (24) exists in the buffer (42) and adjusts the delay amount thereof, so that the cycle in the output byte string (45) Adjust the length. FIG. 2 is a flow chart showing the operation of the control circuit (43), flag is a flag for storing the cycle length output immediately before, and '0' means that it is shorter than 3125 symbols and '1' means 3125. Indicates that the target value T0 is longer than Sibonlu, and the target value T0 is the target value and target value T1 of the preamble length when the cycle length output immediately before is shorter than 3125 symbols.
This is the target value of the preamble length when the cycle length output immediately before is longer than 3125 symbols. Out-ct in the figure is a counter for the number of bytes output as the output byte string (45), H
i-ct is the current delay amount (in bytes) of the buffer (42), H
i-max indicates the maximum delay amount (byte unit) of the buffer (42), that is, the capacity.

The operation of this embodiment will be described with reference to FIG. The internal structure of the buffer (42) is the same as that used in the conventional example, except that each element can process data with a byte width.

Steps (101) to (102) are a buffer initialization process.

Step (101): Buffer initialization is activated by the first SD ((JK) byte) input after reset.

Step (102): Buffer initialization. The delay amount (Hi-ct) of the buffer (42) is initialized to half the maximum delay amount (Hi-max). Also, flag is cleared to 0.

Steps (103) to (106) are the relay processing of the cycle header (21) and the SDU area (23).

Step (103): Relay SD (JK) bytes, Out-c
Count at t.

Step (104): Step (105) (10
6) Do.

Step (105): The input bytes are relayed and counted by out-ct.

Step (106): It is judged whether the byte to be input next is the preamble area (24) and the preamble area (24)
The process branches to the preamble deletion process following the Karaba step (107).

Steps (107) to (112) are preamble deletion processing.

Step (107): Out-ct is cleared in preparation for counting the preamble length in the output byte string (45).

Step (108): The steps following the step (109) are performed for each 1-byte input of the preamble area (24).

Step (109): Judge whether the input byte is in the preamble area (24). Since the (JK) byte belongs to the cycle header area (21), the process branches to the preamble insertion process of step (113) and below.

Step (110): The preamble length output as the output byte string (41) has already reached the target value (T ₀ or T ₁ ) corresponding to the cycle length output immediately before, and the delay of the buffer (42) If the amount (Hi-ct) can be reduced, perform step (111).

Step (111): Decrease the delay amount of the buffer (42) by 1 byte. At this time, 1 byte of the preamble area (24) in the buffer (42) is deleted, and as a result, the output preamble length becomes 1 byte shorter.

Step (112): The input byte is relayed and counted by out-ct.

Steps (113) to (117) are preamble insertion processing.

Step (113): The preamble length output as the output symbol sequence (9) does not reach the target value (T ₀ or T ₁ ) corresponding to the cycle length output immediately before, and the delay amount of the buffer (42) If it is possible to increase, step (114) is performed.

Step (114): Increase the delay amount of the buffer (42) by 1 byte. At this time, the bytes of the preamble area (24) in the buffer (42) are overlapped by 1 byte, so that the output preamble length is increased by 1 byte as a result. The inserted bytes are relayed and counted by out-ct.

Steps (115) to (117): Judge the preamble length output when the insertion of the preamble is completed, and set the flag to '1' if the output cycle length is longer than 3125 symbols, and to '0' if it is shorter. To do.

Next, a specific example will be described.

With T _{0 set} to 3, T ₁ 2 and Hi-max set to 4, this jitter suppression mechanism (4
Let's consider the case where, for example, the cycle of 1562 bytes, 1563 bytes, and 1563 bytes is sequentially input after resetting to 0). First, 1
Since the first input of 1562 bytes is flag = 0 and the target value T ₀ = 3, 1 byte is inserted by the step (113) and output. At this time, Hi-ct = 3 and out-ct = 3. Then, at steps (115) and (116), flag = 1 is set. In the second input of 1563 bytes, flag = 1 and the target value T ₁ is 2, so
One symbol is deleted at steps (110) and (111) and a cycle of 1562 bytes is output, and the Hi-ct at that time becomes 2.
Then, flag = 0 is set in steps (115) and (117).
At the third input of 1563 bytes, flag = 0 and target value T ₀ = 3, so the preamble length does not change and the 1563-byte cycle is output as is, and the Hi-ct at that time remains 2.

FIG. 3 is a diagram showing the effect of suppressing jitter by the jitter suppressing mechanism (40) in which T ₀ 3, T ₁ is 2, and Hi-max is 4. The horizontal axis is the number of cycles relayed after reset, and the horizontal axis is input (output).
This is the deviation between the SD input (output) time and the actual SD input (output) time when assuming a constant force cycle length of 3125 symbols, which corresponds to the jitter amplitude. The subscripts beside the blot points indicate the input cycle length (output cycle length in parentheses) in bytes.

As shown in Fig. 3, this jitter suppression mechanism (4
0) is the effect of reducing the absolute value of the amplitude by half the capacity (Hi-max) of the buffer (42) at the peak point (inflection point) of the input jitter, similar to the conventional one shown in Fig. 12. With.

As described above, in this embodiment, each station has an independent clock, and the ring LA that transmits line data is transmitted.
In the physical layer control unit of N, the jitter suppression mechanism having the variable delay buffer, the flag for storing the transmission frame length output immediately before, and the control circuit having the target value of the transmission frame length to be output next has been described.

Furthermore, the operation is summarized as follows. The jitter suppressing mechanism sets a flag to 0 when the immediately preceding transmission frame is shorter than the nominal transmission frame length, and when the flag is 0, sets the target value of the next transmission frame length to the nominal value. When the transmission frame length is set longer than the transmission frame length and the transmission frame output immediately before is longer than the nominal transmission frame length, the flag in the control circuit is set to 1, and when the flag is 1, the transmission frame length to be output next. The target value of is set shorter than the nominal transmission frame length to suppress the jitter superimposed on the transmission frame length.

Although the flag is cleared to "0" in the buffer initialization in the above embodiment, the effect of suppressing jitter is not changed even if the flag is set to "1".

Further, although the cycle length output immediately before is stored using flag in the above embodiment, the length may be stored without using flag. Further, the history of the previously output length may be stored without being limited to the storage of the immediately preceding one.

In the above embodiment, the case where the processing data width is doubled from the symbol width to the byte width is shown.
The processing data width may be doubled. In this case, 3
Control may be performed so that the average value of the lengths of data, 4 data, etc. approaches a predetermined value (3125 symbols).

Further, in the above embodiment, the case where there are four buffer elements in the buffer is shown, but this number (Hi-max) may be any number.

The configuration of the float chart and buffer shown in the above embodiment is an example, and a buffer having a function of temporarily holding data and a function of adjusting the data length by using this buffer are sufficient.

Further, in the above-mentioned embodiment, the case where the preamble area (24) is added and deleted is shown.
It is shown as an example of idle data added to significant data such as 1) and SDU area (23), and the present invention is applicable to all data when idle data is added to significant data. You can

In the above embodiment, the case where the present invention is applied to the FDDI-II PHY is described. However, other digital PLL (Pha
It can also be used when the average frequency to be output in se lock loop) is not an integral multiple of the digitalization unit.

〔The invention's effect〕

As described above, according to the present invention, the control circuit is provided with means for storing the previously output data length and selectively determining the target value of the data length to be output next. Since the control can be performed so as to have a predetermined value, the processing data width can be widened while waiting for the same jitter suppression effect as in the conventional case, and the control circuit can operate at low speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a jitter suppressing structure according to an embodiment of the present invention, FIG. 2 is a flow chart showing the operation of the control circuit of the same embodiment, and FIG. 3 is a diagram showing the jitter suppressing effect of the same embodiment. , Fig. 4 is an explanatory diagram of the system configuration of a ring LAN in which each station has an independent clock and transmits line data, Fig. 5 is a diagram showing a cycle format which is a transmission frame of the LAN, and Fig. 6 is FIG. 7 is a block diagram showing the internal configuration of the PHY that is the physical layer control unit of the LAN, FIG. 7 is a block diagram showing the configuration of a target smoother that is a conventional jitter suppression configuration, and FIG. 8 is an internal configuration diagram of the buffer. FIG. 9 is a flow chart showing the operation of the control circuit of the conventional jitter suppressing mechanism, FIGS. 10 and 11 are explanatory diagrams showing the processing of the jitter suppressing mechanism, and FIG. 12 is a jitter suppressing effect of the jitter suppressing mechanism. To FIG. In the figure, (40) is a jitter suppression mechanism, (42) is a buffer, and (43) is a control circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A jitter suppressing mechanism having the following elements for adjusting the data length of data composed of predetermined information units to a predetermined length: (a) Significant data consisting of one or more information units and zero. Buffer that inputs and holds data having idle data consisting of more than one information unit, (b) Based on the data length of the previously output data,
Select the target value of the data length from the length above the predetermined length and the length below the predetermined length, and adjust the length of the idle data using the above buffer so that this target value is reached. A control means that approaches the target value.