JP2762803B2 - Cell Flow Controller for Asynchronous Transfer Mode Transmission Network - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer mode (AT).
M) It relates to a cell flow control device for a transmission network.

[0002]

2. Description of the Related Art A synchronous transfer mode is a means for efficiently using an existing communication network for transmitting, exchanging or transferring multimedia information including voice, data and moving picture information (hereinafter sometimes referred to collectively as transmission). (STM) and packet mode are commonly used. The synchronous transfer mode employs time division multiplexing in which time slots are periodically allocated regardless of the presence or absence of information to be transmitted, and a line (channel) having a constant transmission rate is dedicated to one communication. Therefore,
While the transmission rate is fixed throughout one transmission network,
The utilization efficiency for each channel is generally low. These problems are exacerbated in the case of communication in a high-speed broadband communication network, particularly in a wideband ISDN. That is, the type of information to be transmitted increases in response to the high transmission speed of the communication network and the wide frequency band, and the required transmission speeds vary. On the other hand, in the packet mode, information to be sent is divided into blocks, and each block is transferred as a packet with a header in which routing information is written. Since transmission of a packet is performed according to generation of information, the transmission speed can be arbitrarily selected. However, packet mode transfer requires a complicated protocol, and software processing for the execution hinders improvement in transmission speed. This problem becomes a serious constraint when transmitting multimedia information including a large amount of information such as moving image information in real time.

[0003] The ATM, which is an improved packet mode in which the packet is fixed in length and has a unified format with respect to the synchronous transfer mode and the packet mode inevitably including these problems, simplifies the software processing and increases the transmission speed. And therefore high speed LAN
And high-speed broadband communication networks such as broadband ISDN. Therefore, research and development for practical use of ATMs are being vigorously promoted. The above cell in ATM transmission is based on CCITT Recommendation I.3. 150 and I.P. 3
Generally, 61 makes the header length 5 bytes (40 bits) and the information area length 48 bytes (384 bits). ATM employing cell multiplexing based on header information has a high-speed transmission path (link) having a transmission speed of 156 Mbps, for example.
Can greatly change the transmission speed of multimedia information. That is, by employing a self-routing switch that selects a cell transmission path (virtual path or virtual channel) based on header information, ATM
In this case, the switch control is performed in a distributed manner, and the processor for network control is not directly involved in the control, so that high-speed transmission of multimedia information becomes possible.

In order to construct a high-speed broadband communication network for high-speed transmission of multimedia information by ATM, a cell flow control function for limiting a cell flow rate in an ATM layer having a high throughput is essential. That is, if traffic is unevenly distributed as viewed from the entire transmission network, the utilization efficiency of the network is reduced. A cell flow control technique having this purpose is described in U.S. Pat. No. 4,956,839. This cell flow control circuit counts the number of cells transmitted within a predetermined time range based on the header information, and when the number exceeds a predetermined maximum value, the excess cells are counted in the header. Discard it during the conversion process,
The header is converted so that the excess is displayed, and then transferred to the self-routing switch. The switch receiving the excess cells discards the cells according to the traffic in the switch.

[0005]

In such a flow control, since only the above-mentioned maximum value is used as a parameter to determine whether or not the amount is an excess, the flow control is easily affected by traffic fluctuation. In addition to the processing of header information that requires complicated circuit elements for discarding excess cells, high speed is ensured because a part of discarding excess cells depends on the subsequent self-routing switch. Therefore, those self-routing switches adopting a simple circuit configuration are complicated by adding a buffer memory or the like.

SUMMARY OF THE INVENTION It is an object of the present invention to set an upper limit of an allowable cell flow, that is, a parameter defining the detection of the presence or absence of an excess cell, instead of using only the number of cells transmitted within a time range of one length. And a cell flow control device for an ATM transmission network that enables the entire transmission network to flexibly cope with traffic fluctuations by using the number of cells transmitted within an integral multiple of the time range as an additional parameter. Is to do.

It is another object of the present invention to provide a cell flow control apparatus for an ATM transmission network which discards the excess cells independently of the self-routing switch in the ATM transmission network. It is in.

[0008]

SUMMARY OF THE INVENTION A cell flow control device for an ATM transmission network according to the present invention transmits data at an arbitrary time interval through either an input virtual path or an input virtual channel, each having a predetermined number of bits. First means for temporarily accumulating a plurality of incoming ATM cells in the order in which they are transmitted, a first period having a predetermined length and a first period having a length equal to an integral multiple of this length. A second means for generating first and second timing pulses respectively defining a second period, and reading the ATM cell from the first means and outputting the ATM cell to one of an output virtual path, an output virtual channel and a self-routing switch. A first pulse train applied to the first means so as to be transferred and a second pulse train indicating the number of times of reading the ATM cell from the first means. Generating a first count value by counting the pulses of the second pulse train in response to the first timing pulse and generating the first count value within the first period. A fourth means for comparing a first reference value corresponding to the maximum value of the number of cells that can be transferred to the first means and initializing the first means when they match, and responding to the second timing pulse. Counting the number of ATM cells to produce a second count value and a second reference value corresponding to the second count value and the maximum number of cells that can be transferred within the second period. And when they match, a first excess cell detection signal is generated and supplied to the third means, and the third means responds to the first excess cell detection signal to generate the first excess cell detection signal. Average of the maximum value of the number of cells that can be transferred in the second period per the first period Fifth means for controlling the third means so as to generate the first and second pulse trains at corresponding time intervals, and a pulse of the second pulse train in response to the second timing pulse. Counting to generate a third count value, and comparing the third count value with a third reference value corresponding to the maximum value of the number of cells that can be transferred during the second period, and the two match. And a sixth means for generating a second excess cell detection signal and supplying the signal to the third means to stop the generation of the first and second pulse trains.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, a cell flow control apparatus according to an embodiment of the present invention is configured such that a receiving circuit 10 transmitted through a virtual path or virtual channel of a high-speed transmission network and including a synchronization processing circuit and a serial / parallel conversion circuit is used to receive a byte. Several ATM cells converted into parallel input ATM cells INCEL are stored in a FIFO (first-in first
a cell buffer memory circuit 1, a timing control circuit 2, a read pulse control circuit 3, a first excess cell processing circuit 4, a second excess cell processing circuit 5, and a third buffer circuit for temporarily storing data in a (st-out) format The excess cell processing circuit 6 is provided. The cell buffer memory circuit 1 sequentially reads the byte-parallel ATM cells INCEL stored in the FIFO format one by one as byte-parallel output cells OTCEL in response to the read pulse RD. This output cell OT
CEL is a transmission circuit 11 including a parallel-serial conversion circuit.
Is transferred to a transmission path connected to a subsequent node of the transmission network or a self-routing switch functioning as a cross-connect switch. When transferring the output cell OTCEL to this switch, parallel-serial conversion in the transmission circuit 11 is not essential. The timing control circuit 2 generates a first timing signal t1 at a predetermined first cycle (T1).
And a second timing signal t2 generated in a second cycle (T2) equal to an integral multiple of the first cycle (T1).
And the timing signal generation circuit 21 of FIG. In this embodiment, the generation circuit 20 generates, as a timing signal t1, the output of a counter that counts down the 156 Mbps clock CLK to 1/5. Also, the generation circuit 2
1 generates an output of a counter that counts down the clock CLK to 1/50 as a timing signal t2.

The read pulse control circuit 3 reads the buffer memory circuit 1 at the same timing as the input timing of the input cell INCEL during a period when the excess cell detection signal EXS1 is not supplied from the first excess cell processing circuit 4. Sends pulse RD. When the excess cell detection signal EXS1 is supplied from the processing circuit 4, the control circuit 3 reads the read pulse so that the output cell OTCEL is generated at the timing corresponding to the average value per period corresponding to the first cycle (T1). RD is supplied to the buffer memory circuit 1. The delay circuit 30 constituting the control circuit 3 delays the input cell INCEL based on the clock CLK, and generates a delay output signal RDB having a predetermined time width. This signal RD
B is input as a delayed output signal RDB 'to one of a pair of input terminals of the selection circuit through the AND circuit 31 during a period when the third excess cell processing circuit 6 does not generate the excess cell detection signal EXS2. . The selection circuit 32 supplies the signal RDB 'to the second excess cell processing circuit 5 as a delayed read pulse RDA during a period in which the excess cell detection signal EXS1 from the first excess cell processing circuit 4 is not input. I do. The pulse holding circuit 33 receiving the supply of the pulse RDA holds the pulse RDA for one byte-parallel cell (for one cycle of the clock CLK) in response to the clock CLK, and then as a read pulse RD for the buffer memory circuit. Send to 1. The pulse generation circuit 34 divides the frequency of the clock CLK and outputs one pulse RDC for a period that is an integral multiple of the first cycle. This pulse RDC
Is supplied to the pulse generation circuit 34 with a pulse width substantially equal to the read pulses RD and RDA. During a period in which the excess cell detection signal EXS2 from the processing circuit 6 is not supplied, the pair of the selection circuits 32 The other input terminal receives the signal RDC '. The selection circuit 32 outputs the excess cell detection signal EXS from the processing circuit 4.
1 in response to signal RDC 'instead of signal RDB'
Is selected as the read pulse RDA.

The first excess cell processing circuit 4 detects the input cell INCEL every second cycle (T2).
To generate a detection output DET1, the number of which is counted by a cell count circuit 41 to generate a count value CNT1, and the count value and the number of cells that can be transferred within the period of the second cycle (T2). Is compared with a reference value REF1 corresponding to the upper limit value of the excess cell detection signal EXS.
Outputs 1. As is clear from the above description, the detection signal EXS1 indicates that the number of input cells INCEL per the second cycle (T2) has reached a predetermined upper limit. In the excess cell processing circuit 4, the counting circuit 41
Outputs the detection output DET1 to the second timing signal t.
The operation of counting until the supply of 2 is received is repeated, and a count value (strictly, a signal indicating the count value) CNT1 is output for each count operation.

The second excess cell processing circuit 5 reads the read pulse RDA appearing during the first period (T1).
The count value CNT2 is generated by counting the number of cells (preceding the read pulse RD by the time of one byte-parallel cell), and the count value and the number of cells that can be transferred within the period of the first cycle are counted. The count operation is stopped when the reference value REF2 corresponding to the upper limit value is compared, and when both are equal, that is, when the number of times of reading of the cell buffer memory circuit 1 during the period of the first cycle reaches the upper limit value. At the same time, the cell buffer memory circuit 1 is initialized. More specifically, the processing circuit 5 detects the read pulse RDA from the read pulse control circuit 3 to generate a detection signal DET2, and supplies the detection signal DET2 to the first timing signal t1. The counting circuit 51 repeats the operation of counting up to and generating a count value CNT2 (strictly, a signal indicating the count value), and the count value CNT2 and a preset reference value R
EF2, and a comparison circuit 52 for generating a signal S1 indicating that the number of readings of the cell buffer memory circuit 1 within the period of the first cycle has reached the upper limit value when the two become equal. . This signal S1 is held by the pulse holding circuit 53 for the time of one byte-parallel cell, and then becomes a clear signal CLR for initializing the cell buffer memory circuit 1. The signal S1 is supplied to the counting circuit 51.
To the counter circuit 60 of the third excess cell processing circuit 6, which will be described later, as a disable signal.

The third excess cell processing circuit 6 counts the detection output DET2 within the period of the second cycle (T2) as the number of read pulses RDA to generate a count value CNT3,
The count value CNT3 is compared with a reference value REF3 corresponding to the upper limit value of the number of cells that can be transferred within the period of the second period (T2). When both values are equal, the excess cell detection signal EXS2 is controlled. It is supplied to the circuit 3 to stop sending the read pulses RD and RDA to the cell buffer memory circuit 1. More specifically, the processing circuit 6 continuously counts the detection output DET2 from the detection circuit 50 until the second timing signal t2 is input, and counts the count value CNT3.
(Strictly speaking, a signal indicating a count value)
Is provided. This counting operation is continued even if the generation of the detection output DET2 exceeds the upper limit within the period of the first cycle if the signal S1 is supplied as a disable signal. The processing circuit 6 further calculates the count value CNT.
3 is compared with the reference value REF3, and when both are equal, a signal S2 indicating that the number of read times of the cell buffer memory circuit 1 within the period of the second cycle has reached the upper limit value is generated. A circuit 61 and a pulse holding circuit 62 for holding the signal S2 for one byte-parallel cell and then supplying the signal S2 to the control circuit 3 as the excess cell detection signal EXS2.

Next, the operation of this embodiment will be described in more detail with reference to FIG. 2 and FIG. 3, in which the upper limit (M) of the number of cells that can be transferred during the first period T1 is set.
N1) is set to 3, and the upper limit (MN2) in the period of the second cycle T2 is set to 5. The cycle T2 is the cycle T1
10 times as large as When the cycle ratio is set in this manner, the average value (A) of the upper limit of the number of cells that can be transferred within the period of the cycle T1
N) is 0.5. Also, based on these conditions,
The above-mentioned reference values REF1, REF2 and REF3 are preset to 5, 3 and 5, respectively.

The first period T1 defined by the first period T1
In (1), the input cells INCEL (CEL1 and CEL
EL2) is transferred from the cell buffer memory circuit 1 as an output cell OTCEL upon completion of the input (strictly, after a lapse of the time of one byte-parallel cell). In this state, the number of cells transmitted within the period T1 (1) is equal to the upper limit 3 (MN1 =
3), the second excess cell processing circuit 5
, The signal S1 is not generated, so that the selection circuit 32 reads the output signal RDB of the delay circuit 30
Selected as DA. In the next period T1 (2) following the period T1 (1), the input cells INCEL (CE
L3 and CEL4) are the cells CEL1 and CEL2.
In the same manner as described above, immediately after the input is completed, the data is read out and transferred as the output cell OTCEL.

When the input cell INCEL (CEL5) is transmitted to the buffer memory circuit 1 during the period T1 (3), the comparison circuit 4 of the first excess cell processing circuit 4
2 detects that the number of cells has reached 5, and supplies an excess cell detection signal EXS1 to the selection circuit 32. Selection circuit 3
2 selects the output signal RDC of the pulse generation circuit 34 as the read pulse RDA in response to the signal EXS1.
As a result, the input cell CEL5 is read and transferred as the output cell OTCEL at the end of the next period T1 (4). When the read pulse RDA corresponding to the cell CEL5 is generated, the comparison circuit 6 of the third excess cell processing circuit 6
1 detects that the same number of read pulses RDA as the upper limit value 5 (MN2 = 5) of the number of cells that can be transferred during the period T2 (1) has been generated, and thus the excess cell detection signal EXS2
Is supplied to the control circuit 3. The control circuit 3 outputs the signal EX
In response to S2, the generation of the subsequent read pulses RDA and RD is stopped, and the selection circuit 31 has already been switched by the excess cell detection signal EXS1, so that the period T1 (4)
All input cells INCEL (CEL6 and CEL7) transmitted during the period from T1 to T1 (10) are discarded.

A period T2 corresponding to the second cycle T2 which expires at the end of the periods T1 (4) to T1 (10).
First period T1 (11) of period T2 (2) following (1)
In this case, the input cells INCEL (CELs 21, 22, 23 and 24) are continuously transmitted to the buffer memory circuit 1. The cells CEL21, C22, and C23 of the series of cells are transferred as output cells OTCEL immediately after the input to the buffer memory circuit 1 is completed. When the read pulse RDA corresponding to the cell CEL23 is supplied to the processing circuit 5, the comparison circuit 5 receiving the input of the count value CNT2
2 detects that the same number of cells as the upper limit value 3 (MN = 3) of the number of cells that can be transferred per period corresponding to the cycle T1 have already been read from the buffer memory circuit 1, and outputs a clear signal CLR.
Is supplied to the buffer memory circuit 1. Since the buffer memory circuit 1 is initialized in response to the clear signal CLR, the cell CEL which is the last one of the series of input cells is set.
24 are discarded. As described above, in the period T1 (11), the upper limit 3 (MN =
Cell discard is performed based on 3).

At the end of the period T1 (11), the count value CNT1 from the counting circuit 41 indicates the number of cells 4 and the count value CNT3 of the counting circuit 61 indicates 3 read pulses. It does not exceed the upper limit value 5 (MN = 5) of the number of transferable cells in the corresponding period. The above period T1
In the period T1 (12) following (11), the number of cells transmitted in the period corresponding to the period T2 by the comparison circuit 42 can be transferred in the transmitted input cells INCEL (CEL25) within the period. Maximum number of cells 5 (MN2 = 5)
Is reached, and an excess cell detection signal EXS1 is sent to the control circuit 3. In response to this signal EXS1, the selection circuit 32 selects and outputs the output signal RDC from the generation circuit 34 as a read pulse RDA. Therefore, input cell CEL25 is read from buffer memory circuit 1 and transferred at the end of period T1 (12). In addition,
From the period T1 (13) following the period T1 (12) to T1 (2
0), the cell INCEL first input is:
Average value of the number of input cells allowed in the period T2 (2) 0.
Read pulse RD generated at a rate of 5 (AN = 0.5)
Is read from the buffer memory circuit 1 and transferred.

[0019]

As described above, according to the present invention, the cells that can be transferred in the first period (corresponding to the cycle T1) and the second period (corresponding to the cycle T2) that is an integer multiple of the first period and are sufficiently long. The upper limit value (MN1, MN2) of the number and the average value (AN) per the first period are set, and in the case of traffic concentration, the number of discarded cells is transferred by transferring at the upper limit value of the number of transferable cells. Can be reduced. Also,
After the number of transmitted cells reaches the average value, traffic is smoothed by transferring at the average transfer rate, and traffic bias can be avoided.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

FIG. 3 is a timing chart for explaining the operation of the embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 cell buffer memory circuit 2 timing control circuit 3 read pulse control circuit 4 first excess cell processing circuit 5 second excess cell processing circuit 6 third excess cell processing circuit 10 reception circuit 11 transmission circuit

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04L 12/56 H04L 12/28

Claims (5)

(57) [Claims] A plurality of ATM cells each having a predetermined number of bits and transmitted at an arbitrary time interval through one of an input virtual path and an input virtual channel are temporarily stored in the order in which the cells are transmitted. And a first means for defining a first period of a predetermined length and a second period of a length equal to an integer multiple of this length, respectively.
And second means for generating a second timing pulse;
A first pulse train applied to the first means for reading the ATM cell from the first means and transferring the ATM cell to one of an output virtual path, an output virtual channel and a self-routing switch; Third means for generating a second pulse train indicating the number of times the ATM cell has been read; counting the pulses of the second pulse train in response to the first timing pulse to generate a first count value; The first count value is compared with a first reference value corresponding to the maximum value of the number of cells that can be transferred within the first period, and when both match, the first means for initializing the first means is initialized. Means for counting the number of said ATM cells in response to said second timing pulse to produce a second count value and a cell which can be transferred within said second time period and said second count value. Number of The second reference value corresponding to the maximum value is compared with the second reference value, and when they match, a first excess cell detection signal is generated and supplied to the third means, and the third means supplies the first excess cell detection signal to the third means. The first and second pulse trains at a time interval corresponding to an average value of the maximum number of cells that can be transferred within the second period in the first period in response to the minute cell detection signal. Fifth means for controlling the third means to generate; counting the pulses of the second pulse train in response to the second timing pulse to produce a third count value; Is compared with a third reference value corresponding to the maximum value of the number of cells that can be transferred in the second period, and when both match, a second excess cell detection signal is generated. The first and second signals are supplied to the third means.
6. A cell flow control device for an asynchronous transfer mode transmission network, comprising: a sixth means for stopping the generation of the pulse train. 2. The method according to claim 1, wherein said third means includes a plurality of ATMs.
AT in response to the accumulation of cells in said first means, respectively.
First pulse signal generating means for generating an M-cell input pulse train, and a time interval corresponding to an average of the maximum value of the number of cells transferable in the second period per the first period. Second pulse signal generating means for generating an average pulse train; and responding to the first excess cell detection signal, converting the ATM cell input pulse train and the average pulse train into the first and second pulse trains. 2. The cell flow control apparatus for an asynchronous transfer mode transmission network according to claim 1, further comprising: a selection unit that selects the cell flow control as a cell. 3. The first means for counting pulses of the second pulse train to generate the first count value, wherein the fourth means counts pulses of the second pulse train, the first count value and the first reference value. And a first coincidence signal is generated when both are equal.
And the first means in response to the first coincidence signal.
2. The cell flow control apparatus for an asynchronous transfer mode transmission network according to claim 1, further comprising: an initialization signal generating means for generating an initialization signal for initializing said means. 4. The method according to claim 1, wherein the fifth means includes a plurality of ATMs.
Second counting means for counting the number of ATM cells in response to accumulation of the cells in the first means and producing the second count value; and the second count value and the second reference value. 2. A cell flow control apparatus for an asynchronous transfer mode transmission network according to claim 1, further comprising: a second comparing means for comparing the data and when the two become equal to each other, generating the first excess cell detection signal. . 5. The third means for counting the pulses of the second pulse train to generate the third count, wherein the sixth means counts the pulses of the second pulse train, the third count and the third reference value. And third means for producing a second coincidence signal indicating that the two have become equal, and means for producing the second excess cell detection signal in response to the second coincidence signal. The cell flow control device for an asynchronous transfer mode transmission network according to claim 1, wherein the cell flow control device comprises: