JPH0693491B2 - Complementary semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly to a complementary semiconductor integrated circuit device improved to have a latch-up prevention circuit.

[Conventional technology]

Generally, a semiconductor integrated circuit device has a thyristor structure formed parasitically. Therefore, if the thyristor loop is turned on for some reason, a large current continues to flow, and the integrated circuit may be damaged due to melting of the metal wiring such as aluminum or destruction of the P-N junction. This phenomenon is called latch-up and is a very serious problem in the complementary semiconductor integrated circuit device. Therefore, prevention of the latch map phenomenon is an essential item in the complementary semiconductor integrated circuit device.

Generally, this latch-up phenomenon is often triggered by external noise that has entered the input / output pins of the integrated circuit from the outside, and many preventive measures have been devised for the latch-up caused by this external noise. Has been done. However, in a complementary semiconductor integrated circuit device which is operated by supplying three kinds of potentials from the outside, latch-up occurs in the internal circuit due to a special factor other than the above. That is, latch-up occurs depending on the order in which the three types of potentials are supplied (power-on order). Therefore, in this type of semiconductor integrated circuit, measures such as designating the power-on sequence are taken.

[Problems to be Solved by the Invention]

As described above, in the complementary semiconductor integrated circuit device which operates by being supplied with three kinds of potentials, a special factor, namely,
Latch-up may occur depending on how the power-on sequence is selected. This latch-up generation mechanism will be described with reference to the drawings. However, the following description is for a conventional complementary semiconductor integrated circuit device of a so-called P-well type, which is formed by forming a P-type island-shaped region on an n-type substrate, and is Vcc (positive potential), GND, Vs
This is performed for the case where three types of potentials of s (negative potential) are supplied from the outside.

In this case, as shown in FIG. 4, the n-type substrate 1 is inevitably used by connecting it to the positive potential Vcc and the P-type island region (hereinafter referred to as Pul) to the negative potential Vss or GND. .

Therefore, the P well 2 connected to GND and the P well 3 connected to Vss are present on the same substrate. In this case, there is an n ⁺ -type diffusion layer 7 fixed at the Vss potential in the P well 3 and a P ⁺ fixed at the Vcc potential on the n-type substrate.
^{The +} type diffusion layer 8 exists.

Here, for example, consider a case where the potentials are supplied in the order of GND → Vss → Vcc.

First, when the GND potential is fixed and then the Vss potential is fixed, the n-type substrate 1 is not yet fixed to the Vcc potential and is in a floating state. The junction capacitance C1 between the P-well 2 and the n-type substrate 1 and the capacitance between the P-well 3 and the n-type substrate 1 shown in FIG.
Determined by the capacitance division with C2, it becomes the intermediate potential between Vss and GND. At this point, if the potential of the n-type substrate 1 has fallen below the built-in potential of the P-n junction diode D1 formed between the P-well 2 at the GND potential and the n-type substrate 1, this diode D1 will move forward. A large amount of holes are injected from the P well 2 into the n-type substrate 1 by being directionally biased. This hole flows toward the P well 3 having the Vss potential by the bipolar operation. The hole flowing into the P well 3 is P
It flows toward the P ⁺ type diffusion layer 5 for fixing the potential of the well 3, so-called well contact, and raises the P well potential in the vicinity of the n ⁺ type diffusion layer 7. Here, when the P-n junction diode D3 formed by the P well 3 and the n ⁺ type diffusion layer 7 is forward biased, a large amount of electrons are injected into the P well 3. The electrons flow into the n-type substrate 1 by a bipolar operation and are stored in the n-type substrate as it is.

When the Vcc potential is fixed at this point, the excess electrons flow toward the potential fixing n ⁺ type diffusion layer 9 of the n type substrate, so-called sub-contact, and the electron flow causes the P ⁺ type diffusion layer 8 to proceed. When the directional bias is reached, holes are injected from the P ⁺ type diffusion layer 8, the holes flow into the P well 3, and latchup occurs between Vss and Vcc.

[Means for Solving the Problems]

The present invention relates to a complementary semiconductor integrated circuit device that operates by supplying three types of potentials from the outside, and a first n-type drain having the highest potential of the three types of potentials and an intermediate potential as the source.
Type depletion MOS transistor, a first inverter formed between an intermediate potential and a minimum potential for controlling a gate potential of the first n-type depletion MOS transistor, and controlling an input potential of the inverter. A first n-type enhancement MOS transistor having an intermediate potential as a drain, an input of the first inverter as a source, and a maximum potential as a gate, and an input of the first inverter having a drain minimum potential and a source intermediate potential as a gate It is characterized by having a latch-up prevention circuit composed of a second n-type enhancement MOS transistor.

The complementary semiconductor integrated circuit device of the present invention uses a second n-type depletion transistor whose drain-minimum potential is the output of the first inverter, instead of the second n-type enhancement MOS transistor. It is characterized by having been.

The complementary semiconductor integrated circuit device of the present invention is characterized in that a resistor is used between the output of the first inverter and the lowest potential instead of the second n-type enhancement MOS transistor.

〔Example〕

 A first embodiment of the present invention will be described with reference to the drawings.

The explanation is for a P-well type complementary semiconductor integrated circuit device in which a P-well is formed on an n-type substrate, and Vcc (+ 5V), GND
This is performed for the case where three types of potentials (0V) and Vss (-5V) are supplied from the outside.

That is, as shown in FIG. 1, an n-type depletion MOS transistor M1 having Vcc as a drain and GND as a source among three types of potentials, and an n-type depletion MOS transistor M2 for controlling the gate potential of the transistor M1. An inverter formed of an n-type enhancement MOS transistor M3 and a GN for controlling the input potential of this inverter
Latch-up prevention consisting of n-type enhancement transistor M4 with D as drain, inverter input as source, and Vcc as gate, and n-type enhancement MOS transistor M5 with drain as input, Vss as source, and GND as gate Circuit.

The operation and effect of this circuit will be described. However, in this case, the threshold voltage V _T of the n-type depletion transistor is −4V.
Set below. Similar to the above, consider the case where the potentials are supplied in the order of GND → Vss → Vcc. When GND and Vss are supplied, Vcc is floating, and the n-type substrate 1 is V
Attempts to reach an intermediate potential between ss and GND, but M4 is off and M5 is on
Therefore, the potential of the node becomes Vss. Therefore, M2 and M3
The output of the inverter composed of is GND. Therefore M1
Turns on and fixes Vcc to the GND potential. Therefore, the P well 2 of GND potential and the n-type substrate 1 connected to Vcc in FIG. 4 have the same potential, holes are not injected from the P well to the substrate, and latch-up can be prevented. After that, when the Vcc potential is supplied, M4
There ON Suruga, if and where smaller than the ON resistance of M4 in the ON resistance of the M5, the node is the potential [GND-(V _T of M4)]
And the output of the inverter becomes Vss potential. Since V _T of the depletion MOS transistor M1 is set to about −4 V or less, M1 is turned off at this point, and this circuit has no adverse effect at the time when all the potentials are supplied.

FIG. 2 is a circuit diagram of the second embodiment of the present invention, and FIG. 3 is a circuit diagram of the third embodiment of the present invention.

In the circuit of Fig. 1, the M5 transistor uses an n-type enhancement transistor that is always on. Instead of this n-type enhancement transistor, a transistor with a resistance greater than the ON resistance of M4, a resistor, etc. The same result can be obtained by using an n-type depletion MOS transistor having a gate-source short circuit as shown by M6 in FIG. Furthermore, R1 in Fig. 3
Even if it is replaced with a resistor like, the same result can be obtained.

Here, in both cases, when Vcc is supplied and M4 is turned on, it is necessary to set the dimensions and resistance values so that the potential of the node becomes (V _{T of} GND-M4).

〔The invention's effect〕

As described above, according to the present invention, in the complementary semiconductor integrated circuit device that operates by being supplied with three kinds of potentials from the outside, by incorporating the latch-up prevention circuit as described above,
It is possible to prevent the occurrence of latch-up due to the power-on sequence.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a third embodiment of the present invention.
FIG. 4 is a circuit diagram of the embodiment of FIG. 1 ... n type substrate, 2,3 ... P well, 4,5 ... P well potential fixing P ⁺ diffusion layer, 6,7 ...... n ⁺ type diffusion layer, 8 ...... P ⁺ type diffusion layer, 9 …… n ⁺ type diffusion layer for fixing substrate potential, M1, M2, M6 ……
n-type depletion MOS transistor, M3, M4, M5 ...
n-type enhancement MOS transistor, R1 ... Resistor.

Claims (1)

[Claims] 1. In a complementary semiconductor integrated circuit device which operates by supplying three kinds of potentials from the outside, a first n-type depletion using the highest potential of the three kinds of potentials as a drain and an intermediate potential as a source. A MOS transistor, an inverter formed between the intermediate potential and the lowest potential, for controlling the gate potential of the first n-type depletion MOS transistor; a drain of the intermediate potential; a source of the inverter; A first n-type enhancement MOS transistor having a maximum potential as a gate and controlling an input potential of the inverter, and a second n-type enhancement having an input of the inverter as a drain, the minimum potential as a source, and the intermediate potential as a gate. A complementary semiconductor integrated circuit device comprising a MOS transistor.