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JPS58197870A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS58197870A
JPS58197870A JP57079973A JP7997382A JPS58197870A JP S58197870 A JPS58197870 A JP S58197870A JP 57079973 A JP57079973 A JP 57079973A JP 7997382 A JP7997382 A JP 7997382A JP S58197870 A JPS58197870 A JP S58197870A
Authority
JP
Japan
Prior art keywords
output terminal
transistor
latch
semiconductor device
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57079973A
Other languages
Japanese (ja)
Inventor
Yukiya Kamiya
神谷　幸也
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57079973A priority Critical patent/JPS58197870A/en
Publication of JPS58197870A publication Critical patent/JPS58197870A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は相補型ＭＯ８電界効果トランジスタ（以下ＣＭ
Ｏ８と称する）を有する半導体集積回路装置（以下ＩＣ
と称する）に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MO8 field effect transistor (hereinafter referred to as CM
A semiconductor integrated circuit device (hereinafter referred to as IC
(referred to as ).

ＣＭＯ８ｔ−用いたロジックＩＣにおいては隣り合う半
導体領域間の寄生トランジスタによるラッチアップ現象
が問題となっている。Logic ICs using CMO8t- have a problem of latch-up caused by parasitic transistors between adjacent semiconductor regions.

例えば餉１図に示されるこれまでのＣＭＯ８ＩＣにおい
ては、Ｎｉ１８ｉ基板ｌの表面ＫＰ＋拡散層３゜４をソ
ース・ドレインとするＰチャンネルＭＯ８ＦｇＴＱ、　
ｔｌ−形成り、Ｐａｌ［ウェル２１Ｆ）表１１ＫＮ＋拡
散層５．６ｔソース・ドレインとするＮチャネルＭＯ８
ＦＥＴＱ、ｌ−形成してこれらを相補的に接続した構成
な有する。この場合１例えばＱ、の１層４．Ｎ基板１．
Ｐウェル２の間に寄生ラテラル（横形）トランジスタ（
Ｑ、）がオンジ、あるいはＱ、のＮ　層６．Ｐウェル、
Ｎ基板１０間に寄生バーチカル（縦形）トランジスタ（
Ｑ４　）がオンし、このためＱ、側のｖＤＤからＱ！側
の■ｓｓに電流が大量に流れるいわゆるランチアップ現
象な生じている。このラッチアンプの防止の一つの手段
として寄生ラテラルＰＮＰ）ランジスタやバーチカルＮ
ＰＮ　トランジスタのｈＦＥｆ：小さくすることが試み
られているが、このことはＣＭＯ８の特性に影響な与え
ることになり間−がある。For example, in the conventional CMO8IC shown in Figure 1, a P-channel MO8FgTQ with the surface KP + diffusion layer 3°4 of the Ni18i substrate 1 as the source and drain,
tl- formed, Pal [well 21F) Table 11KN+ diffusion layer 5.6t N-channel MO8 as source/drain
It has a configuration in which FETQ and I are formed and connected complementary to each other. In this case, one layer of 1, for example Q, 4. N substrate 1.
A parasitic lateral transistor (
6. P-well,
A parasitic vertical transistor (
Q4) turns on, and therefore Q! from vDD on the Q side. A so-called launch-up phenomenon occurs in which a large amount of current flows through the SS on the side. One way to prevent this latch amplifier is to use a parasitic lateral PNP transistor or vertical N transistor.
Attempts have been made to reduce the hFEf of the PN transistor, but this will have a negative impact on the characteristics of the CMO8.

ラッチアップ現象の他の防止手段として、第２図に示す
ように＊　Ｑｔ　　＃Ｑ＊の周囲にチャネルストッパと
してり／グ状のＮ＋拡散層７．Ｐ＋拡軟層８な設け、こ
れなＶ。Ｄ　”　８８に接続している。As another means for preventing the latch-up phenomenon, as shown in FIG. 2, a groove-shaped N+ diffusion layer 7. is used as a channel stopper around *Qt #Q*. P+ soft layer 8, this is V. D” is connected to 88.

しかしこのような構造としても出力端子−ｖＤＤ間にＰ
−ＮダイオードＤＩ　、出力端子−７８８間にＮ−Ｐダ
イオードＤ、が存在することでこれで出力端子なりＤＤ
、■８８にクランプしているが、この場合第３図で回路
図で示すようにここを流れる電流が寄生、トランジスタ
をトリガすることになり。However, even with this structure, P between the output terminal and vDD
Since there is an N-P diode D between the -N diode DI and the output terminal -788, this becomes the output terminal DD.
, ■ 88, but in this case, as shown in the circuit diagram in Figure 3, the current flowing here becomes parasitic and triggers the transistor.

本質的にラッチアップを防止することは不可能であるこ
とがわかった。It has been found that it is essentially impossible to prevent latch-up.

本発明は上述した問題を解決するべくなされたものであ
り、その目的は耐ラツチアツプのレベルを向上し、それ
によりＩＣの信頼性な向上することにある。The present invention has been made to solve the above-mentioned problems, and its purpose is to improve the level of latchup resistance, thereby improving the reliability of the IC.

第４図は本発明による一実総形ＩＩｉす示すものである
。同図のように本発明では各ＭＯ８Ｆ　Ｅ　Ｔの出力端
子Ｖ：Ｐ−Ｎダイオード、Ｎ−ＰダイオードでｖＤＤ、
■８８にクランプする代りにシｌットキー１１Ｅ　ｔ−
トＳＤ、　　、　８　Ｄ、　テＶＤＩ）、Ｖ８ｓ［り５
７プするものである。これらシ冒ットキーダイオード８
Ｄ、、８Ｄ、はＮ基板、Ｐウェルの表面の一部ＫＡＡ電
極な設けることでシ璽ットキーバリアダイオードを構成
するもので、これらＡ）車底をＶｏＵＴＫＪｉ！続する
。この場合、シロットキーダイオードＳＤ、、８Ｄ、の
順方向電圧ｔＶｆＢＤ、Ｐ−Ｎ、Ｎ−Ｐダイオードの順
方向電圧ｔ”ｆｐとして。FIG. 4 shows a complete form IIi according to the invention. As shown in the figure, in the present invention, the output terminal V of each MO8FET is VDD,
■Instead of clamping to 88, use the shut key 11E t-
SD, , 8 D, VDI), V8s [RI5
7. These exposed key diodes 8
D, , 8D constitute a shutter key barrier diode by providing a part of the surface of the N substrate and P well with a KAA electrode, and these A) VoUTKJi! Continue. In this case, the forward voltage tVfBD of the Sirotkey diodes SD, 8D, and the forward voltage t''fp of the PN, NP diodes.

１Ｖｆｓｏ　ｌ＜ＩＶｆｏ　１ となるようにシ嘗ットキーダイオードの断面積を充分圧
大きくとるようにし、Ｐ−Ｎ、Ｎ−ＰダイオードＤ、、
Ｄ、に順方向電流が流れないようにする。（第５図参照
） このように出力端子をｖＤＤ、■８８に対しシ曹ットキ
ーダイオードでクランプすることにより、ラッチアップ
現象のトリガとなるＰＮＰラテラルトランジスタやＮＰ
Ｎバーチカルトランジスタの動作を阻止することになり
、ラッチアップ現象な防止することができる。The cross-sectional area of the Schottky diode is made sufficiently large so that 1Vfsol<IVfo1, and the P-N, N-P diodes D,...
Prevent forward current from flowing through D. (Refer to Figure 5) By clamping the output terminal with a Schottky diode to vDD,
This prevents the operation of the N vertical transistor, thereby preventing the latch-up phenomenon.

これまでのＣＭＱＩ９１Ｃでは出力端子Ｖ。ＵＴに入る
サージ電圧に対し耐ラツチアツプ電圧は２００〜３００
ｖであるが１本発明のようにシ璽ットキ　　　　ｉ−ク
ランプダイオードを設けることで理論的にはほとんど無
限大に耐ラツチアツプ・レベルを向上することができ、
これによりＩＣ全体の信頼性向上に寄与するＥころは大
である。In the previous CMQI91C, the output terminal was V. The latch-up voltage withstands 200 to 300 against the surge voltage entering the UT.
However, by providing a shut-off i-clamp diode as in the present invention, it is theoretically possible to improve the latch-up resistance level almost infinitely.
As a result, the E roller contributes greatly to improving the reliability of the entire IC.

本発明はＣＭＯ８を用いたロジックＩｃ、ＬＳＩの全て
に適用し５るものである。The present invention is applicable to all logic ICs and LSIs using CMO8.

【図面の簡単な説明】[Brief explanation of drawings]

第１図及び第２図はこれまでのＣＭ　ＯＳ　Ｆ　Ｅ　Ｔ
の構造を示す縦断面図、 ある。 １・・・ＮＭ板、２・・・Ｐウェル、、！、４・・ソー
ス・トレイ／Ｐ”、Ｍ、５８６・・・ソース・ドレイン
Ｎ＋層、７・・・チャネルストッパＮ＋層、訃・・チャ
ネルストッパＰ十ｌ、　ＳＤ、　　、　８Ｄ’、・・・
シ璽ットキーダイオード。 第　　１　　図 第　　３　　図 第４図 第　５ｎ Ｖ′Ｄｒ）Figures 1 and 2 show the previous CM OS FET
A vertical cross-sectional view showing the structure of. 1...NM board, 2...P well,...! , 4... Source tray/P'', M, 586... Source/drain N+ layer, 7... Channel stopper N+ layer, Death... Channel stopper P11, SD, , 8D',...
Shitkey diode. Figure 1 Figure 3 Figure 4 Figure 5n V'Dr)

Claims (1)

【特許請求の範囲】[Claims] １、一つの半導体基板表面の一部に興なる導電蓋ウェル
を形成し、基板側とウェル＠Ｋ１４なるチャネルのＭＯ
８ＦＦｉＴ１に設けて相補的に接続した半導体装置にお
いて、各ＭＯ８ＦＢＴの出力端子をドレイン端子及びソ
ース端子に対しそれぞれクランプするようにシ曹ットキ
ーダイオードな設けたことを特徴とする半導体装置。1. Form a conductive lid well on a part of the surface of one semiconductor substrate, and form a channel MO on the substrate side and well @K14.
1. A semiconductor device provided in an 8FFiT1 and connected complementary to each other, characterized in that a Schottky diode is provided to clamp the output terminal of each MO8FBT to a drain terminal and a source terminal, respectively.
JP57079973A 1982-05-14 1982-05-14 Semiconductor device Pending JPS58197870A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57079973A JPS58197870A (en) 1982-05-14 1982-05-14 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57079973A JPS58197870A (en) 1982-05-14 1982-05-14 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS58197870A true JPS58197870A (en) 1983-11-17

Family

ID=13705263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57079973A Pending JPS58197870A (en) 1982-05-14 1982-05-14 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS58197870A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191371A (en) * 1983-04-14 1984-10-30 Nec Corp Complementary type metal oxide semiconductor field-effect device
EP0166386A2 (en) * 1984-06-29 1986-01-02 Siemens Aktiengesellschaft Integrated circuit of the complementary circuit technique
JPH03501792A (en) * 1987-12-23 1991-04-18 シーメンス、アクチエンゲゼルシヤフト Integrated circuit with “latch-up” protection circuit using complementary MOS circuit technology
EP0838857A2 (en) * 1996-10-22 1998-04-29 International Business Machines Corporation Electrostatic discharge protection device
JP2002016254A (en) * 2000-06-29 2002-01-18 Mitsubishi Electric Corp Semiconductor device
JP2002373943A (en) * 2001-06-14 2002-12-26 Fuji Electric Co Ltd Integrated circuit device for driving flat display device
CN111192548A (en) * 2018-11-14 2020-05-22 罗姆股份有限公司 Driving circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59191371A (en) * 1983-04-14 1984-10-30 Nec Corp Complementary type metal oxide semiconductor field-effect device
JPH0313754B2 (en) * 1983-04-14 1991-02-25 Nippon Electric Co
EP0166386A2 (en) * 1984-06-29 1986-01-02 Siemens Aktiengesellschaft Integrated circuit of the complementary circuit technique
JPH03501792A (en) * 1987-12-23 1991-04-18 シーメンス、アクチエンゲゼルシヤフト Integrated circuit with “latch-up” protection circuit using complementary MOS circuit technology
EP0838857A2 (en) * 1996-10-22 1998-04-29 International Business Machines Corporation Electrostatic discharge protection device
EP0838857A3 (en) * 1996-10-22 2000-08-02 International Business Machines Corporation Electrostatic discharge protection device
JP2002016254A (en) * 2000-06-29 2002-01-18 Mitsubishi Electric Corp Semiconductor device
JP4607291B2 (en) * 2000-06-29 2011-01-05 三菱電機株式会社 Semiconductor device
JP2002373943A (en) * 2001-06-14 2002-12-26 Fuji Electric Co Ltd Integrated circuit device for driving flat display device
CN111192548A (en) * 2018-11-14 2020-05-22 罗姆股份有限公司 Driving circuit
JP2020080500A (en) * 2018-11-14 2020-05-28 ローム株式会社 Driver circuit

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